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61909cc8 |
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19-Jan-2024 |
Wenkai Lin <linwenkai6@hisilicon.com> |
crypto: hisilicon - Fix smp_processor_id() warnings Switch to raw_smp_processor_id() to prevent a number of warnings from kernel debugging. We do not care about preemption here, as the CPU number is only used as a poor mans load balancing or device selection. If preemption happens during an encrypt/decrypt operation a small performance hit will occur but everything will continue to work, so just ignore it. This commit is similar to e7a9b05ca4 ("crypto: cavium - Fix smp_processor_id() warnings"). [ 7538.874350] BUG: using smp_processor_id() in preemptible [00000000] code: af_alg06/8438 [ 7538.874368] caller is debug_smp_processor_id+0x1c/0x28 [ 7538.874373] CPU: 50 PID: 8438 Comm: af_alg06 Kdump: loaded Not tainted 5.10.0.pc+ #18 [ 7538.874377] Call trace: [ 7538.874387] dump_backtrace+0x0/0x210 [ 7538.874389] show_stack+0x2c/0x38 [ 7538.874392] dump_stack+0x110/0x164 [ 7538.874394] check_preemption_disabled+0xf4/0x108 [ 7538.874396] debug_smp_processor_id+0x1c/0x28 [ 7538.874406] sec_create_qps+0x24/0xe8 [hisi_sec2] [ 7538.874408] sec_ctx_base_init+0x20/0x4d8 [hisi_sec2] [ 7538.874411] sec_aead_ctx_init+0x68/0x180 [hisi_sec2] [ 7538.874413] sec_aead_sha256_ctx_init+0x28/0x38 [hisi_sec2] [ 7538.874421] crypto_aead_init_tfm+0x54/0x68 [ 7538.874423] crypto_create_tfm_node+0x6c/0x110 [ 7538.874424] crypto_alloc_tfm_node+0x74/0x288 [ 7538.874426] crypto_alloc_aead+0x40/0x50 [ 7538.874431] aead_bind+0x50/0xd0 [ 7538.874433] alg_bind+0x94/0x148 [ 7538.874439] __sys_bind+0x98/0x118 [ 7538.874441] __arm64_sys_bind+0x28/0x38 [ 7538.874445] do_el0_svc+0x88/0x258 [ 7538.874447] el0_svc+0x1c/0x28 [ 7538.874449] el0_sync_handler+0x8c/0xb8 [ 7538.874452] el0_sync+0x148/0x180 Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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2ff0ad84 |
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02-Dec-2023 |
Zhiqi Song <songzhiqi1@huawei.com> |
crypto: hisilicon/zip - save capability registers in probe process Pre-store the valid value of the zip alg support related capability register in hisi_zip_qm_init(), which will be called by hisi_zip_probe(). It can reduce the number of capability register queries and avoid obtaining incorrect values in abnormal scenarios, such as reset failed and the memory space disabled. Fixes: db700974b69d ("crypto: hisilicon/zip - support zip capability") Signed-off-by: Zhiqi Song <songzhiqi1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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f76f0d7f |
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02-Dec-2023 |
Wenkai Lin <linwenkai6@hisilicon.com> |
crypto: hisilicon/qm - add a function to set qm algs Extract a public function to set qm algs and remove the similar code for setting qm algs in each module. Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com> Signed-off-by: Hao Fang <fanghao11@huawei.com> Signed-off-by: Zhiqi Song <songzhiqi1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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a9864bae |
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23-Nov-2023 |
Chenghai Huang <huangchenghai2@huawei.com> |
crypto: hisilicon/zip - add zip comp high perf mode configuration To meet specific application scenarios, the function of switching between the high performance mode and the high compression mode is added. Use the perf_mode=0/1 configuration to set the compression high perf mode, 0(default, high compression mode), 1(high performance mode). These two modes only apply to the compression direction and are compatible with software algorithm in both directions. Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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a61fb707 |
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28-Oct-2023 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - remove incorrect type cast The 'offset' type is unsigned long in 'struct debugfs_reg32', so type of values casts to unsigned long long is incorrect, and the values do not require type cast, remove them. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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b42ab1c6 |
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28-Sep-2023 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - check function qp num before alg register When the Kunpeng accelerator executes tasks such as encryption and decryption have minimum requirements on the number of device queues. If the number of queues does not meet the requirement, the process initialization will fail. Therefore, the driver checks the number of queues on the device before registering the algorithm. If the number does not meet the requirements, the driver does not register the algorithm to crypto subsystem, the device is still added to the qm_list. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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5831fc1f |
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28-Sep-2023 |
Longfang Liu <liulongfang@huawei.com> |
crypto: hisilicon/qm - fix PF queue parameter issue If the queue isolation feature is enabled, the number of queues supported by the device changes. When PF is enabled using the current default number of queues, the default number of queues may be greater than the number supported by the device. As a result, the PF fails to be bound to the driver. After modification, if queue isolation feature is enabled, when the default queue parameter is greater than the number supported by the device, the number of enabled queues will be changed to the number supported by the device, so that the PF and driver can be properly bound. Fixes: 8bbecfb402f7 ("crypto: hisilicon/qm - add queue isolation support for Kunpeng930") Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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1a9e6f59 |
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14-Sep-2023 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - remove zlib and gzip Remove the support of zlib-deflate and gzip. Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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aa3f8050 |
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14-Sep-2023 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - support deflate algorithm Add the deflate algorithm support for hisilicon zip hardware. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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f69ef19f |
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07-Mar-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
crypto: hisilicon/zip - remove unnecessary aer.h include <linux/aer.h> is unused, so remove it. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Yang Shen <shenyang39@huawei.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Nick Terrell <terrelln@fb.com> Acked-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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b40b62ed |
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11-Nov-2022 |
Kai Ye <yekai13@huawei.com> |
crypto: hisilicon/qm - modify the process of regs dfx The last register logic and different register logic are combined. Use "u32" instead of 'int' in the regs function input parameter to simplify some checks. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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d310dc25 |
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09-Sep-2022 |
Zhiqi Song <songzhiqi1@huawei.com> |
crypto: hisilicon - support get algs by the capability register The value of qm algorithm can change dynamically according to the value of the capability register. Add xxx_set_qm_algs() function to obtain the algs that the hardware device supported from the capability register and set them into usr mode attribute files. Signed-off-by: Zhiqi Song <songzhiqi1@huawei.com> Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com> Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
db700974 |
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09-Sep-2022 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/zip - support zip capability Add function 'hisi_zip_alg_support' to get device configuration information from capability registers, instead of determining whether to register an algorithm based on hardware platform's version. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
d90fab0d |
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09-Sep-2022 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - get error type from hardware registers Hardware V3 and later versions support get error type from registers. To be compatible with later hardware versions, get error type from registers instead of fixed marco. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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129a9f34 |
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09-Sep-2022 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - get qp num and depth from hardware registers Hardware V3 and later versions can obtain qp num and depth supported by the hardware from registers. To be compatible with later hardware versions, get qp num and depth from registers instead of fixed marcos. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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82f00b24 |
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09-Sep-2022 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - get hardware features from hardware registers Before hardware V3, hardwares do not provide the feature registers, driver resolves hardware differences based on the hardware version. As a result, the driver does not support the new hardware. Hardware V3 and later versions support to obtain hardware features, such as power-gating management and doorbell isolation, through the hardware registers. To be compatible with later hardware versions, the features of the current device is obtained by reading the hardware registers instead of the hardware version. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
6d9a8995 |
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13-Aug-2022 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - some misc cleanup Some cleanup for code: 1. Change names for easy to understand. 2. Unify the variables type. 3. Use the right return value. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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3099fc9c |
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09-Jun-2022 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - move alloc qm->wq to qm.c Before stopping the function, the driver needs to flush all the remaining work about event irq. Therefore, accelerator drivers use a private workqueue(qm->wq) to handle event irq instead of the system workqueue. This patch moves alloc workqueue from sec_main.c and zip_main.c to qm.c. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
5bfabd50 |
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09-Apr-2022 |
Kai Ye <yekai13@huawei.com> |
crypto: hisilicon/zip - support last word dumping 1. Add some debugging registers. 2. Add last word dumping function during zip engine controller reset. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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9b0c97df |
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09-Apr-2022 |
Kai Ye <yekai13@huawei.com> |
crypto: hisilicon/zip - support register checking The value of the register is changed after the task running. A debugfs file node is added to help users to check the change of register values. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
442fbc09 |
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08-Mar-2022 |
Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> |
hisi_acc_vfio_pci: Add helper to retrieve the struct pci_driver struct pci_driver pointer is an input into the pci_iov_get_pf_drvdata(). Introduce helpers to retrieve the ACC PF dev struct pci_driver pointers as we use this in ACC vfio migration driver. Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Acked-by: Kai Ye <yekai13@huawei.com> Acked-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Link: https://lore.kernel.org/r/20220308184902.2242-7-shameerali.kolothum.thodi@huawei.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
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#
fae74fea |
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08-Mar-2022 |
Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> |
hisi_acc_qm: Move VF PCI device IDs to common header Move the PCI Device IDs of HiSilicon ACC VF devices to a common header and also use a uniform naming convention. This will be useful when we introduce the vfio PCI HiSilicon ACC live migration driver in subsequent patches. Cc: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Acked-by: Longfang Liu <liulongfang@huawei.com> Acked-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h Link: https://lore.kernel.org/r/20220308184902.2242-4-shameerali.kolothum.thodi@huawei.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
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223a41f5 |
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13-Dec-2021 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - add new algorithms for uacce device Enable deflate/lz77_zstd algorithm for uacce device on Kunpeng930. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
808957ba |
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11-Dec-2021 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - enable ssid for sva sgl For Kunpeng 920, the bit 0 of register 'HZIP_SGL_RUSER_32_63' stand for whether the ssid is valid. So this bit should be set as valid for sva mode. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
376a5c3c |
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19-Nov-2021 |
Kai Ye <yekai13@huawei.com> |
crypto: hisilicon - modify the value of engine type rate Modify the value of type rate from new QM spec. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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6e96dbe7 |
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20-Sep-2021 |
Colin Ian King <colin.king@canonical.com> |
crypto: hisilicon/zip - Fix spelling mistake "COMSUMED" -> "CONSUMED" There is a spelling mistake in a literal string. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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74f5edbf |
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13-Aug-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon - change parameter passing of debugfs function To avoid repeatedly obtaining 'qm' from 'filp', parameter passing of debugfs function directly use 'qm' instead of 'filp'. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
607c191b |
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13-Aug-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon - support runtime PM for accelerator device Add runtime PM support for Kunpeng930 accelerator device. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
1295292d |
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13-Aug-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon - using 'debugfs_create_file' instead of 'debugfs_create_regset32' The accelerator devices support runtime PM, when device is in suspended, an exception will occur if reading registers. Therefore, this patch uses 'debugfs_create_file' instead of 'debugfs_create_regset32' to create debugfs file, and then the driver can get the device status before reading the register. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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ed5fa39f |
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07-Aug-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon - enable zip device clock gating Kunpeng930 zip device supports dynamic clock gating. When executing tasks, the algorithm core is opened, and when idle, the algorithm core is closed. This patch enables zip dynamic clock gating by writing hardware registers. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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38a9eb81 |
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11-Jun-2021 |
Kai Ye <yekai13@huawei.com> |
crypto: hisilicon/zip - adds the max shaper type rate The ZIP driver support configure each function's QoS in the Host for Kunpeng930. The ZIP driver needs to configure the maximum shaper type rate. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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a5c164b1 |
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22-May-2021 |
Longfang Liu <liulongfang@huawei.com> |
crypto: hisilicon/qm - support address prefetching Kunpeng930 hardware supports address prefetching to improve performance before doing tasks in SVA scenario. This patch enables this function in device initialization by writing hardware registers. In the process of reset, address prefetching is disabled to avoid the failure of interaction between accelerator device and SMMU. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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b7da13d0 |
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15-May-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - enable to close master ooo when NFE occurs Kunpeng930 could be able to close master ooo when NFE occurs, which will disable memory accessing from device and execute tasks. This ensures that errors do not spread. This patch enables the hardware to close master ooo when an error occurs by writing hardware registers, and ensures that the driver will not drain qp because the hardware will empty the tasks automatically. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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3b9c24de |
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15-May-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - adjust order of device error configuration In order to avoid reporting an exception but the error type is not configured, the driver needs to configure the error type first, and then enable the error interrupt. Before executing the task, hardware error initialization is needed so that the hardware can detect the error in time. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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b7220a74 |
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12-Apr-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon - support new error types for ZIP Kunpeng930 ZIP adds 'zip_axi_poison_err' 'zip_sva_err' and 'QM_ACC_DO_TASK_TIMEOUT' hardware error types. This patch enables the error types and configures the error types as NFE. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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d9e21600 |
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12-Apr-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon - dynamic configuration 'err_info' 'err_info' does not support dynamic configuration since it is const type. Therefore, in order to support new error type later, 'err_info' is changed to dynamic configuration. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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c4392b46 |
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20-Mar-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - move 'CURRENT_QM' code to qm.c Since the code related to 'CURRENT_QM' debugfs is exactly same in sec/hpre/zip driver, move 'CURRENT_QM' to qm.c to reduce duplicate code. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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45bb26d9 |
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20-Mar-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - set the total number of queues Move the configuration of the total number of queues 'ctrl_qp_num' from sec2/hpre/zip to qm.c. And get the total number of queues from the hardware register for Kunpeng930. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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1db0016e |
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05-Feb-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - do not reset hardware when CE happens There is no need to reset hardware when Corrected Error(CE) happens. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
3e9954fe |
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05-Feb-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - removing driver after reset Add waiting logic for resetting as removing driver, otherwise call trace will occur due to releasing resource. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
cc3292d1 |
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04-Feb-2021 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon - PASID fixed on Kunpeng 930 Enable PASID by setting 'sqc' and 'cqc' pasid bits per queue in Kunpeng 930. For Kunpeng 920, PASID is effective for all queues once set in SVA scenarios. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
f8408d2b |
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04-Jan-2021 |
Kai Ye <yekai13@huawei.com> |
crypto: hisilicon - add ZIP device using mode parameter Add 'uacce_mode' parameter for ZIP, which can be set as 0(default) or 1. '0' means ZIP is only registered to kernel crypto, and '1' means it's registered to both kernel crypto and UACCE. Signed-off-by: Kai Ye <yekai13@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
1dc44035 |
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13-Nov-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - add a work_queue for zip irq The patch 'irqchip/gic-v3-its: Balance initial LPI affinity across CPUs' set the IRQ to an uncentain CPU. If an IRQ is bound to the CPU used by the thread which is sending request, the throughput will be just half. So allocate a 'work_queue' and set as 'WQ_UNBOUND' to do the back half work on some different CPUS. Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
a8ff38bd |
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31-Oct-2020 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - modify the return type of debugfs interface Since 'qm_create_debugfs_file' always returns 0, change it as 'void'. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
2fcb4cc3 |
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25-Sep-2020 |
Sihang Chen <chensihang1@hisilicon.com> |
crypto: hisilicon/zip - fix the uninitalized 'curr_qm_qp_num' The 'qm->curr_qm_qp_num' is not initialized, which will result in failure to write the current_q file. Signed-off-by: Sihang Chen <chensihang1@hisilicon.com> Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
698f9523 |
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25-Sep-2020 |
Hao Fang <fanghao11@huawei.com> |
crypto: hisilicon/zip - fix the uncleared debug registers ZIP debug registers aren't cleared even if its driver is removed, so add a clearing operation when remove driver. Signed-off-by: Hao Fang <fanghao11@huawei.com> Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
d8140b87 |
|
19-Sep-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/qm - fix wrong return type of 'pci_get_drvdata' The parameter type of 'pci_set_drvdata' is 'struct hisi_qm', so here the return type of 'pci_get_drvdata' should be 'struct hisi_qm' too. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
0542a941 |
|
10-Sep-2020 |
Longfang Liu <liulongfang@huawei.com> |
crypto: hisilicon - update ZIP module parameter description In order to pass kernel CRYPTO test, ZIP module parameter 'pf_q_num' needs to be set as greater than 1. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
2ca73193 |
|
07-Sep-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - fix some coding styles 1.Unified alignment styles 2.Remove unnecessary goto branch 3.Remove address printf Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
2a928693 |
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07-Sep-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - supplement some comments Supplement some comments. Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
b1a25820 |
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07-Sep-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - add print for error branch Add print for some error branches. Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
533b2079 |
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07-Sep-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - replace 'sprintf' with 'scnprintf' Replace 'sprintf' with 'scnprintf' to avoid overrun. Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
4b33f057 |
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07-Sep-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon/zip - modify debugfs interface parameters Update debugfs interface parameters Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
15b0694f |
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07-Sep-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - unify naming style for functions and macros 1.Add prefix 'HZIP' for some macros 2.Add prefix 'hisi_zip' for some functions Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
70af3e7e |
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07-Sep-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/zip - remove some useless parameters 1.Remove the macro 'HZIP_VF_NUM'. 2.Remove 'list' of the struct 'hisi_zip' Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
3d29e98d |
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15-Aug-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/qm - fix the process of register algorithms to crypto When the devices are removed or not existing, the corresponding algorithms which are registered by 'hisi-zip' driver can't be used. Move 'hisi_zip_register_to_crypto' from 'hisi_zip_init' to 'hisi_zip_probe'. The algorithms will be registered to crypto only when there is device bind on the driver. And when the devices are removed, the algorithms will be unregistered. In the previous process, the function 'xxx_register_to_crypto' need a lock and a static variable to judge if the registration is the first time. Move this action into the function 'hisi_qm_alg_register'. Each device will call 'hisi_qm_alg_register' to add itself to qm list in probe process and registering algs when the qm list is empty. Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
daa31783 |
|
15-Aug-2020 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon/qm - fix the call trace when unbind device Call trace will appear in the Hisilicon crypto driver unbinding or disabling SRIOV during task running with TFMs on the corresponding function. The log looks like this: [ 293.908078] Call trace: [ 293.908080] __queue_work+0x494/0x548 [ 293.908081] queue_work_on+0x84/0xd8 [ 293.908092] qm_irq+0x4c/0xd0 [hisi_qm] [ 293.908096] __handle_irq_event_percpu+0x74/0x2a0 [ 293.908098] handle_irq_event_percpu+0x40/0x98 [ 293.908099] handle_irq_event+0x4c/0x80 [ 293.908101] handle_fasteoi_irq+0xb0/0x170 [ 293.908102] generic_handle_irq+0x3c/0x58 [ 293.908103] __handle_domain_irq+0x68/0xc0 [ 293.908104] gic_handle_irq+0xb4/0x298 [ 293.908105] el1_irq+0xcc/0x180 [ 293.908107] arch_cpu_idle+0x38/0x228 [ 293.908110] default_idle_call+0x20/0x40 [ 293.908113] do_idle+0x1cc/0x2b8 [ 293.908114] cpu_startup_entry+0x2c/0x30 [ 293.908115] rest_init+0xdc/0xe8 [ 293.908117] arch_call_rest_init+0x14/0x1c [ 293.908117] start_kernel+0x490/0x4c4 This patch adds a waiting logic as user doing the above two operations to avoid panic. The two operations will hold on in the driver remove function until the tasks release all their relative TFMs. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
64dfe495 |
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15-Aug-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/qm - register callback function to 'pci_driver.shutdown' Since the drivers such as HPRE/SEC/ZIP do not implement 'pci_driver.shutdow', a RAS will be triggered at OS rebooting or shutting down as the hardware device is processing request. The log looks like this: NOTICE: [NimbusSecNodeType1]:[2372L]This is sec, Base = 0x141800000 NOTICE: [NimbusSecHandle]:[2319L] SecIntSt = 0x3 NOTICE: [NimbusSecHandle]:[2320L] SecQmIntStatus = 0x2 NOTICE: [PrintSecurityType]:[344L] SecurityType is RECOVERABLE! This patch offers a new API in qm to shutdown devices, and add shutdown callbacks in ACC driver based on this new API. So the running devices will be stopped when the OS reboot or shutdown. Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
e88dd6e1 |
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15-Aug-2020 |
Yang Shen <shenyang39@huawei.com> |
crypto: hisilicon/qm - fix no stop reason when use 'hisi_qm_stop' Now, there are three reasons of stopping: 'NORMAL', 'SOFT_RESET' and 'FLR'. In order to keep this, explicitly pass the stop reason as an input parameter of 'hisi_qm_stop' function. Fixes: b67202e8ed30("crypto: hisilicon/qm - add state machine for QM") Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
813ec3f1 |
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05-Jul-2020 |
Barry Song <song.bao.hua@hisilicon.com> |
crypto: hisilicon/zip - permit users to specify NUMA node If users don't specify NUMA node, the driver will use the ZIP module near the CPU allocating acomp. Otherwise, it uses the ZIP module according to the requirement of users. Cc: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
58ca0060 |
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20-May-2020 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon - fix driver compatibility issue with different versions of devices In order to be compatible with devices of different versions, V1 in the accelerator driver is now isolated, and other versions are the previous V2 processing flow. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
c31dc9fe |
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15-May-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon/qm - add DebugFS for xQC and xQE dump Add dump information of SQC/CQC/EQC/AEQC/SQE/CQE/EQE/AEQE. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
6621e649 |
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15-May-2020 |
Longfang Liu <liulongfang@huawei.com> |
crypto: hisilicon/zip - add debugfs for Hisilicon ZIP Hisilicon ZIP engine driver uses debugfs to provides IO operation debug information Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
3176637a |
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09-May-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - remove codes of directly report device errors through MSI The hardware device can be configured to report directly through MSI, but this method will not go through RAS, configure all hardware errors that should be processed by driver to NFE. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
d9701f8d |
|
09-May-2020 |
Weili Qian <qianweili@huawei.com> |
crypto: hisilicon - unify initial value assignment into QM Some initial value assignment of struct hisi_qm could put into QM. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
b977e030 |
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09-May-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - remove use_dma_api related codes The codes related use_dma_api is useless which should be removed. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
7ce396fa |
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09-May-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - add FLR support Add callback reset_prepare and reset_done in QM, The callback reset_prepare will uninit device error configuration and stop the QM, the callback reset_done will init the device error configuration and restart the QM. Uninit the error configuration will disable device block master OOO when Multi-bit ECC error occurs to avoid the request of FLR will not return. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
20b291f5 |
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09-May-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - refactor module parameter pf_q_num related code put q_num_set similar code into qm to reduce the redundancy. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
cfd66a66 |
|
09-May-2020 |
Longfang Liu <liulongfang@huawei.com> |
crypto: hisilicon/zip - modify the ZIP probe process Misc fixes on coding style: 1.Merge QM initialization code into a function 2.Merge QM's PF and VF initialization into a function Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
8f68659b |
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08-May-2020 |
Rikard Falkeborn <rikard.falkeborn@gmail.com> |
crypto: hisilicon/zip - constify struct debugfs_reg32 hzip_dfx_regs is never changed and can be made const. This allows the compiler to put it in the text section instead of the data section. Before: text data bss dec hex filename 15236 6160 480 21876 5574 drivers/crypto/hisilicon/zip/zip_main.o After: text data bss dec hex filename 15620 5776 480 21876 5574 drivers/crypto/hisilicon/zip/zip_main.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
84c9b780 |
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03-Apr-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon/zip - add controller reset support for zip Register controller reset handle with PCIe AER. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
35ee280f |
|
02-Apr-2020 |
Hao Fang <fanghao11@huawei.com> |
crypto: hisilicon - add vfs_num module parameter for hpre/sec The vfs_num module parameter has been used in zip driver, this patch adds this for HPRE and SEC driver. Signed-off-by: Hao Fang <fanghao11@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
#
cd1b7ae3 |
|
02-Apr-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - unify SR-IOV related codes into QM Clean the duplicate SR-IOV related codes, put all into qm.c. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
619e464a |
|
02-Apr-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - put vfs_num into struct hisi_qm We plan to move vfs_num related code into qm.c, put the param vfs_num into struct hisi_qm first. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
18f1ab3f |
|
10-Mar-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon/zip - Use hisi_qm_alloc_qps_node() when init ctx Encapsulate hisi_qm_alloc_qps_node() to new interface to replace find_zip_device(), which will fix the bug of creating QP failure especially in multi-thread scenario. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
9e00df71 |
|
11-Feb-2020 |
Zhangfei Gao <zhangfei.gao@linaro.org> |
crypto: hisilicon - register zip engine to uacce Register qm to uacce framework for user crypto driver Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
#
18bead70 |
|
11-Feb-2020 |
Zhangfei Gao <zhangfei.gao@linaro.org> |
crypto: hisilicon - Remove module_param uacce_mode Remove the module_param uacce_mode, which is not used currently. Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
f826e6ef |
|
20-Jan-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - Unify error detect process into qm In error detect process, a lot of duplicate code can put into qm. We add two callback(get_dev_hw_err_status and log_dev_hw_err) into struct hisi_qm_err_ini to handle device error detect, meanwhile the qm error detect not changed. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
de3daf4b |
|
20-Jan-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - Configure zip RAS error type Configure zip RAS error type in error handle initialization, Where ECC 1bit is configured as CE error, others are NFE. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
eaebf4c3 |
|
20-Jan-2020 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - Unify hardware error init/uninit into QM The initialization and uninitialization of zip/hpre/sec/qm hardware error is processed in respective drivers, which could be unified into qm.c. We add struct hisi_qm_err_ini into struct hisi_qm, which involve all error handlers of device and assignment should be done in driver probe. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
#
4a97bfc7 |
|
07-Nov-2019 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
crypto: hisilicon - no need to check return value of debugfs_create functions When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
#
39977f4b |
|
06-Nov-2019 |
Hao Fang <fanghao11@huawei.com> |
crypto: hisilicon - add vfs_num module param for zip Currently the VF can be enabled only through sysfs interface after module loaded, but this also needs to be done when the module loaded in some scenarios. This patch adds module param vfs_num, adds hisi_zip_sriov_enable() in probe, and also adjusts the position of probe. Signed-off-by: Hao Fang <fanghao11@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
5c2d6a52 |
|
07-Nov-2019 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
crypto: hisilicon: no need to check return value of debugfs_create functions When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/20191107085200.GB1274176@kroah.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
1e67ee93 |
|
01-Nov-2019 |
Zhou Wang <wangzhou1@hisilicon.com> |
crypto: hisilicon - replace #ifdef with IS_ENABLED for CONFIG_NUMA Replace #ifdef CONFIG_NUMA with IS_ENABLED(CONFIG_NUMA) to fix kbuild error. Fixes: 700f7d0d29c7 ("crypto: hisilicon - fix to return...") Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Reported-by: kbuild test robot <lkp@intel.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
#
700f7d0d |
|
25-Oct-2019 |
Zhou Wang <wangzhou1@hisilicon.com> |
crypto: hisilicon - fix to return sub-optimal device when best device has no qps Currently find_zip_device() finds zip device which has the min NUMA distance with current CPU. This patch modifies find_zip_device to return sub-optimal device when best device has no qps. This patch sorts all devices by NUMA distance, then finds the best zip device which has free qp. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
#
719181f3 |
|
21-Oct-2019 |
Shukun Tan <tanshukun1@huawei.com> |
crypto: hisilicon - fix param should be static when not external. This patch fixes following sparse warning: zip_main.c:87:1: warning: symbol 'hisi_zip_list' was not declared. Should it be static? zip_main.c:88:1: warning: symbol 'hisi_zip_list_lock' was not declared. Should it be static? zip_main.c:948:68: warning: Using plain integer as NULL pointer Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
#
ee1788c6 |
|
21-Oct-2019 |
Zhou Wang <wangzhou1@hisilicon.com> |
crypto: hisilicon - tiny fix about QM/ZIP error callback print Tiny fix to make QM/ZIP error callback print clear and right. If one version hardware does not support error handling, we directly print this. And QM is embedded in ZIP, we can use ZIP print only, so remove unnecessary QM print. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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bf6a7a5a |
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19-Sep-2019 |
Arnd Bergmann <arnd@arndb.de> |
crypto: hisilicon - avoid unused function warning The only caller of hisi_zip_vf_q_assign() is hidden in an #ifdef, so the function causes a warning when CONFIG_PCI_IOV is disabled: drivers/crypto/hisilicon/zip/zip_main.c:740:12: error: unused function 'hisi_zip_vf_q_assign' [-Werror,-Wunused-function] Replace the #ifdef with an IS_ENABLED() check that leads to the function being dropped based on the configuration. Fixes: 79e09f30eeba ("crypto: hisilicon - add SRIOV support for ZIP") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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72c7a68d |
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02-Aug-2019 |
Zhou Wang <wangzhou1@hisilicon.com> |
crypto: hisilicon - add debugfs for ZIP and QM HiSilicon ZIP engine driver uses debugfs to provide debug information, the usage can be found in /Documentation/ABI/testing/debugfs-hisi-zip. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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79e09f30 |
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02-Aug-2019 |
Zhou Wang <wangzhou1@hisilicon.com> |
crypto: hisilicon - add SRIOV support for ZIP HiSilicon ZIP engine supports PCI SRIOV. This patch enable this feature. User can enable VFs and pass through them to VM, same ZIP driver can work in VM to provide ZLIB and GZIP algorithm by crypto acomp interface. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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62c455ca |
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02-Aug-2019 |
Zhou Wang <wangzhou1@hisilicon.com> |
crypto: hisilicon - add HiSilicon ZIP accelerator support The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It uses Hisilicon QM as the interface to the CPU. This patch provides PCIe driver to the accelerator and registers it to crypto acomp interface. It also uses sgl as data input/output interface. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Kenneth Lee <liguozhu@hisilicon.com> Signed-off-by: Hao Fang <fanghao11@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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