1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PCIe host controller driver for Texas Instruments Keystone SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments., Ltd. 6 * https://www.ti.com 7 * 8 * Author: Murali Karicheri <m-karicheri2@ti.com> 9 * Implementation based on pci-exynos.c and pcie-designware.c 10 */ 11 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/gpio/consumer.h> 15#include <linux/init.h> 16#include <linux/interrupt.h> 17#include <linux/irqchip/chained_irq.h> 18#include <linux/irqdomain.h> 19#include <linux/mfd/syscon.h> 20#include <linux/msi.h> 21#include <linux/of.h> 22#include <linux/of_irq.h> 23#include <linux/of_pci.h> 24#include <linux/phy/phy.h> 25#include <linux/platform_device.h> 26#include <linux/regmap.h> 27#include <linux/resource.h> 28#include <linux/signal.h> 29 30#include "../../pci.h" 31#include "pcie-designware.h" 32 33#define PCIE_VENDORID_MASK 0xffff 34#define PCIE_DEVICEID_SHIFT 16 35 36/* Application registers */ 37#define CMD_STATUS 0x004 38#define LTSSM_EN_VAL BIT(0) 39#define OB_XLAT_EN_VAL BIT(1) 40#define DBI_CS2 BIT(5) 41 42#define CFG_SETUP 0x008 43#define CFG_BUS(x) (((x) & 0xff) << 16) 44#define CFG_DEVICE(x) (((x) & 0x1f) << 8) 45#define CFG_FUNC(x) ((x) & 0x7) 46#define CFG_TYPE1 BIT(24) 47 48#define OB_SIZE 0x030 49#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) 50#define OB_OFFSET_HI(n) (0x204 + (8 * (n))) 51#define OB_ENABLEN BIT(0) 52#define OB_WIN_SIZE 8 /* 8MB */ 53 54#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) 55#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) 56#define PCIE_EP_IRQ_SET 0x64 57#define PCIE_EP_IRQ_CLR 0x68 58#define INT_ENABLE BIT(0) 59 60/* IRQ register defines */ 61#define IRQ_EOI 0x050 62 63#define MSI_IRQ 0x054 64#define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) 65#define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) 66#define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) 67#define MSI_IRQ_OFFSET 4 68 69#define IRQ_STATUS(n) (0x184 + ((n) << 4)) 70#define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) 71#define INTx_EN BIT(0) 72 73#define ERR_IRQ_STATUS 0x1c4 74#define ERR_IRQ_ENABLE_SET 0x1c8 75#define ERR_AER BIT(5) /* ECRC error */ 76#define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ 77#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ 78#define ERR_CORR BIT(3) /* Correctable error */ 79#define ERR_NONFATAL BIT(2) /* Non-fatal error */ 80#define ERR_FATAL BIT(1) /* Fatal error */ 81#define ERR_SYS BIT(0) /* System error */ 82#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ 83 ERR_NONFATAL | ERR_FATAL | ERR_SYS) 84 85/* PCIE controller device IDs */ 86#define PCIE_RC_K2HK 0xb008 87#define PCIE_RC_K2E 0xb009 88#define PCIE_RC_K2L 0xb00a 89#define PCIE_RC_K2G 0xb00b 90 91#define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) 92#define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) 93 94#define EP 0x0 95#define LEG_EP 0x1 96#define RC 0x2 97 98#define KS_PCIE_SYSCLOCKOUTEN BIT(0) 99 100#define AM654_PCIE_DEV_TYPE_MASK 0x3 101#define AM654_WIN_SIZE SZ_64K 102 103#define APP_ADDR_SPACE_0 (16 * SZ_1K) 104 105#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 106 107struct ks_pcie_of_data { 108 enum dw_pcie_device_mode mode; 109 const struct dw_pcie_host_ops *host_ops; 110 const struct dw_pcie_ep_ops *ep_ops; 111 u32 version; 112}; 113 114struct keystone_pcie { 115 struct dw_pcie *pci; 116 /* PCI Device ID */ 117 u32 device_id; 118 int intx_host_irqs[PCI_NUM_INTX]; 119 120 int msi_host_irq; 121 int num_lanes; 122 u32 num_viewport; 123 struct phy **phy; 124 struct device_link **link; 125 struct device_node *msi_intc_np; 126 struct irq_domain *intx_irq_domain; 127 struct device_node *np; 128 129 /* Application register space */ 130 void __iomem *va_app_base; /* DT 1st resource */ 131 struct resource app; 132 bool is_am6; 133}; 134 135static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) 136{ 137 return readl(ks_pcie->va_app_base + offset); 138} 139 140static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, 141 u32 val) 142{ 143 writel(val, ks_pcie->va_app_base + offset); 144} 145 146static void ks_pcie_msi_irq_ack(struct irq_data *data) 147{ 148 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 149 struct keystone_pcie *ks_pcie; 150 u32 irq = data->hwirq; 151 struct dw_pcie *pci; 152 u32 reg_offset; 153 u32 bit_pos; 154 155 pci = to_dw_pcie_from_pp(pp); 156 ks_pcie = to_keystone_pcie(pci); 157 158 reg_offset = irq % 8; 159 bit_pos = irq >> 3; 160 161 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), 162 BIT(bit_pos)); 163 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); 164} 165 166static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 167{ 168 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 169 struct keystone_pcie *ks_pcie; 170 struct dw_pcie *pci; 171 u64 msi_target; 172 173 pci = to_dw_pcie_from_pp(pp); 174 ks_pcie = to_keystone_pcie(pci); 175 176 msi_target = ks_pcie->app.start + MSI_IRQ; 177 msg->address_lo = lower_32_bits(msi_target); 178 msg->address_hi = upper_32_bits(msi_target); 179 msg->data = data->hwirq; 180 181 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 182 (int)data->hwirq, msg->address_hi, msg->address_lo); 183} 184 185static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, 186 const struct cpumask *mask, bool force) 187{ 188 return -EINVAL; 189} 190 191static void ks_pcie_msi_mask(struct irq_data *data) 192{ 193 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 194 struct keystone_pcie *ks_pcie; 195 u32 irq = data->hwirq; 196 struct dw_pcie *pci; 197 unsigned long flags; 198 u32 reg_offset; 199 u32 bit_pos; 200 201 raw_spin_lock_irqsave(&pp->lock, flags); 202 203 pci = to_dw_pcie_from_pp(pp); 204 ks_pcie = to_keystone_pcie(pci); 205 206 reg_offset = irq % 8; 207 bit_pos = irq >> 3; 208 209 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), 210 BIT(bit_pos)); 211 212 raw_spin_unlock_irqrestore(&pp->lock, flags); 213} 214 215static void ks_pcie_msi_unmask(struct irq_data *data) 216{ 217 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 218 struct keystone_pcie *ks_pcie; 219 u32 irq = data->hwirq; 220 struct dw_pcie *pci; 221 unsigned long flags; 222 u32 reg_offset; 223 u32 bit_pos; 224 225 raw_spin_lock_irqsave(&pp->lock, flags); 226 227 pci = to_dw_pcie_from_pp(pp); 228 ks_pcie = to_keystone_pcie(pci); 229 230 reg_offset = irq % 8; 231 bit_pos = irq >> 3; 232 233 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), 234 BIT(bit_pos)); 235 236 raw_spin_unlock_irqrestore(&pp->lock, flags); 237} 238 239static struct irq_chip ks_pcie_msi_irq_chip = { 240 .name = "KEYSTONE-PCI-MSI", 241 .irq_ack = ks_pcie_msi_irq_ack, 242 .irq_compose_msi_msg = ks_pcie_compose_msi_msg, 243 .irq_set_affinity = ks_pcie_msi_set_affinity, 244 .irq_mask = ks_pcie_msi_mask, 245 .irq_unmask = ks_pcie_msi_unmask, 246}; 247 248static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) 249{ 250 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; 251 return dw_pcie_allocate_domains(pp); 252} 253 254static void ks_pcie_handle_intx_irq(struct keystone_pcie *ks_pcie, 255 int offset) 256{ 257 struct dw_pcie *pci = ks_pcie->pci; 258 struct device *dev = pci->dev; 259 u32 pending; 260 261 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); 262 263 if (BIT(0) & pending) { 264 dev_dbg(dev, ": irq: irq_offset %d", offset); 265 generic_handle_domain_irq(ks_pcie->intx_irq_domain, offset); 266 } 267 268 /* EOI the INTx interrupt */ 269 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); 270} 271 272static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) 273{ 274 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); 275} 276 277static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) 278{ 279 u32 reg; 280 struct device *dev = ks_pcie->pci->dev; 281 282 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); 283 if (!reg) 284 return IRQ_NONE; 285 286 if (reg & ERR_SYS) 287 dev_err(dev, "System Error\n"); 288 289 if (reg & ERR_FATAL) 290 dev_err(dev, "Fatal Error\n"); 291 292 if (reg & ERR_NONFATAL) 293 dev_dbg(dev, "Non Fatal Error\n"); 294 295 if (reg & ERR_CORR) 296 dev_dbg(dev, "Correctable Error\n"); 297 298 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) 299 dev_err(dev, "AXI tag lookup fatal Error\n"); 300 301 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) 302 dev_err(dev, "ECRC Error\n"); 303 304 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); 305 306 return IRQ_HANDLED; 307} 308 309static void ks_pcie_ack_intx_irq(struct irq_data *d) 310{ 311} 312 313static void ks_pcie_mask_intx_irq(struct irq_data *d) 314{ 315} 316 317static void ks_pcie_unmask_intx_irq(struct irq_data *d) 318{ 319} 320 321static struct irq_chip ks_pcie_intx_irq_chip = { 322 .name = "Keystone-PCI-INTX-IRQ", 323 .irq_ack = ks_pcie_ack_intx_irq, 324 .irq_mask = ks_pcie_mask_intx_irq, 325 .irq_unmask = ks_pcie_unmask_intx_irq, 326}; 327 328static int ks_pcie_init_intx_irq_map(struct irq_domain *d, 329 unsigned int irq, irq_hw_number_t hw_irq) 330{ 331 irq_set_chip_and_handler(irq, &ks_pcie_intx_irq_chip, 332 handle_level_irq); 333 irq_set_chip_data(irq, d->host_data); 334 335 return 0; 336} 337 338static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = { 339 .map = ks_pcie_init_intx_irq_map, 340 .xlate = irq_domain_xlate_onetwocell, 341}; 342 343/** 344 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers 345 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 346 * PCIe host controller driver information. 347 * 348 * Since modification of dbi_cs2 involves different clock domain, read the 349 * status back to ensure the transition is complete. 350 */ 351static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) 352{ 353 u32 val; 354 355 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 356 val |= DBI_CS2; 357 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 358 359 do { 360 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 361 } while (!(val & DBI_CS2)); 362} 363 364/** 365 * ks_pcie_clear_dbi_mode() - Disable DBI mode 366 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 367 * PCIe host controller driver information. 368 * 369 * Since modification of dbi_cs2 involves different clock domain, read the 370 * status back to ensure the transition is complete. 371 */ 372static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) 373{ 374 u32 val; 375 376 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 377 val &= ~DBI_CS2; 378 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 379 380 do { 381 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 382 } while (val & DBI_CS2); 383} 384 385static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 386{ 387 u32 val; 388 u32 num_viewport = ks_pcie->num_viewport; 389 struct dw_pcie *pci = ks_pcie->pci; 390 struct dw_pcie_rp *pp = &pci->pp; 391 u64 start, end; 392 struct resource *mem; 393 int i; 394 395 mem = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM)->res; 396 start = mem->start; 397 end = mem->end; 398 399 /* Disable BARs for inbound access */ 400 ks_pcie_set_dbi_mode(ks_pcie); 401 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 402 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); 403 ks_pcie_clear_dbi_mode(ks_pcie); 404 405 if (ks_pcie->is_am6) 406 return; 407 408 val = ilog2(OB_WIN_SIZE); 409 ks_pcie_app_writel(ks_pcie, OB_SIZE, val); 410 411 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ 412 for (i = 0; i < num_viewport && (start < end); i++) { 413 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), 414 lower_32_bits(start) | OB_ENABLEN); 415 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 416 upper_32_bits(start)); 417 start += OB_WIN_SIZE * SZ_1M; 418 } 419 420 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 421 val |= OB_XLAT_EN_VAL; 422 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 423} 424 425static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus, 426 unsigned int devfn, int where) 427{ 428 struct dw_pcie_rp *pp = bus->sysdata; 429 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 430 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 431 u32 reg; 432 433 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | 434 CFG_FUNC(PCI_FUNC(devfn)); 435 if (!pci_is_root_bus(bus->parent)) 436 reg |= CFG_TYPE1; 437 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); 438 439 return pp->va_cfg0_base + where; 440} 441 442static struct pci_ops ks_child_pcie_ops = { 443 .map_bus = ks_pcie_other_map_bus, 444 .read = pci_generic_config_read, 445 .write = pci_generic_config_write, 446}; 447 448/** 449 * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization 450 * @bus: A pointer to the PCI bus structure. 451 * 452 * This sets BAR0 to enable inbound access for MSI_IRQ register 453 */ 454static int ks_pcie_v3_65_add_bus(struct pci_bus *bus) 455{ 456 struct dw_pcie_rp *pp = bus->sysdata; 457 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 458 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 459 460 if (!pci_is_root_bus(bus)) 461 return 0; 462 463 /* Configure and set up BAR0 */ 464 ks_pcie_set_dbi_mode(ks_pcie); 465 466 /* Enable BAR0 */ 467 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); 468 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); 469 470 ks_pcie_clear_dbi_mode(ks_pcie); 471 472 /* 473 * For BAR0, just setting bus address for inbound writes (MSI) should 474 * be sufficient. Use physical address to avoid any conflicts. 475 */ 476 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 477 478 return 0; 479} 480 481static struct pci_ops ks_pcie_ops = { 482 .map_bus = dw_pcie_own_conf_map_bus, 483 .read = pci_generic_config_read, 484 .write = pci_generic_config_write, 485 .add_bus = ks_pcie_v3_65_add_bus, 486}; 487 488/** 489 * ks_pcie_link_up() - Check if link up 490 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host 491 * controller driver information. 492 */ 493static int ks_pcie_link_up(struct dw_pcie *pci) 494{ 495 u32 val; 496 497 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); 498 val &= PORT_LOGIC_LTSSM_STATE_MASK; 499 return (val == PORT_LOGIC_LTSSM_STATE_L0); 500} 501 502static void ks_pcie_stop_link(struct dw_pcie *pci) 503{ 504 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 505 u32 val; 506 507 /* Disable Link training */ 508 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 509 val &= ~LTSSM_EN_VAL; 510 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 511} 512 513static int ks_pcie_start_link(struct dw_pcie *pci) 514{ 515 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 516 u32 val; 517 518 /* Initiate Link Training */ 519 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 520 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); 521 522 return 0; 523} 524 525static void ks_pcie_quirk(struct pci_dev *dev) 526{ 527 struct pci_bus *bus = dev->bus; 528 struct pci_dev *bridge; 529 static const struct pci_device_id rc_pci_devids[] = { 530 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), 531 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 532 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E), 533 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 534 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 535 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 536 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), 537 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 538 { 0, }, 539 }; 540 541 if (pci_is_root_bus(bus)) 542 bridge = dev; 543 544 /* look for the host bridge */ 545 while (!pci_is_root_bus(bus)) { 546 bridge = bus->self; 547 bus = bus->parent; 548 } 549 550 if (!bridge) 551 return; 552 553 /* 554 * Keystone PCI controller has a h/w limitation of 555 * 256 bytes maximum read request size. It can't handle 556 * anything higher than this. So force this limit on 557 * all downstream devices. 558 */ 559 if (pci_match_id(rc_pci_devids, bridge)) { 560 if (pcie_get_readrq(dev) > 256) { 561 dev_info(&dev->dev, "limiting MRRS to 256\n"); 562 pcie_set_readrq(dev, 256); 563 } 564 } 565} 566DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); 567 568static void ks_pcie_msi_irq_handler(struct irq_desc *desc) 569{ 570 unsigned int irq = desc->irq_data.hwirq; 571 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 572 u32 offset = irq - ks_pcie->msi_host_irq; 573 struct dw_pcie *pci = ks_pcie->pci; 574 struct dw_pcie_rp *pp = &pci->pp; 575 struct device *dev = pci->dev; 576 struct irq_chip *chip = irq_desc_get_chip(desc); 577 u32 vector, reg, pos; 578 579 dev_dbg(dev, "%s, irq %d\n", __func__, irq); 580 581 /* 582 * The chained irq handler installation would have replaced normal 583 * interrupt driver handler so we need to take care of mask/unmask and 584 * ack operation. 585 */ 586 chained_irq_enter(chip, desc); 587 588 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); 589 /* 590 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit 591 * shows 1, 9, 17, 25 and so forth 592 */ 593 for (pos = 0; pos < 4; pos++) { 594 if (!(reg & BIT(pos))) 595 continue; 596 597 vector = offset + (pos << 3); 598 dev_dbg(dev, "irq: bit %d, vector %d\n", pos, vector); 599 generic_handle_domain_irq(pp->irq_domain, vector); 600 } 601 602 chained_irq_exit(chip, desc); 603} 604 605/** 606 * ks_pcie_intx_irq_handler() - Handle INTX interrupt 607 * @desc: Pointer to irq descriptor 608 * 609 * Traverse through pending INTX interrupts and invoke handler for each. Also 610 * takes care of interrupt controller level mask/ack operation. 611 */ 612static void ks_pcie_intx_irq_handler(struct irq_desc *desc) 613{ 614 unsigned int irq = irq_desc_get_irq(desc); 615 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 616 struct dw_pcie *pci = ks_pcie->pci; 617 struct device *dev = pci->dev; 618 u32 irq_offset = irq - ks_pcie->intx_host_irqs[0]; 619 struct irq_chip *chip = irq_desc_get_chip(desc); 620 621 dev_dbg(dev, ": Handling INTX irq %d\n", irq); 622 623 /* 624 * The chained irq handler installation would have replaced normal 625 * interrupt driver handler so we need to take care of mask/unmask and 626 * ack operation. 627 */ 628 chained_irq_enter(chip, desc); 629 ks_pcie_handle_intx_irq(ks_pcie, irq_offset); 630 chained_irq_exit(chip, desc); 631} 632 633static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) 634{ 635 struct device *dev = ks_pcie->pci->dev; 636 struct device_node *np = ks_pcie->np; 637 struct device_node *intc_np; 638 struct irq_data *irq_data; 639 int irq_count, irq, ret, i; 640 641 if (!IS_ENABLED(CONFIG_PCI_MSI)) 642 return 0; 643 644 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); 645 if (!intc_np) { 646 if (ks_pcie->is_am6) 647 return 0; 648 dev_warn(dev, "msi-interrupt-controller node is absent\n"); 649 return -EINVAL; 650 } 651 652 irq_count = of_irq_count(intc_np); 653 if (!irq_count) { 654 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); 655 ret = -EINVAL; 656 goto err; 657 } 658 659 for (i = 0; i < irq_count; i++) { 660 irq = irq_of_parse_and_map(intc_np, i); 661 if (!irq) { 662 ret = -EINVAL; 663 goto err; 664 } 665 666 if (!ks_pcie->msi_host_irq) { 667 irq_data = irq_get_irq_data(irq); 668 if (!irq_data) { 669 ret = -EINVAL; 670 goto err; 671 } 672 ks_pcie->msi_host_irq = irq_data->hwirq; 673 } 674 675 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, 676 ks_pcie); 677 } 678 679 of_node_put(intc_np); 680 return 0; 681 682err: 683 of_node_put(intc_np); 684 return ret; 685} 686 687static int ks_pcie_config_intx_irq(struct keystone_pcie *ks_pcie) 688{ 689 struct device *dev = ks_pcie->pci->dev; 690 struct irq_domain *intx_irq_domain; 691 struct device_node *np = ks_pcie->np; 692 struct device_node *intc_np; 693 int irq_count, irq, ret = 0, i; 694 695 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); 696 if (!intc_np) { 697 /* 698 * Since INTX interrupts are modeled as edge-interrupts in 699 * AM6, keep it disabled for now. 700 */ 701 if (ks_pcie->is_am6) 702 return 0; 703 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); 704 return -EINVAL; 705 } 706 707 irq_count = of_irq_count(intc_np); 708 if (!irq_count) { 709 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); 710 ret = -EINVAL; 711 goto err; 712 } 713 714 for (i = 0; i < irq_count; i++) { 715 irq = irq_of_parse_and_map(intc_np, i); 716 if (!irq) { 717 ret = -EINVAL; 718 goto err; 719 } 720 ks_pcie->intx_host_irqs[i] = irq; 721 722 irq_set_chained_handler_and_data(irq, 723 ks_pcie_intx_irq_handler, 724 ks_pcie); 725 } 726 727 intx_irq_domain = irq_domain_add_linear(intc_np, PCI_NUM_INTX, 728 &ks_pcie_intx_irq_domain_ops, NULL); 729 if (!intx_irq_domain) { 730 dev_err(dev, "Failed to add irq domain for INTX irqs\n"); 731 ret = -EINVAL; 732 goto err; 733 } 734 ks_pcie->intx_irq_domain = intx_irq_domain; 735 736 for (i = 0; i < PCI_NUM_INTX; i++) 737 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); 738 739err: 740 of_node_put(intc_np); 741 return ret; 742} 743 744#ifdef CONFIG_ARM 745/* 746 * When a PCI device does not exist during config cycles, keystone host 747 * gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE). 748 * This handler always returns 0 for this kind of fault. 749 */ 750static int ks_pcie_fault(unsigned long addr, unsigned int fsr, 751 struct pt_regs *regs) 752{ 753 unsigned long instr = *(unsigned long *) instruction_pointer(regs); 754 755 if ((instr & 0x0e100090) == 0x00100090) { 756 int reg = (instr >> 12) & 15; 757 758 regs->uregs[reg] = -1; 759 regs->ARM_pc += 4; 760 } 761 762 return 0; 763} 764#endif 765 766static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) 767{ 768 int ret; 769 unsigned int id; 770 struct regmap *devctrl_regs; 771 struct dw_pcie *pci = ks_pcie->pci; 772 struct device *dev = pci->dev; 773 struct device_node *np = dev->of_node; 774 struct of_phandle_args args; 775 unsigned int offset = 0; 776 777 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); 778 if (IS_ERR(devctrl_regs)) 779 return PTR_ERR(devctrl_regs); 780 781 /* Do not error out to maintain old DT compatibility */ 782 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); 783 if (!ret) 784 offset = args.args[0]; 785 786 ret = regmap_read(devctrl_regs, offset, &id); 787 if (ret) 788 return ret; 789 790 dw_pcie_dbi_ro_wr_en(pci); 791 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); 792 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); 793 dw_pcie_dbi_ro_wr_dis(pci); 794 795 return 0; 796} 797 798static int __init ks_pcie_host_init(struct dw_pcie_rp *pp) 799{ 800 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 801 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 802 int ret; 803 804 pp->bridge->ops = &ks_pcie_ops; 805 if (!ks_pcie->is_am6) 806 pp->bridge->child_ops = &ks_child_pcie_ops; 807 808 ret = ks_pcie_config_intx_irq(ks_pcie); 809 if (ret) 810 return ret; 811 812 ret = ks_pcie_config_msi_irq(ks_pcie); 813 if (ret) 814 return ret; 815 816 ks_pcie_stop_link(pci); 817 ks_pcie_setup_rc_app_regs(ks_pcie); 818 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 819 pci->dbi_base + PCI_IO_BASE); 820 821 ret = ks_pcie_init_id(ks_pcie); 822 if (ret < 0) 823 return ret; 824 825#ifdef CONFIG_ARM 826 /* 827 * PCIe access errors that result into OCP errors are caught by ARM as 828 * "External aborts" 829 */ 830 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, 831 "Asynchronous external abort"); 832#endif 833 834 return 0; 835} 836 837static const struct dw_pcie_host_ops ks_pcie_host_ops = { 838 .init = ks_pcie_host_init, 839 .msi_init = ks_pcie_msi_host_init, 840}; 841 842static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { 843 .init = ks_pcie_host_init, 844}; 845 846static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) 847{ 848 struct keystone_pcie *ks_pcie = priv; 849 850 return ks_pcie_handle_error_irq(ks_pcie); 851} 852 853static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, 854 u32 reg, size_t size, u32 val) 855{ 856 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 857 858 ks_pcie_set_dbi_mode(ks_pcie); 859 dw_pcie_write(base + reg, size, val); 860 ks_pcie_clear_dbi_mode(ks_pcie); 861} 862 863static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { 864 .start_link = ks_pcie_start_link, 865 .stop_link = ks_pcie_stop_link, 866 .link_up = ks_pcie_link_up, 867 .write_dbi2 = ks_pcie_am654_write_dbi2, 868}; 869 870static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) 871{ 872 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 873 int flags; 874 875 ep->page_size = AM654_WIN_SIZE; 876 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; 877 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); 878 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); 879} 880 881static void ks_pcie_am654_raise_intx_irq(struct keystone_pcie *ks_pcie) 882{ 883 struct dw_pcie *pci = ks_pcie->pci; 884 u8 int_pin; 885 886 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); 887 if (int_pin == 0 || int_pin > 4) 888 return; 889 890 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), 891 INT_ENABLE); 892 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); 893 mdelay(1); 894 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); 895 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), 896 INT_ENABLE); 897} 898 899static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 900 unsigned int type, u16 interrupt_num) 901{ 902 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 903 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 904 905 switch (type) { 906 case PCI_IRQ_INTX: 907 ks_pcie_am654_raise_intx_irq(ks_pcie); 908 break; 909 case PCI_IRQ_MSI: 910 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 911 break; 912 case PCI_IRQ_MSIX: 913 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 914 break; 915 default: 916 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 917 return -EINVAL; 918 } 919 920 return 0; 921} 922 923static const struct pci_epc_features ks_pcie_am654_epc_features = { 924 .linkup_notifier = false, 925 .msi_capable = true, 926 .msix_capable = true, 927 .bar[BAR_0] = { .type = BAR_RESERVED, }, 928 .bar[BAR_1] = { .type = BAR_RESERVED, }, 929 .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, 930 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, 931 .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, 932 .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, 933 .align = SZ_1M, 934}; 935 936static const struct pci_epc_features* 937ks_pcie_am654_get_features(struct dw_pcie_ep *ep) 938{ 939 return &ks_pcie_am654_epc_features; 940} 941 942static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { 943 .init = ks_pcie_am654_ep_init, 944 .raise_irq = ks_pcie_am654_raise_irq, 945 .get_features = &ks_pcie_am654_get_features, 946}; 947 948static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 949{ 950 int num_lanes = ks_pcie->num_lanes; 951 952 while (num_lanes--) { 953 phy_power_off(ks_pcie->phy[num_lanes]); 954 phy_exit(ks_pcie->phy[num_lanes]); 955 } 956} 957 958static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) 959{ 960 int i; 961 int ret; 962 int num_lanes = ks_pcie->num_lanes; 963 964 for (i = 0; i < num_lanes; i++) { 965 ret = phy_reset(ks_pcie->phy[i]); 966 if (ret < 0) 967 goto err_phy; 968 969 ret = phy_init(ks_pcie->phy[i]); 970 if (ret < 0) 971 goto err_phy; 972 973 ret = phy_power_on(ks_pcie->phy[i]); 974 if (ret < 0) { 975 phy_exit(ks_pcie->phy[i]); 976 goto err_phy; 977 } 978 } 979 980 return 0; 981 982err_phy: 983 while (--i >= 0) { 984 phy_power_off(ks_pcie->phy[i]); 985 phy_exit(ks_pcie->phy[i]); 986 } 987 988 return ret; 989} 990 991static int ks_pcie_set_mode(struct device *dev) 992{ 993 struct device_node *np = dev->of_node; 994 struct of_phandle_args args; 995 unsigned int offset = 0; 996 struct regmap *syscon; 997 u32 val; 998 u32 mask; 999 int ret = 0; 1000 1001 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1002 if (IS_ERR(syscon)) 1003 return 0; 1004 1005 /* Do not error out to maintain old DT compatibility */ 1006 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1007 if (!ret) 1008 offset = args.args[0]; 1009 1010 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; 1011 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; 1012 1013 ret = regmap_update_bits(syscon, offset, mask, val); 1014 if (ret) { 1015 dev_err(dev, "failed to set pcie mode\n"); 1016 return ret; 1017 } 1018 1019 return 0; 1020} 1021 1022static int ks_pcie_am654_set_mode(struct device *dev, 1023 enum dw_pcie_device_mode mode) 1024{ 1025 struct device_node *np = dev->of_node; 1026 struct of_phandle_args args; 1027 unsigned int offset = 0; 1028 struct regmap *syscon; 1029 u32 val; 1030 u32 mask; 1031 int ret = 0; 1032 1033 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1034 if (IS_ERR(syscon)) 1035 return 0; 1036 1037 /* Do not error out to maintain old DT compatibility */ 1038 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1039 if (!ret) 1040 offset = args.args[0]; 1041 1042 mask = AM654_PCIE_DEV_TYPE_MASK; 1043 1044 switch (mode) { 1045 case DW_PCIE_RC_TYPE: 1046 val = RC; 1047 break; 1048 case DW_PCIE_EP_TYPE: 1049 val = EP; 1050 break; 1051 default: 1052 dev_err(dev, "INVALID device type %d\n", mode); 1053 return -EINVAL; 1054 } 1055 1056 ret = regmap_update_bits(syscon, offset, mask, val); 1057 if (ret) { 1058 dev_err(dev, "failed to set pcie mode\n"); 1059 return ret; 1060 } 1061 1062 return 0; 1063} 1064 1065static const struct ks_pcie_of_data ks_pcie_rc_of_data = { 1066 .host_ops = &ks_pcie_host_ops, 1067 .version = DW_PCIE_VER_365A, 1068}; 1069 1070static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { 1071 .host_ops = &ks_pcie_am654_host_ops, 1072 .mode = DW_PCIE_RC_TYPE, 1073 .version = DW_PCIE_VER_490A, 1074}; 1075 1076static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { 1077 .ep_ops = &ks_pcie_am654_ep_ops, 1078 .mode = DW_PCIE_EP_TYPE, 1079 .version = DW_PCIE_VER_490A, 1080}; 1081 1082static const struct of_device_id ks_pcie_of_match[] = { 1083 { 1084 .type = "pci", 1085 .data = &ks_pcie_rc_of_data, 1086 .compatible = "ti,keystone-pcie", 1087 }, 1088 { 1089 .data = &ks_pcie_am654_rc_of_data, 1090 .compatible = "ti,am654-pcie-rc", 1091 }, 1092 { 1093 .data = &ks_pcie_am654_ep_of_data, 1094 .compatible = "ti,am654-pcie-ep", 1095 }, 1096 { }, 1097}; 1098 1099static int ks_pcie_probe(struct platform_device *pdev) 1100{ 1101 const struct dw_pcie_host_ops *host_ops; 1102 const struct dw_pcie_ep_ops *ep_ops; 1103 struct device *dev = &pdev->dev; 1104 struct device_node *np = dev->of_node; 1105 const struct ks_pcie_of_data *data; 1106 enum dw_pcie_device_mode mode; 1107 struct dw_pcie *pci; 1108 struct keystone_pcie *ks_pcie; 1109 struct device_link **link; 1110 struct gpio_desc *gpiod; 1111 struct resource *res; 1112 void __iomem *base; 1113 u32 num_viewport; 1114 struct phy **phy; 1115 u32 num_lanes; 1116 char name[10]; 1117 u32 version; 1118 int ret; 1119 int irq; 1120 int i; 1121 1122 data = of_device_get_match_data(dev); 1123 if (!data) 1124 return -EINVAL; 1125 1126 version = data->version; 1127 host_ops = data->host_ops; 1128 ep_ops = data->ep_ops; 1129 mode = data->mode; 1130 1131 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); 1132 if (!ks_pcie) 1133 return -ENOMEM; 1134 1135 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1136 if (!pci) 1137 return -ENOMEM; 1138 1139 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); 1140 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); 1141 if (IS_ERR(ks_pcie->va_app_base)) 1142 return PTR_ERR(ks_pcie->va_app_base); 1143 1144 ks_pcie->app = *res; 1145 1146 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); 1147 base = devm_pci_remap_cfg_resource(dev, res); 1148 if (IS_ERR(base)) 1149 return PTR_ERR(base); 1150 1151 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) 1152 ks_pcie->is_am6 = true; 1153 1154 pci->dbi_base = base; 1155 pci->dbi_base2 = base; 1156 pci->dev = dev; 1157 pci->ops = &ks_pcie_dw_pcie_ops; 1158 pci->version = version; 1159 1160 irq = platform_get_irq(pdev, 0); 1161 if (irq < 0) 1162 return irq; 1163 1164 ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, 1165 "ks-pcie-error-irq", ks_pcie); 1166 if (ret < 0) { 1167 dev_err(dev, "failed to request error IRQ %d\n", 1168 irq); 1169 return ret; 1170 } 1171 1172 ret = of_property_read_u32(np, "num-lanes", &num_lanes); 1173 if (ret) 1174 num_lanes = 1; 1175 1176 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); 1177 if (!phy) 1178 return -ENOMEM; 1179 1180 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL); 1181 if (!link) 1182 return -ENOMEM; 1183 1184 for (i = 0; i < num_lanes; i++) { 1185 snprintf(name, sizeof(name), "pcie-phy%d", i); 1186 phy[i] = devm_phy_optional_get(dev, name); 1187 if (IS_ERR(phy[i])) { 1188 ret = PTR_ERR(phy[i]); 1189 goto err_link; 1190 } 1191 1192 if (!phy[i]) 1193 continue; 1194 1195 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 1196 if (!link[i]) { 1197 ret = -EINVAL; 1198 goto err_link; 1199 } 1200 } 1201 1202 ks_pcie->np = np; 1203 ks_pcie->pci = pci; 1204 ks_pcie->link = link; 1205 ks_pcie->num_lanes = num_lanes; 1206 ks_pcie->phy = phy; 1207 1208 gpiod = devm_gpiod_get_optional(dev, "reset", 1209 GPIOD_OUT_LOW); 1210 if (IS_ERR(gpiod)) { 1211 ret = PTR_ERR(gpiod); 1212 if (ret != -EPROBE_DEFER) 1213 dev_err(dev, "Failed to get reset GPIO\n"); 1214 goto err_link; 1215 } 1216 1217 /* Obtain references to the PHYs */ 1218 for (i = 0; i < num_lanes; i++) 1219 phy_pm_runtime_get_sync(ks_pcie->phy[i]); 1220 1221 ret = ks_pcie_enable_phy(ks_pcie); 1222 1223 /* Release references to the PHYs */ 1224 for (i = 0; i < num_lanes; i++) 1225 phy_pm_runtime_put_sync(ks_pcie->phy[i]); 1226 1227 if (ret) { 1228 dev_err(dev, "failed to enable phy\n"); 1229 goto err_link; 1230 } 1231 1232 platform_set_drvdata(pdev, ks_pcie); 1233 pm_runtime_enable(dev); 1234 ret = pm_runtime_get_sync(dev); 1235 if (ret < 0) { 1236 dev_err(dev, "pm_runtime_get_sync failed\n"); 1237 goto err_get_sync; 1238 } 1239 1240 if (dw_pcie_ver_is_ge(pci, 480A)) 1241 ret = ks_pcie_am654_set_mode(dev, mode); 1242 else 1243 ret = ks_pcie_set_mode(dev); 1244 if (ret < 0) 1245 goto err_get_sync; 1246 1247 switch (mode) { 1248 case DW_PCIE_RC_TYPE: 1249 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { 1250 ret = -ENODEV; 1251 goto err_get_sync; 1252 } 1253 1254 ret = of_property_read_u32(np, "num-viewport", &num_viewport); 1255 if (ret < 0) { 1256 dev_err(dev, "unable to read *num-viewport* property\n"); 1257 goto err_get_sync; 1258 } 1259 1260 /* 1261 * "Power Sequencing and Reset Signal Timings" table in 1262 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 1263 * indicates PERST# should be deasserted after minimum of 100us 1264 * once REFCLK is stable. The REFCLK to the connector in RC 1265 * mode is selected while enabling the PHY. So deassert PERST# 1266 * after 100 us. 1267 */ 1268 if (gpiod) { 1269 usleep_range(100, 200); 1270 gpiod_set_value_cansleep(gpiod, 1); 1271 } 1272 1273 ks_pcie->num_viewport = num_viewport; 1274 pci->pp.ops = host_ops; 1275 ret = dw_pcie_host_init(&pci->pp); 1276 if (ret < 0) 1277 goto err_get_sync; 1278 break; 1279 case DW_PCIE_EP_TYPE: 1280 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { 1281 ret = -ENODEV; 1282 goto err_get_sync; 1283 } 1284 1285 pci->ep.ops = ep_ops; 1286 ret = dw_pcie_ep_init(&pci->ep); 1287 if (ret < 0) 1288 goto err_get_sync; 1289 break; 1290 default: 1291 dev_err(dev, "INVALID device type %d\n", mode); 1292 } 1293 1294 ks_pcie_enable_error_irq(ks_pcie); 1295 1296 return 0; 1297 1298err_get_sync: 1299 pm_runtime_put(dev); 1300 pm_runtime_disable(dev); 1301 ks_pcie_disable_phy(ks_pcie); 1302 1303err_link: 1304 while (--i >= 0 && link[i]) 1305 device_link_del(link[i]); 1306 1307 return ret; 1308} 1309 1310static void ks_pcie_remove(struct platform_device *pdev) 1311{ 1312 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 1313 struct device_link **link = ks_pcie->link; 1314 int num_lanes = ks_pcie->num_lanes; 1315 struct device *dev = &pdev->dev; 1316 1317 pm_runtime_put(dev); 1318 pm_runtime_disable(dev); 1319 ks_pcie_disable_phy(ks_pcie); 1320 while (num_lanes--) 1321 device_link_del(link[num_lanes]); 1322} 1323 1324static struct platform_driver ks_pcie_driver = { 1325 .probe = ks_pcie_probe, 1326 .remove_new = ks_pcie_remove, 1327 .driver = { 1328 .name = "keystone-pcie", 1329 .of_match_table = ks_pcie_of_match, 1330 }, 1331}; 1332builtin_platform_driver(ks_pcie_driver); 1333