Searched refs:divider (Results 126 - 147 of 147) sorted by relevance

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/linux-master/drivers/gpu/drm/exynos/
H A Dexynos_drm_scaler.c342 unsigned int timer, unsigned int divider)
348 val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider);
341 scaler_set_timer(struct scaler_context *scaler, unsigned int timer, unsigned int divider) argument
/linux-master/drivers/firmware/xilinx/
H A Dzynqmp.c625 * zynqmp_pm_clock_setdivider() - Set the clock divider for given id
627 * @divider: divider value
629 * This function is used by master to set divider for any clock
634 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) argument
636 return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, NULL, 2, clock_id, divider);
641 * zynqmp_pm_clock_getdivider() - Get the clock divider for given id
643 * @divider: divider value
645 * This function is used by master to get divider value
650 zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) argument
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/linux-master/sound/isa/es1688/
H A Des1688_lib.c299 unsigned int bits, divider; local
306 divider = 256 - 7160000*20/(8*82*runtime->rate);
309 snd_es1688_write(chip, 0xa2, divider);
/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c118 u64 divider; local
125 divider = fref * 2;
128 dec_multiple = div_u64(pll_freq * multiplier, divider);
570 * The post dividers and mux clocks are created using the standard divider and
572 * state to follow the master PLL's divider/mux state. Therefore, we don't
H A Ddsi_phy_7nm.c114 u64 divider; local
121 divider = fref * 2;
124 dec_multiple = div_u64(pll_freq * multiplier, divider);
619 * The post dividers and mux clocks are created using the standard divider and
621 * state to follow the master PLL's divider/mux state. Therefore, we don't
/linux-master/drivers/clk/ti/
H A Dadpll.c255 dev_err(d->dev, "failed to register divider %s: %li\n",
442 u32 frac_m, divider, v; local
455 divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
458 do_div(rate, divider);
518 /* Internal input clock divider N2 */
640 /* Internal mux, sources from divider N2 or clkinpulow */
649 /* Internal divider M2, sources DCO */
659 /* Internal fixed divider, after M2 before clkout */
692 /* Output clkouthif with a divider M3, sources from hif */
722 /* Internal divider M
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/linux-master/drivers/power/supply/
H A Dcpcap-battery.c239 * @divider: conversion divider
256 s16 offset, u32 divider)
260 if (!divider)
267 acc = div_s64(acc, divider);
254 cpcap_battery_cc_raw_div(struct cpcap_battery_ddata *ddata, s32 sample, s32 accumulator, s16 offset, u32 divider) argument
/linux-master/drivers/soc/qcom/
H A Dqcom-geni-se.c626 unsigned int divider; local
637 divider = DIV_ROUND_UP(tbl[i], req_freq);
638 new_delta = req_freq - tbl[i] / divider;
/linux-master/drivers/gpu/drm/radeon/
H A Drv6xx_dpm.c380 u32 index, u32 divider)
383 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);
387 u32 index, u32 divider)
389 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
394 u32 index, u32 divider)
397 LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK);
379 rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
386 rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
393 rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
/linux-master/drivers/gpu/drm/kmb/
H A Dkmb_dsi.c94 u32 divider; member in struct:vco_params
885 .divider = 1,
961 t_freq = target_freq_mhz * vco_p.divider;
/linux-master/kernel/sched/
H A Dfair.c3815 u32 divider = get_pelt_divider(&se->avg); local
3817 se->avg.load_avg = div_u64(se_weight(se) * se->avg.load_sum, divider);
4027 * _avg must be null when _sum are null because _avg = _sum / divider
4274 u32 new_sum, divider; local
4284 divider = get_pelt_divider(&cfs_rq->avg);
4289 new_sum = se->avg.util_avg * divider;
4306 u32 new_sum, divider; local
4316 divider = get_pelt_divider(&cfs_rq->avg);
4320 new_sum = se->avg.runnable_avg * divider;
4339 u32 divider; local
4586 u32 divider = get_pelt_divider(&cfs_rq->avg); local
4655 u32 divider = get_pelt_divider(&cfs_rq->avg); local
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/linux-master/drivers/clk/bcm/
H A Dclk-kona.c49 /* Convert a divider into the scaled divisor value it represents. */
56 * Build a scaled divider value as close as possible to the
73 /* The scaled minimum divisor representable by a divider */
83 /* The scaled maximum divisor representable by a divider */
97 * Convert a scaled divisor into its divider representation as
98 * stored in a divider register field.
101 divider(struct bcm_clk_div *div, u64 scaled_div) function
555 /* Read a divider value and return the scaled divisor it represents. */
569 /* Extract the full divider field from the register value */
577 * Convert a divider'
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/linux-master/arch/sh/boards/mach-ecovec24/
H A Dsetup.c514 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
519 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
/linux-master/drivers/clk/qcom/
H A DMakefile11 clk-qcom-y += clk-regmap-divider.o
/linux-master/fs/gfs2/
H A Ddir.c1007 u32 start, len, half_len, divider; local
1077 /* Compute the divider */
1078 divider = (start + half_len) << (32 - dip->i_depth);
1089 be32_to_cpu(dent->de_hash) < divider) {
/linux-master/drivers/gpu/drm/i915/display/
H A Dvlv_dsi.c955 * On Broxton the PLL needs to be enabled with a valid divider
1201 /* return txclkesc cycles in terms of divider and duration in us */
1202 static u16 txclkesc(u32 divider, unsigned int us) argument
1204 switch (divider) {
1330 * escape clock divider, 20MHz, shared for A and C.
H A Dintel_dpll_mgr.c1497 unsigned int p; /* chosen divider */
1507 unsigned int divider)
1521 ctx->p = divider;
1529 ctx->p = divider;
1700 * have found the definitive divider, we can't
1710 * If a solution is found with an even divider, prefer
1764 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
2596 * Program half of the nominal DCO divider fraction value.
1504 skl_wrpll_try_divider(struct skl_wrpll_context *ctx, u64 central_freq, u64 dco_freq, unsigned int divider) argument
H A Dintel_display.c149 int divider; local
152 divider = val & CCK_FREQUENCY_VALUES;
155 (divider << CCK_FREQUENCY_STATUS_SHIFT),
158 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
3742 * The PLL needs to be enabled with a valid divider
/linux-master/drivers/comedi/drivers/
H A Dni_mio_common.c1954 int divider; local
1959 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1962 divider = (nanosec) / devpriv->clock_ns;
1965 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1968 return divider - 1;
4137 /* use the last data value to set the fout divider */
4903 * Find best multiplier/divider to try and get the PLL running at 80 MHz
/linux-master/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c819 unsigned int max_clk = 2500000, divider; local
859 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
866 val = FIELD_PREP(PPSC_MDC_CFG, divider);
871 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
/linux-master/drivers/staging/media/ipu3/
H A Dipu3-css-params.c29 unsigned int divider)
31 int i = fls(divider) - fls(counter);
36 if (divider >> i < counter)
28 imgu_css_scaler_get_exp(unsigned int counter, unsigned int divider) argument
/linux-master/lib/zstd/compress/
H A Dzstd_compress.c1400 U32 const divider = (cParams->minMatch==3) ? 3 : 4; local
1401 size_t const maxNbSeq = blockSize / divider;
1780 U32 const divider = (params->cParams.minMatch==3) ? 3 : 4; local
1781 size_t const maxNbSeq = blockSize / divider;

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