Searched refs:SDValue (Results 76 - 100 of 129) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp59 SDValue Base;
61 SDValue Index;
120 RxSBGOperands(unsigned Op, SDValue N)
128 SDValue Input;
138 inline SDValue getImm(const SDNode *Node, uint64_t Imm) const {
155 bool selectAddress(SDValue N, SystemZAddressingMode &AM) const;
159 SDValue &Base, SDValue &Disp) const;
161 SDValue &Base, SDValue
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2040 SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
2045 return SDValue(Node, 0);
2382 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2564 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2578 SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2596 const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
2597 SmallVectorImpl<std::pair<Register, SDValue>>
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGISel.h26 class SDValue;
91 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
93 std::vector<SDValue> &OutOps) {
99 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
105 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
205 void ReplaceUses(SDValue F, SDValue T) {
212 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
234 void SelectInlineAsmMemoryOperands(std::vector<SDValue>
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp217 SDValue
218 HexagonTargetLowering::getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
220 SmallVector<SDValue,4> IntOps;
222 for (const SDValue &Op : Ops)
259 SDValue
260 HexagonTargetLowering::opCastElem(SDValue Vec, MVT ElemTy,
268 SDValue
276 HexagonTargetLowering::opSplit(SDValue Vec, const SDLoc &dl,
327 SDValue
328 HexagonTargetLowering::convertToByteIndex(SDValue ElemId
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H A DHexagonISelLowering.cpp160 SDValue
161 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
163 return SDValue();
171 static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
172 SDValue Chain, ISD::ArgFlagsTy Flags,
174 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
197 SDValue
198 HexagonTargetLowering::LowerReturn(SDValue Chai
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H A DHexagonISelDAGToDAG.cpp68 SDValue Chain = LD->getChain();
69 SDValue Base = LD->getBasePtr();
70 SDValue Offset = LD->getOffset();
129 SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
135 SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32);
137 Zero, SDValue(N, 0));
141 SDValue(N, 0));
146 SDValue From[3] = { SDValue(LD,0), SDValue(L
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16ISelDAGToDAG.cpp50 SDValue InFlag = SDValue(Mul, 0);
55 InFlag = SDValue(Lo, 1);
98 bool Mips16DAGToDAGISel::selectAddr(bool SPAllowed, SDValue Addr, SDValue &Base,
99 SDValue &Offset) {
153 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
167 bool Mips16DAGToDAGISel::selectAddr16(SDValue Addr, SDValue &Base,
168 SDValue
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H A DMips16ISelLowering.h47 getOpndList(SmallVectorImpl<SDValue> &Ops,
48 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
50 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
51 SDValue Chain) const override;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp83 SDValue Res(&Node, i);
106 SDValue NewVal = getSDValue(NewValId);
206 DAG.setRoot(SDValue());
379 ReplaceValueWith(SDValue(N, i), SDValue(M, i));
513 std::vector<SDValue> NewOps;
516 SDValue OrigOp = N->getOperand(i);
517 SDValue Op = OrigOp;
565 void DAGTypeLegalizer::AnalyzeNewValue(SDValue &Val) {
574 void DAGTypeLegalizer::RemapValue(SDValue
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H A DLegalizeTypesGeneric.cpp35 SDValue &Lo, SDValue &Hi) {
36 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
40 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
43 SDValue InOp = N->getOperand(0);
121 SDValue CastInOp = DAG.getNode(ISD::BITCAST, dl, NVT, InOp);
123 SmallVector<SDValue, 8> Vals;
133 SDValue LHS = Vals[Slot];
134 SDValue RH
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H A DTargetLowering.cpp52 SDValue &Chain) const {
81 const SmallVectorImpl<SDValue> &OutVals) const {
93 SDValue Value = OutVals[I];
129 std::pair<SDValue, SDValue>
131 ArrayRef<SDValue> Ops,
134 SDValue InChain) const {
143 SDValue NewOp = Ops[i];
159 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
276 SDValue
5169 turnVectorIntoSplatVector(MutableArrayRef<SDValue> Values, std::function<bool(SDValue)> Predicate, SDValue AlternativeReplacement = SDValue()) argument
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H A DLegalizeDAG.cpp64 SDValue Chain;
65 SDValue FloatPtr;
66 SDValue IntPtr;
69 SDValue IntValue;
114 SDValue OptimizeFloatStore(StoreSDNode *ST);
123 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
125 SDValue ExpandINSERT_VECTOR_EL
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H A DSelectionDAGBuilder.h97 DenseMap<const Value*, SDValue> NodeMap;
101 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
130 SmallVector<SDValue, 8> PendingLoads;
141 SmallVector<SDValue, 8> PendingExports;
151 SmallVector<SDValue, 8> PendingConstrainedFP;
152 SmallVector<SDValue, 8> PendingConstrainedFPStrict;
155 SDValue updateRoot(SmallVectorImpl<SDValue> &Pending);
464 SDValue getMemoryRoot();
470 SDValue getRoo
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H A DSelectionDAG.cpp107 static void NewSDValueDbgMsg(SDValue V, StringRef Msg, SelectionDAG *G) {
181 SDValue NotZero = N->getOperand(i);
209 for (const SDValue &Op : N->op_values()) {
242 for (const SDValue &Op : N->op_values()) {
255 for (const SDValue &Op : N->op_values()) {
270 return all_of(N->op_values(), [](SDValue Op) { return Op.isUndef(); });
273 bool ISD::matchUnaryPredicate(SDValue Op,
300 SDValue LHS, SDValue RHS,
318 SDValue LHSO
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp194 SDValue
195 SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
198 const SmallVectorImpl<SDValue> &OutVals,
205 SDValue
206 SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
209 const SmallVectorImpl<SDValue> &OutVals,
223 SDValue Flag;
224 SmallVector<SDValue, 4> RetOps(1, Chain);
226 RetOps.push_back(SDValue());
235 SDValue Ar
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp43 SDValue Reg;
102 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
103 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
104 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
106 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
107 std::vector<SDValue> &OutOps) override;
116 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
119 bool SelectAddr(SDValue Addr, SDValue
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp61 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
63 std::vector<SDValue> &OutOps) override;
66 bool SelectRDVLImm(SDValue N, SDValue &Imm);
70 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
71 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue
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H A DAArch64ISelLowering.cpp1100 static bool optimizeLogicalImm(SDValue Op, unsigned Size, uint64_t Imm,
1176 SDValue New;
1187 SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT);
1188 New = SDValue(
1196 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1241 const SDValue Op, KnownBits &Known,
1882 static bool isCMN(SDValue Op, ISD::CondCode CC) {
1887 static SDValue emitStrictFPComparison(SDValue LHS, SDValue RH
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1877 static bool isSRL16(const SDValue &Op) {
1885 static bool isSRA16(const SDValue &Op) {
1893 static bool isSHL16(const SDValue &Op) {
1905 static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
2038 SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2039 MVT LocVT, MVT ValVT, SDValue Val) const {
2052 SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2054 SDValue Val) const {
2069 SDValue ARMTargetLowering::LowerCallResult(
2070 SDValue Chai
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp475 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
492 SDValue Result = LowerLOAD(Op, DAG);
503 SDValue Chain = Op.getOperand(0);
509 const SDValue Args[8] = {
548 SDValue TexArgs[19] = {
572 SDValue Args[8] = {
655 return SDValue();
659 SmallVectorImpl<SDValue> &Results,
680 SDValue Resul
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H A DSIISelLowering.cpp1520 SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1522 SDValue Chain,
1537 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
1543 SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1550 SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1551 const SDLoc &SL, SDValue Val,
1581 SDValue SITargetLowering::lowerKernargMemParameter(
1582 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain,
1599 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
1600 SDValue Loa
6581 getBufferOffsetForMMO(SDValue VOffset, SDValue SOffset, SDValue Offset, SDValue VIndex = SDValue()) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp130 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
1603 static bool isFloatingPointZero(SDValue Op) {
2263 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2264 SDValue OpVal(nullptr, 0);
2273 SDValue UniquedVals[4];
2280 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2285 return SDValue(); // no match.
2318 return SDValue();
2327 return SDValue();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp63 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
64 std::vector<SDValue> &OutOps) override;
74 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
75 bool SelectFIAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
100 bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp352 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
389 static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
425 SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
456 SDValue Op0 = Op.getOperand(0);
458 return SDValue();
459 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
460 SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
468 static SDValue getTargetNod
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp74 SDValue
75 VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
78 const SmallVectorImpl<SDValue> &OutVals,
90 SDValue Flag;
91 SmallVector<SDValue, 4> RetOps(1, Chain);
97 SDValue OutVal = OutVals[i];
134 SDValue VETargetLowering::LowerFormalArguments(
135 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
137 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
164 SDValue Ar
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