Lines Matching refs:SDValue
61 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
63 std::vector<SDValue> &OutOps) override;
66 bool SelectRDVLImm(SDValue N, SDValue &Imm);
70 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
71 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
72 bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
73 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
76 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
79 bool SelectAddrModeIndexed7S8(SDValue N, SDValue &Base, SDValue &OffImm) {
82 bool SelectAddrModeIndexed7S16(SDValue N, SDValue &Base, SDValue &OffImm) {
85 bool SelectAddrModeIndexed7S32(SDValue N, SDValue &Base, SDValue &OffImm) {
88 bool SelectAddrModeIndexed7S64(SDValue N, SDValue &Base, SDValue &OffImm) {
91 bool SelectAddrModeIndexed7S128(SDValue N, SDValue &Base, SDValue &OffImm) {
94 bool SelectAddrModeIndexedS9S128(SDValue N, SDValue &Base, SDValue &OffImm) {
97 bool SelectAddrModeIndexedU6S128(SDValue N, SDValue &Base, SDValue &OffImm) {
100 bool SelectAddrModeIndexed8(SDValue N, SDValue &Base, SDValue &OffImm) {
103 bool SelectAddrModeIndexed16(SDValue N, SDValue &Base, SDValue &OffImm) {
106 bool SelectAddrModeIndexed32(SDValue N, SDValue &Base, SDValue &OffImm) {
109 bool SelectAddrModeIndexed64(SDValue N, SDValue &Base, SDValue &OffImm) {
112 bool SelectAddrModeIndexed128(SDValue N, SDValue &Base, SDValue &OffImm) {
115 bool SelectAddrModeUnscaled8(SDValue N, SDValue &Base, SDValue &OffImm) {
118 bool SelectAddrModeUnscaled16(SDValue N, SDValue &Base, SDValue &OffImm) {
121 bool SelectAddrModeUnscaled32(SDValue N, SDValue &Base, SDValue &OffImm) {
124 bool SelectAddrModeUnscaled64(SDValue N, SDValue &Base, SDValue &OffImm) {
127 bool SelectAddrModeUnscaled128(SDValue N, SDValue &Base, SDValue &OffImm) {
132 bool SelectAddrModeWRO(SDValue N, SDValue &Base, SDValue &Offset,
133 SDValue &SignExtend, SDValue &DoShift) {
138 bool SelectAddrModeXRO(SDValue N, SDValue &Base, SDValue &Offset,
139 SDValue &SignExtend, SDValue &DoShift) {
143 bool SelectDupZeroOrUndef(SDValue N) {
165 bool SelectDupZero(SDValue N) {
184 bool SelectSVEAddSubImm(SDValue N, SDValue &Imm, SDValue &Shift) {
189 bool SelectSVELogicalImm(SDValue N, SDValue &Imm) {
194 bool SelectSVEShiftImm64(SDValue N, SDValue &Imm) {
200 bool SelectCntImm(SDValue N, SDValue &Imm) {
224 SDValue createDTuple(ArrayRef<SDValue> Vecs);
225 SDValue createQTuple(ArrayRef<SDValue> Vecs);
228 SDValue createZTuple(ArrayRef<SDValue> Vecs);
232 SDValue createTuple(ArrayRef<SDValue> Vecs, const unsigned RegClassIDs[],
251 bool SelectAddrModeFrameIndexSVE(SDValue N, SDValue &Base, SDValue &OffImm);
254 bool SelectAddrModeIndexedSVE(SDNode *Root, SDValue N, SDValue &Base,
255 SDValue &OffImm);
258 bool SelectSVERegRegAddrMode(SDValue N, SDValue &Base, SDValue &Offset) {
268 std::tuple<unsigned, SDValue, SDValue>
270 const SDValue &OldBase, const SDValue &OldOffset,
287 bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
288 SDValue &Shift);
289 bool SelectAddrModeIndexed7S(SDValue N, unsigned Size, SDValue &Base,
290 SDValue &OffImm) {
293 bool SelectAddrModeIndexedBitWidth(SDValue N, bool IsSignedImm, unsigned BW,
294 unsigned Size, SDValue &Base,
295 SDValue &OffImm);
296 bool SelectAddrModeIndexed(SDValue N, unsigned Size, SDValue &Base,
297 SDValue &OffImm);
298 bool SelectAddrModeUnscaled(SDValue N, unsigned Size, SDValue &Base,
299 SDValue &OffImm);
300 bool SelectAddrModeWRO(SDValue N, unsigned Size, SDValue &Base,
301 SDValue &Offset, SDValue &SignExtend,
302 SDValue &DoShift);
303 bool SelectAddrModeXRO(SDValue N, unsigned Size, SDValue &Base,
304 SDValue &Offset, SDValue &SignExtend,
305 SDValue &DoShift);
306 bool isWorthFolding(SDValue V) const;
307 bool SelectExtendedSHL(SDValue N, unsigned Size, bool WantExtend,
308 SDValue &Offset, SDValue &SignExtend);
311 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
315 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
319 bool SelectSVE8BitLslImm(SDValue N, SDValue &Imm, SDValue &Shift);
321 bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);
323 bool SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm);
325 bool SelectSVESignedArithImm(SDValue N, SDValue &Imm);
326 bool SelectSVEShiftImm64(SDValue N, uint64_t Low, uint64_t High,
327 SDValue &Imm);
329 bool SelectSVEArithImm(SDValue N, SDValue &Imm);
330 bool SelectSVERegRegAddrMode(SDValue N, unsigned Scale, SDValue &Base,
331 SDValue &Offset);
347 static bool isIntImmediate(SDValue N, uint64_t &Imm) {
361 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
372 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
373 SDValue NewOp =
374 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
386 bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
387 SDValue &Shift) {
416 bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
417 SDValue &Shift) {
449 static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
466 static bool isWorthFoldingSHL(SDValue V) {
489 bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
500 const SDValue LHS = V.getOperand(0);
501 const SDValue RHS = V.getOperand(1);
517 bool AArch64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
518 SDValue &Reg, SDValue &Shift) {
541 getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
593 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) {
598 SDValue SV = DL->getOperand(0);
602 SDValue EV = SV.getOperand(1);
616 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
617 SDValue &LaneOp, int &LaneIdx) {
633 SDValue Op0 = N->getOperand(0);
634 SDValue Op1 = N->getOperand(1);
635 SDValue MLAOp1; // Will hold ordinary multiplicand for MLA.
636 SDValue MLAOp2; // Will hold lane-accessed multiplicand for MLA.
649 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
651 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
678 SDValue SMULLOp0;
679 SDValue SMULLOp1;
686 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
688 SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
725 static SDValue narrowIfNeeded(SelectionDAG *CurDAG, SDValue N) {
730 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
733 return SDValue(Node, 0);
738 bool AArch64DAGToDAGISel::SelectRDVLImm(SDValue N, SDValue &Imm) {
756 bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
757 SDValue &Shift) {
804 static bool isWorthFoldingADDlow(SDValue N) {
823 bool AArch64DAGToDAGISel::SelectAddrModeIndexedBitWidth(SDValue N, bool IsSignedImm,
825 SDValue &Base,
826 SDValue &OffImm) {
886 bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
887 SDValue &Base, SDValue &OffImm) {
946 bool AArch64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
947 SDValue &Base,
948 SDValue &OffImm) {
972 static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
974 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
975 SDValue ImpDef = SDValue(
979 return SDValue(Node, 0);
984 bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
985 bool WantExtend, SDValue &Offset,
986 SDValue &SignExtend) {
1016 bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
1017 SDValue &Base, SDValue &Offset,
1018 SDValue &SignExtend,
1019 SDValue &DoShift) {
1022 SDValue LHS = N.getOperand(0);
1023 SDValue RHS = N.getOperand(1);
1105 bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
1106 SDValue &Base, SDValue &Offset,
1107 SDValue &SignExtend,
1108 SDValue &DoShift) {
1111 SDValue LHS = N.getOperand(0);
1112 SDValue RHS = N.getOperand(1);
1145 SDValue Ops[] = { RHS };
1148 SDValue MOVIV = SDValue(MOVI, 0);
1181 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
1190 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
1199 SDValue AArch64DAGToDAGISel::createZTuple(ArrayRef<SDValue> Regs) {
1209 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
1221 SmallVector<SDValue, 4> Ops;
1235 return SDValue(N, 0);
1247 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
1249 SDValue RegSeq = createQTuple(Regs);
1251 SmallVector<SDValue, 6> Ops;
1327 SDValue Chain = LD->getChain();
1328 SDValue Base = LD->getBasePtr();
1332 SDValue Offset = CurDAG->getTargetConstant(OffsetVal, dl, MVT::i64);
1333 SDValue Ops[] = { Base, Offset, Chain };
1337 SDValue LoadedVal = SDValue(Res, 1);
1339 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
1341 SDValue(CurDAG->getMachineNode(
1348 ReplaceUses(SDValue(N, 0), LoadedVal);
1349 ReplaceUses(SDValue(N, 1), SDValue(Res, 0));
1350 ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
1359 SDValue Chain = N->getOperand(0);
1361 SDValue Ops[] = {N->getOperand(2), // Mem operand;
1367 SDValue SuperReg = SDValue(Ld, 0);
1369 ReplaceUses(SDValue(N, i),
1372 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1385 SDValue Chain = N->getOperand(0);
1387 SDValue Ops[] = {N->getOperand(1), // Mem operand
1397 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1400 SDValue SuperReg = SDValue(Ld, 1);
1402 ReplaceUses(SDValue(N, 0), SuperReg);
1405 ReplaceUses(SDValue(N, i),
1409 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1414 /// mode. Returns a tuple consisting of an Opcode, an SDValue representing the
1415 /// new Base and an SDValue representing the new offset.
1416 std::tuple<unsigned, SDValue, SDValue>
1419 const SDValue &OldBase,
1420 const SDValue &OldOffset,
1422 SDValue NewBase = OldBase;
1423 SDValue NewOffset = OldOffset;
1443 SDValue Chain = N->getOperand(0);
1446 SDValue Base, Offset;
1452 SDValue Ops[] = {N->getOperand(1), // Predicate
1459 SDValue SuperReg = SDValue(Load, 0);
1461 ReplaceUses(SDValue(N, i), CurDAG->getTargetExtractSubreg(
1466 ReplaceUses(SDValue(N, ChainIdx), SDValue(Load, 1));
1477 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1478 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1480 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
1496 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1497 SDValue RegSeq = createZTuple(Regs);
1501 SDValue Offset, Base;
1506 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate
1515 bool AArch64DAGToDAGISel::SelectAddrModeFrameIndexSVE(SDValue N, SDValue &Base,
1516 SDValue &OffImm) {
1541 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1542 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1544 SDValue Ops[] = {RegSeq,
1562 SDValue operator()(SDValue V64Reg) {
1569 SDValue Undef =
1570 SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
1578 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
1595 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1601 SDValue RegSeq = createQTuple(Regs);
1608 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
1611 SDValue SuperReg = SDValue(Ld, 0);
1617 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1620 ReplaceUses(SDValue(N, i), NV);
1623 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1634 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1640 SDValue RegSeq = createQTuple(Regs);
1648 SDValue Ops[] = {RegSeq,
1657 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1660 SDValue SuperReg = SDValue(Ld, 1);
1662 ReplaceUses(SDValue(N, 0),
1669 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT,
1673 ReplaceUses(SDValue(N, i), NV);
1678 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1689 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1695 SDValue RegSeq = createQTuple(Regs);
1700 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
1718 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1724 SDValue RegSeq = createQTuple(Regs);
1732 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
1746 unsigned &Opc, SDValue &Opd0,
1838 SDValue &Opd0, unsigned &Immr,
1847 SDValue Op = N->getOperand(0);
1871 SDValue &Opd0, unsigned &LSB,
1916 static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1992 SDValue Op = N->getOperand(0);
1998 SDValue Opd0 = Widen(CurDAG, Op.getOperand(0));
2001 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
2013 SDValue Extract = N->getOperand(0);
2037 SDValue &Opd0, unsigned &Immr, unsigned &Imms,
2079 SDValue Opd0;
2089 SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, MVT::i64),
2093 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
2095 MVT::i32, SDValue(BFM, 0), SubReg));
2099 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
2137 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);
2139 static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
2148 static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
2175 static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
2185 static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
2213 static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
2269 SDValue Orig, unsigned Depth) {
2284 return getUsefulBitsFromAndWithImmediate(SDValue(UserNode, 0), UsefulBits,
2288 return getUsefulBitsFromUBFM(SDValue(UserNode, 0), UsefulBits, Depth);
2294 return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
2298 return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
2316 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
2343 static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
2368 return SDValue(ShiftNode, 0);
2373 static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
2375 SDValue &Src, int &ShiftAmount,
2453 SDValue And = N->getOperand(0);
2513 SDValue Ops[] = {And.getOperand(0), SDValue(MOVI, 0),
2557 SDValue Dst, Src;
2560 SDValue OrOpd0Val = N->getOperand(I % 2);
2562 SDValue OrOpd1Val = N->getOperand((I + 1) % 2);
2625 SDValue Ops[] = {Dst, Src, CurDAG->getTargetConstant(ImmR, DL, VT),
2636 SDValue And0 = N->getOperand(0);
2637 SDValue And1 = N->getOperand(1);
2652 SDValue Src = And1->getOperand(0);
2653 SDValue Dst = And0->getOperand(0);
2670 SDValue Ops[] = {Dst, SDValue(LSR, 0),
2686 getUsefulBits(SDValue(N, 0), NUsefulBits);
2711 SDValue Op0;
2713 if (!isBitfieldPositioningOp(CurDAG, SDValue(N, 0), /*BiggerPattern=*/false,
2723 SDValue Ops[] = {Op0, CurDAG->getTargetConstant(ImmR, DL, VT),
2764 SDValue ShiftAmt = N->getOperand(1);
2766 SDValue NewShiftAmt;
2774 SDValue Add0 = ShiftAmt->getOperand(0);
2775 SDValue Add1 = ShiftAmt->getOperand(1);
2798 SDValue Zero =
2802 NewShiftAmt = SDValue(Neg, 0);
2824 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, DL, MVT::i32);
2828 NewShiftAmt = SDValue(Ext, 0);
2831 SDValue Ops[] = {N->getOperand(0), NewShiftAmt};
2837 AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
3042 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
3051 ReplaceUses(SDValue(N, 0), SDValue(CmpSwap, 0));
3052 ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 2));
3058 bool AArch64DAGToDAGISel::SelectSVE8BitLslImm(SDValue N, SDValue &Base,
3059 SDValue &Offset) {
3084 bool AArch64DAGToDAGISel::SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift) {
3118 bool AArch64DAGToDAGISel::SelectSVESignedArithImm(SDValue N, SDValue &Imm) {
3130 bool AArch64DAGToDAGISel::SelectSVEArithImm(SDValue N, SDValue &Imm) {
3143 bool AArch64DAGToDAGISel::SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm) {
3183 bool AArch64DAGToDAGISel::SelectSVEShiftImm64(SDValue N, uint64_t Low,
3184 uint64_t High, SDValue &Imm) {
3206 SDValue IRG_SP = N->getOperand(2);
3216 SDValue FiOp = CurDAG->getTargetFrameIndex(
3242 {SDValue(N1, 0), N->getOperand(2)});
3245 {SDValue(N2, 0), CurDAG->getTargetConstant(0, DL, MVT::i64),
3252 static SDNode *extractSubReg(SelectionDAG *DAG, EVT VT, SDValue V) {
3279 static SDNode *insertSubReg(SelectionDAG *DAG, EVT VT, SDValue V) {
3292 SDValue(Container, 0), V, SubReg);
3298 SDValue(Container, 0), V, SubReg);
3432 SDValue New = CurDAG->getCopyFromReg(
3437 SDValue New = CurDAG->getCopyFromReg(
3451 SDValue TFI = CurDAG->getTargetFrameIndex(
3454 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, DL, MVT::i32),
3468 SDValue MemAddr = Node->getOperand(2);
3470 SDValue Chain = Node->getOperand(0);
3487 SDValue Chain = Node->getOperand(0);
3488 SDValue ValLo = Node->getOperand(2);
3489 SDValue ValHi = Node->getOperand(3);
3490 SDValue MemAddr = Node->getOperand(4);
3493 SDValue Ops[] = {ValLo, ValHi, MemAddr, Chain};
4876 bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
4877 SDValue &Base,
4878 SDValue &OffImm) {
4887 SDValue VScale = N.getOperand(1);
4909 bool AArch64DAGToDAGISel::SelectSVERegRegAddrMode(SDValue N, unsigned Scale,
4910 SDValue &Base,
4911 SDValue &Offset) {
4916 const SDValue LHS = N.getOperand(0);
4917 const SDValue RHS = N.getOperand(1);
4931 const SDValue ShiftRHS = RHS.getOperand(1);