Lines Matching refs:SDValue
475 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
492 SDValue Result = LowerLOAD(Op, DAG);
503 SDValue Chain = Op.getOperand(0);
509 const SDValue Args[8] = {
548 SDValue TexArgs[19] = {
572 SDValue Args[8] = {
655 return SDValue();
659 SmallVectorImpl<SDValue> &Results,
680 SDValue Result;
686 SDValue Op = SDValue(N, 1);
687 SDValue RES = LowerSDIVREM(Op, DAG);
693 SDValue Op = SDValue(N, 0);
700 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
701 SDValue Vector) const {
705 SmallVector<SDValue, 8> Args;
715 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
718 SDValue Vector = Op.getOperand(0);
719 SDValue Index = Op.getOperand(1);
730 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
733 SDValue Vector = Op.getOperand(0);
734 SDValue Value = Op.getOperand(1);
735 SDValue Index = Op.getOperand(2);
742 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
747 SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
748 SDValue Op,
758 SDValue GA = DAG.getTargetGlobalAddress(GV, SDLoc(GSD), ConstPtrVT);
762 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
766 SDValue Arg = Op.getOperand(0);
770 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
786 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT,
796 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
800 SDValue Lo = Op.getOperand(0);
801 SDValue Hi = Op.getOperand(1);
802 SDValue Shift = Op.getOperand(2);
803 SDValue Zero = DAG.getConstant(0, DL, VT);
804 SDValue One = DAG.getConstant(1, DL, VT);
806 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT);
807 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
808 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
809 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
816 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
819 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
821 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
823 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
824 SDValue LoBig = Zero;
832 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
836 SDValue Lo = Op.getOperand(0);
837 SDValue Hi = Op.getOperand(1);
838 SDValue Shift = Op.getOperand(2);
839 SDValue Zero = DAG.getConstant(0, DL, VT);
840 SDValue One = DAG.getConstant(1, DL, VT);
844 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT);
845 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
846 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
847 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
854 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
857 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
858 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
861 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
862 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
870 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
875 SDValue Lo = Op.getOperand(0);
876 SDValue Hi = Op.getOperand(1);
878 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi);
883 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi);
888 SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const {
898 SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const {
908 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
923 bool R600TargetLowering::isZero(SDValue Op) const {
933 bool R600TargetLowering::isHWTrueValue(SDValue Op) const {
940 bool R600TargetLowering::isHWFalseValue(SDValue Op) const {
947 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
951 SDValue LHS = Op.getOperand(0);
952 SDValue RHS = Op.getOperand(1);
953 SDValue True = Op.getOperand(2);
954 SDValue False = Op.getOperand(3);
955 SDValue CC = Op.getOperand(4);
956 SDValue Temp;
960 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
1032 SDValue Cond = LHS;
1033 SDValue Zero = RHS;
1056 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1065 SDValue HWTrue, HWFalse;
1080 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1093 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1144 SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store,
1152 SDValue Mask;
1163 SDValue OldChain = Store->getChain();
1166 SDValue Chain = VectorTrunc ? OldChain->getOperand(0) : OldChain;
1167 SDValue BasePtr = Store->getBasePtr();
1168 SDValue Offset = Store->getOffset();
1171 SDValue LoadPtr = BasePtr;
1178 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1184 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1189 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1193 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1198 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1202 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1205 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1209 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt);
1219 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1223 SDValue NewStore = DAG.getStore(Chain, DL, Value, Ptr, PtrInfo);
1234 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1238 SDValue Chain = StoreNode->getChain();
1239 SDValue Ptr = StoreNode->getBasePtr();
1240 SDValue Value = StoreNode->getValue();
1256 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain);
1258 SDValue NewStore = DAG.getTruncStore(
1276 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr,
1284 SDValue MaskConstant;
1293 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr,
1295 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1299 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift);
1302 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1303 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift);
1307 SDValue Src[4] = {
1313 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src);
1314 SDValue Args[3] = { Chain, Input, DWordAddr };
1333 return SDValue();
1346 return SDValue();
1390 SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op,
1398 SDValue BasePtr = Load->getBasePtr();
1399 SDValue Chain = Load->getChain();
1400 SDValue Offset = Load->getOffset();
1402 SDValue LoadPtr = BasePtr;
1409 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1415 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1418 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1422 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1426 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt);
1432 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1438 SDValue Ops[] = {
1446 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1459 SDValue Chain = LoadNode->getChain();
1460 SDValue Ptr = LoadNode->getBasePtr();
1465 SDValue Ops[2];
1475 SDValue Result;
1495 SDValue MergedValues[2] = {
1502 // For most operations returning SDValue() will result in the node being
1511 SDValue NewLoad = DAG.getExtLoad(
1514 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad,
1517 SDValue MergedValues[2] = { Res, Chain };
1522 return SDValue();
1532 return SDValue();
1535 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1536 SDValue Chain = Op.getOperand(0);
1537 SDValue Cond = Op.getOperand(1);
1538 SDValue Jump = Op.getOperand(2);
1544 SDValue R600TargetLowering::lowerFrameIndex(SDValue Op,
1584 SDValue R600TargetLowering::LowerFormalArguments(
1585 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1587 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1612 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1641 SDValue Arg = DAG.getLoad(
1689 static SDValue CompactSwizzlableVector(
1690 SelectionDAG &DAG, SDValue VectorEntry,
1697 SDValue NewBldVec[4];
1734 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1741 SDValue NewBldVec[4];
1774 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4],
1798 SDValue R600TargetLowering::constBufferLoad(LoadSDNode *LoadNode, int Block,
1802 SDValue Chain = LoadNode->getChain();
1803 SDValue Ptr = LoadNode->getBasePtr();
1808 return SDValue();
1811 return SDValue();
1815 SDValue Slots[4];
1822 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1832 SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements));
1837 SDValue MergedValues[2] = {
1848 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1856 SDValue Arg = N->getOperand(0);
1870 SDValue FNeg = N->getOperand(0);
1872 return SDValue();
1874 SDValue SelectCC = FNeg.getOperand(0);
1880 return SDValue();
1894 SDValue InVec = N->getOperand(0);
1895 SDValue InVal = N->getOperand(1);
1896 SDValue EltNo = N->getOperand(2);
1906 return SDValue();
1910 return SDValue();
1916 SmallVector<SDValue, 8> Ops;
1924 return SDValue();
1946 SDValue Arg = N->getOperand(0);
1968 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI))
1976 SDValue LHS = N->getOperand(0);
1978 return SDValue();
1981 SDValue RHS = N->getOperand(1);
1982 SDValue True = N->getOperand(2);
1983 SDValue False = N->getOperand(3);
1989 return SDValue();
1993 default: return SDValue();
2009 return SDValue();
2013 SDValue Arg = N->getOperand(1);
2017 SDValue NewArgs[8] = {
2019 SDValue(),
2031 SDValue Arg = N->getOperand(1);
2035 SDValue NewArgs[19] = {
2062 SDValue Ptr = LoadNode->getBasePtr();
2076 SDValue &Src, SDValue &Neg, SDValue &Abs,
2077 SDValue &Sel, SDValue &Imm,
2103 SDValue CstOffset = Src.getOperand(0);
2214 SDValue FakeOp;
2216 std::vector<SDValue> Ops(Node->op_begin(), Node->op_end());
2252 SDValue &Src = Ops[OperandIdx[i] - 1];
2253 SDValue &Neg = Ops[NegIdx[i] - 1];
2254 SDValue &Abs = Ops[AbsIdx[i] - 1];
2259 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2265 SDValue &Src = Ops[i];
2290 SDValue &Src = Ops[OperandIdx[i] - 1];
2291 SDValue &Neg = Ops[NegIdx[i] - 1];
2292 SDValue FakeAbs;
2293 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2301 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2302 SDValue &Imm = Ops[ImmIdx];