Searched refs:intel_de_posting_read (Results 1 - 25 of 31) sorted by relevance

12

/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_fdi.c435 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
494 intel_de_posting_read(dev_priv, reg);
547 intel_de_posting_read(dev_priv, reg);
575 intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
629 intel_de_posting_read(dev_priv, reg);
658 intel_de_posting_read(dev_priv, reg);
664 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
709 intel_de_posting_read(dev_priv, reg);
715 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
767 intel_de_posting_read(dev_pri
[all...]
H A Dg4x_hdmi.c62 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
233 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
297 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
299 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
312 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
319 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
321 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
360 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
367 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
398 intel_de_posting_read(dev_pri
[all...]
H A Dintel_fifo_underrun.c107 intel_de_posting_read(dev_priv, reg);
127 intel_de_posting_read(dev_priv, reg);
160 intel_de_posting_read(dev_priv, GEN7_ERR_INT);
248 intel_de_posting_read(dev_priv, SERR_INT);
H A Dintel_dkl_phy.c112 intel_de_posting_read(i915, DKL_REG_MMIO(reg));
H A Dintel_vga.c45 intel_de_posting_read(dev_priv, vga_reg);
H A Dg4x_dp.c211 intel_de_posting_read(dev_priv, DP_A);
226 intel_de_posting_read(dev_priv, DP_A);
245 intel_de_posting_read(dev_priv, DP_A);
433 intel_de_posting_read(dev_priv, intel_dp->output_reg);
437 intel_de_posting_read(dev_priv, intel_dp->output_reg);
457 intel_de_posting_read(dev_priv, intel_dp->output_reg);
461 intel_de_posting_read(dev_priv, intel_dp->output_reg);
618 intel_de_posting_read(dev_priv, intel_dp->output_reg);
646 intel_de_posting_read(dev_priv, intel_dp->output_reg);
668 intel_de_posting_read(dev_pri
[all...]
H A Dintel_pipe_crc.c612 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
647 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
662 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
H A Dintel_pps.c147 intel_de_posting_read(dev_priv, intel_dp->output_reg);
150 intel_de_posting_read(dev_priv, intel_dp->output_reg);
153 intel_de_posting_read(dev_priv, intel_dp->output_reg);
751 intel_de_posting_read(dev_priv, pp_ctrl_reg);
821 intel_de_posting_read(dev_priv, pp_ctrl_reg);
948 intel_de_posting_read(dev_priv, pp_ctrl_reg);
956 intel_de_posting_read(dev_priv, pp_ctrl_reg);
964 intel_de_posting_read(dev_priv, pp_ctrl_reg);
1011 intel_de_posting_read(dev_priv, pp_ctrl_reg);
1055 intel_de_posting_read(dev_pri
[all...]
H A Dintel_pch_refclk.c616 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
635 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
646 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
660 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
H A Dintel_hdmi.c242 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
313 intel_de_posting_read(dev_priv, reg);
391 intel_de_posting_read(dev_priv, reg);
463 intel_de_posting_read(dev_priv, reg);
542 intel_de_posting_read(dev_priv, ctl_reg);
899 intel_de_posting_read(dev_priv, reg);
919 intel_de_posting_read(dev_priv, reg);
1071 intel_de_posting_read(dev_priv, reg);
1092 intel_de_posting_read(dev_priv, reg);
1128 intel_de_posting_read(dev_pri
[all...]
H A Dintel_dvo.c195 intel_de_posting_read(i915, DVO(port));
212 intel_de_posting_read(i915, DVO(port));
H A Dhsw_ips.c83 intel_de_posting_read(i915, IPS_CTL);
H A Dintel_de.h76 #define intel_de_posting_read(p,...) __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__) macro
H A Dintel_dpll_mgr.c574 intel_de_posting_read(i915, PCH_DPLL(id));
583 intel_de_posting_read(i915, PCH_DPLL(id));
593 intel_de_posting_read(i915, PCH_DPLL(id));
696 intel_de_posting_read(i915, WRPLL_CTL(id));
707 intel_de_posting_read(i915, SPLL_CTL);
717 intel_de_posting_read(i915, WRPLL_CTL(id));
733 intel_de_posting_read(i915, SPLL_CTL);
1371 intel_de_posting_read(i915, DPLL_CTRL1);
1386 intel_de_posting_read(i915, regs[id].cfgcr1);
1387 intel_de_posting_read(i91
[all...]
H A Dintel_backlight.c502 intel_de_posting_read(i915, BLC_PWM_PCH_CTL1);
539 intel_de_posting_read(i915, BLC_PWM_CPU_CTL2);
553 intel_de_posting_read(i915, BLC_PWM_PCH_CTL1);
583 intel_de_posting_read(i915, BLC_PWM_CTL);
627 intel_de_posting_read(i915, BLC_PWM_CTL2);
660 intel_de_posting_read(i915, VLV_BLC_PWM_CTL2(pipe));
709 intel_de_posting_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller));
740 intel_de_posting_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller));
H A Dintel_dpll.c1849 intel_de_posting_read(dev_priv, DPLL(pipe));
1866 intel_de_posting_read(dev_priv, DPLL(pipe));
1995 intel_de_posting_read(dev_priv, DPLL(pipe));
2024 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
2190 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
2245 intel_de_posting_read(dev_priv, DPLL(pipe));
2263 intel_de_posting_read(dev_priv, DPLL(pipe));
2289 intel_de_posting_read(dev_priv, DPLL(pipe));
H A Dintel_crt.c505 intel_de_posting_read(dev_priv, crt->adpa_reg);
728 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
965 intel_de_posting_read(dev_priv, crt->adpa_reg);
H A Dintel_display_power.c1060 intel_de_posting_read(dev_priv, reg);
1255 intel_de_posting_read(dev_priv, D_COMP_BDW);
1289 intel_de_posting_read(dev_priv, LCPLL_CTL);
1305 intel_de_posting_read(dev_priv, LCPLL_CTL);
1332 intel_de_posting_read(dev_priv, LCPLL_CTL);
H A Dicl_dsi.c364 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
370 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
377 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
672 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
H A Dintel_lvds.c325 intel_de_posting_read(dev_priv, lvds_encoder->reg);
348 intel_de_posting_read(dev_priv, lvds_encoder->reg);
H A Dintel_gmbus.c288 intel_de_posting_read(i915, bus->gpio_reg);
305 intel_de_posting_read(i915, bus->gpio_reg);
H A Dvlv_dsi_pll.c547 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL);
H A Dintel_ddi.c1476 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
2319 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3312 intel_de_posting_read(dev_priv, reg);
3566 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3583 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3611 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3626 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3634 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
H A Dintel_display.c468 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2948 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3178 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3208 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
8193 intel_de_posting_read(dev_priv, DPLL(pipe));
8206 intel_de_posting_read(dev_priv, DPLL(pipe));
8211 intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8235 intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8240 intel_de_posting_read(dev_priv, DPLL(pipe));
H A Dvlv_dsi.c659 intel_de_posting_read(display, port_ctrl);
675 intel_de_posting_read(display, port_ctrl);

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