1/* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright �� 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30#include <linux/export.h> 31#include <linux/i2c-algo-bit.h> 32#include <linux/i2c.h> 33 34#include <drm/display/drm_hdcp_helper.h> 35 36#include "i915_drv.h" 37#include "i915_irq.h" 38#include "i915_reg.h" 39#include "intel_de.h" 40#include "intel_display_types.h" 41#include "intel_gmbus.h" 42#include "intel_gmbus_regs.h" 43 44struct intel_gmbus { 45 struct i2c_adapter adapter; 46#define GMBUS_FORCE_BIT_RETRY (1U << 31) 47 u32 force_bit; 48 u32 reg0; 49 i915_reg_t gpio_reg; 50 struct i2c_algo_bit_data bit_algo; 51 struct drm_i915_private *i915; 52}; 53 54enum gmbus_gpio { 55 GPIOA, 56 GPIOB, 57 GPIOC, 58 GPIOD, 59 GPIOE, 60 GPIOF, 61 GPIOG, 62 GPIOH, 63 __GPIOI_UNUSED, 64 GPIOJ, 65 GPIOK, 66 GPIOL, 67 GPIOM, 68 GPION, 69 GPIOO, 70}; 71 72struct gmbus_pin { 73 const char *name; 74 enum gmbus_gpio gpio; 75}; 76 77/* Map gmbus pin pairs to names and registers. */ 78static const struct gmbus_pin gmbus_pins[] = { 79 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 80 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 81 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 82 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 83 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 84 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 85}; 86 87static const struct gmbus_pin gmbus_pins_bdw[] = { 88 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 89 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 90 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 91 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 92}; 93 94static const struct gmbus_pin gmbus_pins_skl[] = { 95 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 96 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 97 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 98}; 99 100static const struct gmbus_pin gmbus_pins_bxt[] = { 101 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 102 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 103 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 104}; 105 106static const struct gmbus_pin gmbus_pins_cnp[] = { 107 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 108 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 109 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 110 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 111}; 112 113static const struct gmbus_pin gmbus_pins_icp[] = { 114 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 115 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 116 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 117 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 118 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 119 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 120 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 121 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 122 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 123}; 124 125static const struct gmbus_pin gmbus_pins_dg1[] = { 126 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 127 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 128 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 129 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 130}; 131 132static const struct gmbus_pin gmbus_pins_dg2[] = { 133 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 134 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 135 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 136 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 137 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 138}; 139 140static const struct gmbus_pin gmbus_pins_mtp[] = { 141 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 142 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 143 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 144 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 145 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 146 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 147 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 148 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 149 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 150}; 151 152static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 153 unsigned int pin) 154{ 155 const struct gmbus_pin *pins; 156 size_t size; 157 158 if (INTEL_PCH_TYPE(i915) >= PCH_MTL) { 159 pins = gmbus_pins_mtp; 160 size = ARRAY_SIZE(gmbus_pins_mtp); 161 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 162 pins = gmbus_pins_dg2; 163 size = ARRAY_SIZE(gmbus_pins_dg2); 164 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 165 pins = gmbus_pins_dg1; 166 size = ARRAY_SIZE(gmbus_pins_dg1); 167 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 168 pins = gmbus_pins_icp; 169 size = ARRAY_SIZE(gmbus_pins_icp); 170 } else if (HAS_PCH_CNP(i915)) { 171 pins = gmbus_pins_cnp; 172 size = ARRAY_SIZE(gmbus_pins_cnp); 173 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 174 pins = gmbus_pins_bxt; 175 size = ARRAY_SIZE(gmbus_pins_bxt); 176 } else if (DISPLAY_VER(i915) == 9) { 177 pins = gmbus_pins_skl; 178 size = ARRAY_SIZE(gmbus_pins_skl); 179 } else if (IS_BROADWELL(i915)) { 180 pins = gmbus_pins_bdw; 181 size = ARRAY_SIZE(gmbus_pins_bdw); 182 } else { 183 pins = gmbus_pins; 184 size = ARRAY_SIZE(gmbus_pins); 185 } 186 187 if (pin >= size || !pins[pin].name) 188 return NULL; 189 190 return &pins[pin]; 191} 192 193bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) 194{ 195 return get_gmbus_pin(i915, pin); 196} 197 198/* Intel GPIO access functions */ 199 200#define I2C_RISEFALL_TIME 10 201 202static inline struct intel_gmbus * 203to_intel_gmbus(struct i2c_adapter *i2c) 204{ 205 return container_of(i2c, struct intel_gmbus, adapter); 206} 207 208void 209intel_gmbus_reset(struct drm_i915_private *i915) 210{ 211 intel_de_write(i915, GMBUS0(i915), 0); 212 intel_de_write(i915, GMBUS4(i915), 0); 213} 214 215static void pnv_gmbus_clock_gating(struct drm_i915_private *i915, 216 bool enable) 217{ 218 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 219 intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 220 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 221} 222 223static void pch_gmbus_clock_gating(struct drm_i915_private *i915, 224 bool enable) 225{ 226 intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 227 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 228} 229 230static void bxt_gmbus_clock_gating(struct drm_i915_private *i915, 231 bool enable) 232{ 233 intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, 234 !enable ? BXT_GMBUS_GATING_DIS : 0); 235} 236 237static u32 get_reserved(struct intel_gmbus *bus) 238{ 239 struct drm_i915_private *i915 = bus->i915; 240 u32 reserved = 0; 241 242 /* On most chips, these bits must be preserved in software. */ 243 if (!IS_I830(i915) && !IS_I845G(i915)) 244 reserved = intel_de_read_notrace(i915, bus->gpio_reg) & 245 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 246 247 return reserved; 248} 249 250static int get_clock(void *data) 251{ 252 struct intel_gmbus *bus = data; 253 struct drm_i915_private *i915 = bus->i915; 254 u32 reserved = get_reserved(bus); 255 256 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 257 intel_de_write_notrace(i915, bus->gpio_reg, reserved); 258 259 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 260} 261 262static int get_data(void *data) 263{ 264 struct intel_gmbus *bus = data; 265 struct drm_i915_private *i915 = bus->i915; 266 u32 reserved = get_reserved(bus); 267 268 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 269 intel_de_write_notrace(i915, bus->gpio_reg, reserved); 270 271 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 272} 273 274static void set_clock(void *data, int state_high) 275{ 276 struct intel_gmbus *bus = data; 277 struct drm_i915_private *i915 = bus->i915; 278 u32 reserved = get_reserved(bus); 279 u32 clock_bits; 280 281 if (state_high) 282 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 283 else 284 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 285 GPIO_CLOCK_VAL_MASK; 286 287 intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits); 288 intel_de_posting_read(i915, bus->gpio_reg); 289} 290 291static void set_data(void *data, int state_high) 292{ 293 struct intel_gmbus *bus = data; 294 struct drm_i915_private *i915 = bus->i915; 295 u32 reserved = get_reserved(bus); 296 u32 data_bits; 297 298 if (state_high) 299 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 300 else 301 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 302 GPIO_DATA_VAL_MASK; 303 304 intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits); 305 intel_de_posting_read(i915, bus->gpio_reg); 306} 307 308static int 309intel_gpio_pre_xfer(struct i2c_adapter *adapter) 310{ 311 struct intel_gmbus *bus = to_intel_gmbus(adapter); 312 struct drm_i915_private *i915 = bus->i915; 313 314 intel_gmbus_reset(i915); 315 316 if (IS_PINEVIEW(i915)) 317 pnv_gmbus_clock_gating(i915, false); 318 319 set_data(bus, 1); 320 set_clock(bus, 1); 321 udelay(I2C_RISEFALL_TIME); 322 return 0; 323} 324 325static void 326intel_gpio_post_xfer(struct i2c_adapter *adapter) 327{ 328 struct intel_gmbus *bus = to_intel_gmbus(adapter); 329 struct drm_i915_private *i915 = bus->i915; 330 331 set_data(bus, 1); 332 set_clock(bus, 1); 333 334 if (IS_PINEVIEW(i915)) 335 pnv_gmbus_clock_gating(i915, true); 336} 337 338static void 339intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 340{ 341 struct i2c_algo_bit_data *algo; 342 343 algo = &bus->bit_algo; 344 345 bus->gpio_reg = gpio_reg; 346 bus->adapter.algo_data = algo; 347 algo->setsda = set_data; 348 algo->setscl = set_clock; 349 algo->getsda = get_data; 350 algo->getscl = get_clock; 351 algo->pre_xfer = intel_gpio_pre_xfer; 352 algo->post_xfer = intel_gpio_post_xfer; 353 algo->udelay = I2C_RISEFALL_TIME; 354 algo->timeout = usecs_to_jiffies(2200); 355 algo->data = bus; 356} 357 358static bool has_gmbus_irq(struct drm_i915_private *i915) 359{ 360 /* 361 * encoder->shutdown() may want to use GMBUS 362 * after irqs have already been disabled. 363 */ 364 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 365} 366 367static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en) 368{ 369 DEFINE_WAIT(wait); 370 u32 gmbus2; 371 int ret; 372 373 /* Important: The hw handles only the first bit, so set only one! Since 374 * we also need to check for NAKs besides the hw ready/idle signal, we 375 * need to wake up periodically and check that ourselves. 376 */ 377 if (!has_gmbus_irq(i915)) 378 irq_en = 0; 379 380 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 381 intel_de_write_fw(i915, GMBUS4(i915), irq_en); 382 383 status |= GMBUS_SATOER; 384 ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 385 2); 386 if (ret) 387 ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 388 50); 389 390 intel_de_write_fw(i915, GMBUS4(i915), 0); 391 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 392 393 if (gmbus2 & GMBUS_SATOER) 394 return -ENXIO; 395 396 return ret; 397} 398 399static int 400gmbus_wait_idle(struct drm_i915_private *i915) 401{ 402 DEFINE_WAIT(wait); 403 u32 irq_enable; 404 int ret; 405 406 /* Important: The hw handles only the first bit, so set only one! */ 407 irq_enable = 0; 408 if (has_gmbus_irq(i915)) 409 irq_enable = GMBUS_IDLE_EN; 410 411 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 412 intel_de_write_fw(i915, GMBUS4(i915), irq_enable); 413 414 ret = intel_de_wait_for_register_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10); 415 416 intel_de_write_fw(i915, GMBUS4(i915), 0); 417 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 418 419 return ret; 420} 421 422static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915) 423{ 424 return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 425 GMBUS_BYTE_COUNT_MAX; 426} 427 428static int 429gmbus_xfer_read_chunk(struct drm_i915_private *i915, 430 unsigned short addr, u8 *buf, unsigned int len, 431 u32 gmbus0_reg, u32 gmbus1_index) 432{ 433 unsigned int size = len; 434 bool burst_read = len > gmbus_max_xfer_size(i915); 435 bool extra_byte_added = false; 436 437 if (burst_read) { 438 /* 439 * As per HW Spec, for 512Bytes need to read extra Byte and 440 * Ignore the extra byte read. 441 */ 442 if (len == 512) { 443 extra_byte_added = true; 444 len++; 445 } 446 size = len % 256 + 256; 447 intel_de_write_fw(i915, GMBUS0(i915), 448 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 449 } 450 451 intel_de_write_fw(i915, GMBUS1(i915), 452 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 453 while (len) { 454 int ret; 455 u32 val, loop = 0; 456 457 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 458 if (ret) 459 return ret; 460 461 val = intel_de_read_fw(i915, GMBUS3(i915)); 462 do { 463 if (extra_byte_added && len == 1) 464 break; 465 466 *buf++ = val & 0xff; 467 val >>= 8; 468 } while (--len && ++loop < 4); 469 470 if (burst_read && len == size - 4) 471 /* Reset the override bit */ 472 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg); 473 } 474 475 return 0; 476} 477 478/* 479 * HW spec says that 512Bytes in Burst read need special treatment. 480 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 481 * an I2C slave, which supports such a lengthy burst read too for experiments. 482 * 483 * So until things get clarified on HW support, to avoid the burst read length 484 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 485 */ 486#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 487 488static int 489gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg, 490 u32 gmbus0_reg, u32 gmbus1_index) 491{ 492 u8 *buf = msg->buf; 493 unsigned int rx_size = msg->len; 494 unsigned int len; 495 int ret; 496 497 do { 498 if (HAS_GMBUS_BURST_READ(i915)) 499 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 500 else 501 len = min(rx_size, gmbus_max_xfer_size(i915)); 502 503 ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len, 504 gmbus0_reg, gmbus1_index); 505 if (ret) 506 return ret; 507 508 rx_size -= len; 509 buf += len; 510 } while (rx_size != 0); 511 512 return 0; 513} 514 515static int 516gmbus_xfer_write_chunk(struct drm_i915_private *i915, 517 unsigned short addr, u8 *buf, unsigned int len, 518 u32 gmbus1_index) 519{ 520 unsigned int chunk_size = len; 521 u32 val, loop; 522 523 val = loop = 0; 524 while (len && loop < 4) { 525 val |= *buf++ << (8 * loop++); 526 len -= 1; 527 } 528 529 intel_de_write_fw(i915, GMBUS3(i915), val); 530 intel_de_write_fw(i915, GMBUS1(i915), 531 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 532 while (len) { 533 int ret; 534 535 val = loop = 0; 536 do { 537 val |= *buf++ << (8 * loop); 538 } while (--len && ++loop < 4); 539 540 intel_de_write_fw(i915, GMBUS3(i915), val); 541 542 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 543 if (ret) 544 return ret; 545 } 546 547 return 0; 548} 549 550static int 551gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg, 552 u32 gmbus1_index) 553{ 554 u8 *buf = msg->buf; 555 unsigned int tx_size = msg->len; 556 unsigned int len; 557 int ret; 558 559 do { 560 len = min(tx_size, gmbus_max_xfer_size(i915)); 561 562 ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len, 563 gmbus1_index); 564 if (ret) 565 return ret; 566 567 buf += len; 568 tx_size -= len; 569 } while (tx_size != 0); 570 571 return 0; 572} 573 574/* 575 * The gmbus controller can combine a 1 or 2 byte write with another read/write 576 * that immediately follows it by using an "INDEX" cycle. 577 */ 578static bool 579gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 580{ 581 return (i + 1 < num && 582 msgs[i].addr == msgs[i + 1].addr && 583 !(msgs[i].flags & I2C_M_RD) && 584 (msgs[i].len == 1 || msgs[i].len == 2) && 585 msgs[i + 1].len > 0); 586} 587 588static int 589gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs, 590 u32 gmbus0_reg) 591{ 592 u32 gmbus1_index = 0; 593 u32 gmbus5 = 0; 594 int ret; 595 596 if (msgs[0].len == 2) 597 gmbus5 = GMBUS_2BYTE_INDEX_EN | 598 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 599 if (msgs[0].len == 1) 600 gmbus1_index = GMBUS_CYCLE_INDEX | 601 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 602 603 /* GMBUS5 holds 16-bit index */ 604 if (gmbus5) 605 intel_de_write_fw(i915, GMBUS5(i915), gmbus5); 606 607 if (msgs[1].flags & I2C_M_RD) 608 ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg, 609 gmbus1_index); 610 else 611 ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index); 612 613 /* Clear GMBUS5 after each index transfer */ 614 if (gmbus5) 615 intel_de_write_fw(i915, GMBUS5(i915), 0); 616 617 return ret; 618} 619 620static int 621do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 622 u32 gmbus0_source) 623{ 624 struct intel_gmbus *bus = to_intel_gmbus(adapter); 625 struct drm_i915_private *i915 = bus->i915; 626 int i = 0, inc, try = 0; 627 int ret = 0; 628 629 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 630 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 631 bxt_gmbus_clock_gating(i915, false); 632 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 633 pch_gmbus_clock_gating(i915, false); 634 635retry: 636 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0); 637 638 for (; i < num; i += inc) { 639 inc = 1; 640 if (gmbus_is_index_xfer(msgs, i, num)) { 641 ret = gmbus_index_xfer(i915, &msgs[i], 642 gmbus0_source | bus->reg0); 643 inc = 2; /* an index transmission is two msgs */ 644 } else if (msgs[i].flags & I2C_M_RD) { 645 ret = gmbus_xfer_read(i915, &msgs[i], 646 gmbus0_source | bus->reg0, 0); 647 } else { 648 ret = gmbus_xfer_write(i915, &msgs[i], 0); 649 } 650 651 if (!ret) 652 ret = gmbus_wait(i915, 653 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 654 if (ret == -ETIMEDOUT) 655 goto timeout; 656 else if (ret) 657 goto clear_err; 658 } 659 660 /* Generate a STOP condition on the bus. Note that gmbus can't generata 661 * a STOP on the very first cycle. To simplify the code we 662 * unconditionally generate the STOP condition with an additional gmbus 663 * cycle. */ 664 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 665 666 /* Mark the GMBUS interface as disabled after waiting for idle. 667 * We will re-enable it at the start of the next xfer, 668 * till then let it sleep. 669 */ 670 if (gmbus_wait_idle(i915)) { 671 drm_dbg_kms(&i915->drm, 672 "GMBUS [%s] timed out waiting for idle\n", 673 adapter->name); 674 ret = -ETIMEDOUT; 675 } 676 intel_de_write_fw(i915, GMBUS0(i915), 0); 677 ret = ret ?: i; 678 goto out; 679 680clear_err: 681 /* 682 * Wait for bus to IDLE before clearing NAK. 683 * If we clear the NAK while bus is still active, then it will stay 684 * active and the next transaction may fail. 685 * 686 * If no ACK is received during the address phase of a transaction, the 687 * adapter must report -ENXIO. It is not clear what to return if no ACK 688 * is received at other times. But we have to be careful to not return 689 * spurious -ENXIO because that will prevent i2c and drm edid functions 690 * from retrying. So return -ENXIO only when gmbus properly quiescents - 691 * timing out seems to happen when there _is_ a ddc chip present, but 692 * it's slow responding and only answers on the 2nd retry. 693 */ 694 ret = -ENXIO; 695 if (gmbus_wait_idle(i915)) { 696 drm_dbg_kms(&i915->drm, 697 "GMBUS [%s] timed out after NAK\n", 698 adapter->name); 699 ret = -ETIMEDOUT; 700 } 701 702 /* Toggle the Software Clear Interrupt bit. This has the effect 703 * of resetting the GMBUS controller and so clearing the 704 * BUS_ERROR raised by the slave's NAK. 705 */ 706 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT); 707 intel_de_write_fw(i915, GMBUS1(i915), 0); 708 intel_de_write_fw(i915, GMBUS0(i915), 0); 709 710 drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 711 adapter->name, msgs[i].addr, 712 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 713 714 /* 715 * Passive adapters sometimes NAK the first probe. Retry the first 716 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 717 * has retries internally. See also the retry loop in 718 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 719 */ 720 if (ret == -ENXIO && i == 0 && try++ == 0) { 721 drm_dbg_kms(&i915->drm, 722 "GMBUS [%s] NAK on first message, retry\n", 723 adapter->name); 724 goto retry; 725 } 726 727 goto out; 728 729timeout: 730 drm_dbg_kms(&i915->drm, 731 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 732 bus->adapter.name, bus->reg0 & 0xff); 733 intel_de_write_fw(i915, GMBUS0(i915), 0); 734 735 /* 736 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 737 * instead. Use EAGAIN to have i2c core retry. 738 */ 739 ret = -EAGAIN; 740 741out: 742 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 743 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 744 bxt_gmbus_clock_gating(i915, true); 745 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 746 pch_gmbus_clock_gating(i915, true); 747 748 return ret; 749} 750 751static int 752gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 753{ 754 struct intel_gmbus *bus = to_intel_gmbus(adapter); 755 struct drm_i915_private *i915 = bus->i915; 756 intel_wakeref_t wakeref; 757 int ret; 758 759 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 760 761 if (bus->force_bit) { 762 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 763 if (ret < 0) 764 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 765 } else { 766 ret = do_gmbus_xfer(adapter, msgs, num, 0); 767 if (ret == -EAGAIN) 768 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 769 } 770 771 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 772 773 return ret; 774} 775 776int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 777{ 778 struct intel_gmbus *bus = to_intel_gmbus(adapter); 779 struct drm_i915_private *i915 = bus->i915; 780 u8 cmd = DRM_HDCP_DDC_AKSV; 781 u8 buf[DRM_HDCP_KSV_LEN] = {}; 782 struct i2c_msg msgs[] = { 783 { 784 .addr = DRM_HDCP_DDC_ADDR, 785 .flags = 0, 786 .len = sizeof(cmd), 787 .buf = &cmd, 788 }, 789 { 790 .addr = DRM_HDCP_DDC_ADDR, 791 .flags = 0, 792 .len = sizeof(buf), 793 .buf = buf, 794 } 795 }; 796 intel_wakeref_t wakeref; 797 int ret; 798 799 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 800 mutex_lock(&i915->display.gmbus.mutex); 801 802 /* 803 * In order to output Aksv to the receiver, use an indexed write to 804 * pass the i2c command, and tell GMBUS to use the HW-provided value 805 * instead of sourcing GMBUS3 for the data. 806 */ 807 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 808 809 mutex_unlock(&i915->display.gmbus.mutex); 810 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 811 812 return ret; 813} 814 815static u32 gmbus_func(struct i2c_adapter *adapter) 816{ 817 return i2c_bit_algo.functionality(adapter) & 818 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 819 /* I2C_FUNC_10BIT_ADDR | */ 820 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 821 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 822} 823 824static const struct i2c_algorithm gmbus_algorithm = { 825 .master_xfer = gmbus_xfer, 826 .functionality = gmbus_func 827}; 828 829static void gmbus_lock_bus(struct i2c_adapter *adapter, 830 unsigned int flags) 831{ 832 struct intel_gmbus *bus = to_intel_gmbus(adapter); 833 struct drm_i915_private *i915 = bus->i915; 834 835 mutex_lock(&i915->display.gmbus.mutex); 836} 837 838static int gmbus_trylock_bus(struct i2c_adapter *adapter, 839 unsigned int flags) 840{ 841 struct intel_gmbus *bus = to_intel_gmbus(adapter); 842 struct drm_i915_private *i915 = bus->i915; 843 844 return mutex_trylock(&i915->display.gmbus.mutex); 845} 846 847static void gmbus_unlock_bus(struct i2c_adapter *adapter, 848 unsigned int flags) 849{ 850 struct intel_gmbus *bus = to_intel_gmbus(adapter); 851 struct drm_i915_private *i915 = bus->i915; 852 853 mutex_unlock(&i915->display.gmbus.mutex); 854} 855 856static const struct i2c_lock_operations gmbus_lock_ops = { 857 .lock_bus = gmbus_lock_bus, 858 .trylock_bus = gmbus_trylock_bus, 859 .unlock_bus = gmbus_unlock_bus, 860}; 861 862/** 863 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 864 * @i915: i915 device private 865 */ 866int intel_gmbus_setup(struct drm_i915_private *i915) 867{ 868 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 869 unsigned int pin; 870 int ret; 871 872 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 873 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE; 874 else if (!HAS_GMCH(i915)) 875 /* 876 * Broxton uses the same PCH offsets for South Display Engine, 877 * even though it doesn't have a PCH. 878 */ 879 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE; 880 881 mutex_init(&i915->display.gmbus.mutex); 882 init_waitqueue_head(&i915->display.gmbus.wait_queue); 883 884 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 885 const struct gmbus_pin *gmbus_pin; 886 struct intel_gmbus *bus; 887 888 gmbus_pin = get_gmbus_pin(i915, pin); 889 if (!gmbus_pin) 890 continue; 891 892 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 893 if (!bus) { 894 ret = -ENOMEM; 895 goto err; 896 } 897 898 bus->adapter.owner = THIS_MODULE; 899 snprintf(bus->adapter.name, 900 sizeof(bus->adapter.name), 901 "i915 gmbus %s", gmbus_pin->name); 902 903 bus->adapter.dev.parent = &pdev->dev; 904 bus->i915 = i915; 905 906 bus->adapter.algo = &gmbus_algorithm; 907 bus->adapter.lock_ops = &gmbus_lock_ops; 908 909 /* 910 * We wish to retry with bit banging 911 * after a timed out GMBUS attempt. 912 */ 913 bus->adapter.retries = 1; 914 915 /* By default use a conservative clock rate */ 916 bus->reg0 = pin | GMBUS_RATE_100KHZ; 917 918 /* gmbus seems to be broken on i830 */ 919 if (IS_I830(i915)) 920 bus->force_bit = 1; 921 922 intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio)); 923 924 ret = i2c_add_adapter(&bus->adapter); 925 if (ret) { 926 kfree(bus); 927 goto err; 928 } 929 930 i915->display.gmbus.bus[pin] = bus; 931 } 932 933 intel_gmbus_reset(i915); 934 935 return 0; 936 937err: 938 intel_gmbus_teardown(i915); 939 940 return ret; 941} 942 943struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915, 944 unsigned int pin) 945{ 946 if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) || 947 !i915->display.gmbus.bus[pin])) 948 return NULL; 949 950 return &i915->display.gmbus.bus[pin]->adapter; 951} 952 953void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 954{ 955 struct intel_gmbus *bus = to_intel_gmbus(adapter); 956 struct drm_i915_private *i915 = bus->i915; 957 958 mutex_lock(&i915->display.gmbus.mutex); 959 960 bus->force_bit += force_bit ? 1 : -1; 961 drm_dbg_kms(&i915->drm, 962 "%sabling bit-banging on %s. force bit now %d\n", 963 force_bit ? "en" : "dis", adapter->name, 964 bus->force_bit); 965 966 mutex_unlock(&i915->display.gmbus.mutex); 967} 968 969bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 970{ 971 struct intel_gmbus *bus = to_intel_gmbus(adapter); 972 973 return bus->force_bit; 974} 975 976void intel_gmbus_teardown(struct drm_i915_private *i915) 977{ 978 unsigned int pin; 979 980 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 981 struct intel_gmbus *bus; 982 983 bus = i915->display.gmbus.bus[pin]; 984 if (!bus) 985 continue; 986 987 i2c_del_adapter(&bus->adapter); 988 989 kfree(bus); 990 i915->display.gmbus.bus[pin] = NULL; 991 } 992} 993 994void intel_gmbus_irq_handler(struct drm_i915_private *i915) 995{ 996 wake_up_all(&i915->display.gmbus.wait_queue); 997} 998