Searched refs:ResultReg (Results 1 - 16 of 16) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp368 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); local
370 ResultReg)
374 return ResultReg;
391 unsigned ResultReg = createResultReg(RC); local
393 ResultReg).addReg(ZeroReg, getKillRegState(true));
394 return ResultReg;
427 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
429 TII.get(TargetOpcode::COPY), ResultReg)
432 return ResultReg;
445 unsigned ResultReg local
469 unsigned ResultReg; local
1054 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); local
1065 unsigned ResultReg = 0; local
1103 unsigned ResultReg; local
1210 unsigned ResultReg = 0; local
1335 unsigned ResultReg; local
1380 unsigned ResultReg; local
1422 unsigned ResultReg; local
1467 unsigned ResultReg; local
1565 unsigned ResultReg; local
1627 unsigned ResultReg = 0; local
1725 unsigned ResultReg = local
1768 unsigned ResultReg = local
1894 unsigned ResultReg = createResultReg(RC); local
1928 unsigned ResultReg; local
1954 unsigned ResultReg; local
2023 unsigned ResultReg = local
2575 unsigned ResultReg = 0; local
2701 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, local
2831 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, local
2846 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass); local
2862 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass); local
2895 unsigned ResultReg = createResultReg( local
2943 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, local
3051 unsigned ResultReg = createResultReg(RC); local
3176 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); local
3366 unsigned ResultReg = emitLoad(VT, VT, Src); local
3511 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); local
3645 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
3676 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill); local
3978 unsigned ResultReg; local
4021 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1); local
4104 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, local
4132 unsigned ResultReg = createResultReg(RC); local
4211 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, local
4239 unsigned ResultReg = createResultReg(RC); local
4332 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, local
4360 unsigned ResultReg = createResultReg(RC); local
4609 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); local
4630 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); local
4677 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true, local
4729 unsigned ResultReg = local
4748 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); local
4766 unsigned ResultReg = 0; local
4825 unsigned ResultReg = 0; local
4878 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill); local
4945 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); local
4979 unsigned ResultReg; local
[all...]
H A DAArch64InstrInfo.cpp4410 Register ResultReg = Root.getOperand(0).getReg();
4427 if (Register::isVirtualRegister(ResultReg))
4428 MRI.constrainRegClass(ResultReg, RC);
4438 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4443 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4449 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4561 Register ResultReg = Root.getOperand(0).getReg();
4567 if (Register::isVirtualRegister(ResultReg))
4568 MRI.constrainRegClass(ResultReg, RC);
4577 BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp627 Register ResultReg = local
630 if (!ResultReg)
634 updateValueMap(I, ResultReg);
661 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, local
663 if (!ResultReg)
667 updateValueMap(I, ResultReg);
677 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), local
679 if (!ResultReg)
685 updateValueMap(I, ResultReg);
961 CLI.ResultReg
1502 Register ResultReg = getRegForValue(II->getArgOperand(0)); local
1547 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), local
1582 Register ResultReg; local
1618 Register ResultReg = createResultReg(TyRegClass); local
1771 Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG, local
1824 unsigned ResultReg; local
2098 Register ResultReg = createResultReg(RC); local
2110 Register ResultReg = createResultReg(RC); local
2132 Register ResultReg = createResultReg(RC); local
2157 Register ResultReg = createResultReg(RC); local
2183 Register ResultReg = createResultReg(RC); local
2206 Register ResultReg = createResultReg(RC); local
2230 Register ResultReg = createResultReg(RC); local
2250 Register ResultReg = createResultReg(RC); local
2272 Register ResultReg = createResultReg(RC); local
2288 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp181 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
329 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
330 if (!ResultReg)
333 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
334 return ResultReg;
345 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
347 ResultReg)
350 return ResultReg;
366 unsigned ResultReg = createResultReg(RC); local
370 emitInst(Opc, ResultReg)
638 emitCmp(unsigned ResultReg, const CmpInst *CI) argument
757 emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment) argument
868 unsigned ResultReg; local
905 unsigned ResultReg; local
986 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
1059 unsigned ResultReg = createResultReg(RC); local
1298 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); local
1470 unsigned ResultReg = createResultReg(Allocation[ArgNo].RC); local
1822 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
1947 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
1966 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
2134 unsigned ResultReg = createResultReg(RC); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp88 unsigned &ResultReg, unsigned Alignment = 1);
97 unsigned &ResultReg);
318 MachineMemOperand *MMO, unsigned &ResultReg,
469 ResultReg = createResultReg(RC);
471 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
706 unsigned &ResultReg) {
712 ResultReg = RR;
1322 unsigned ResultReg = 0; local
1323 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg,
1327 updateValueMap(I, ResultReg);
317 X86FastEmitLoad(MVT VT, X86AddressMode &AM, MachineMemOperand *MMO, unsigned &ResultReg, unsigned Alignment) argument
704 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
1427 unsigned ResultReg = 0; local
1834 Register ResultReg = createResultReg(RC); local
1977 unsigned ResultReg = 0; local
2128 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, RHSIsKill, local
2193 unsigned ResultReg; local
2346 Register ResultReg = local
2373 Register ResultReg = createResultReg(RC); local
2446 Register ResultReg = local
2481 Register ResultReg = createResultReg(RC); local
2544 Register ResultReg = fastEmitInst_extractsubreg(MVT::i8, local
2617 unsigned ResultReg = 0; local
2843 Register ResultReg = createResultReg(RC); local
2908 unsigned ResultReg = 0; local
3143 Register ResultReg = createResultReg(RC); local
3266 unsigned ResultReg; local
3547 Register ResultReg = FuncInfo.CreateRegs(CLI.RetTy); local
3673 Register ResultReg = createResultReg(DstClass); local
3704 Register ResultReg = createResultReg(&X86::GR64RegClass); local
3786 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); local
3883 Register ResultReg = createResultReg(RC); local
3916 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
3976 Register ResultReg = createResultReg(RC); local
[all...]
H A DX86InstructionSelector.cpp1029 Register ResultReg = I.getOperand(0).getReg(); local
1031 ResultReg,
1032 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI);
1046 TII.get(SETFOpc[2]), ResultReg)
1073 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp589 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg)); local
591 ResultReg)
593 return ResultReg;
601 unsigned ResultReg = local
606 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
608 return ResultReg;
620 unsigned ResultReg = local
625 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
627 return ResultReg;
714 unsigned ResultReg local
769 unsigned ResultReg; local
927 unsigned ResultReg = createResultReg(RC); local
1043 unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass); local
1104 unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass); local
1195 unsigned ResultReg = createResultReg(RC); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp194 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
303 Register ResultReg = createResultReg(RC); local
311 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
316 TII.get(TargetOpcode::COPY), ResultReg)
319 return ResultReg;
326 unsigned ResultReg = createResultReg(RC); local
336 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
344 TII.get(TargetOpcode::COPY), ResultReg)
347 return ResultReg;
354 unsigned ResultReg local
379 unsigned ResultReg = createResultReg(RC); local
494 unsigned ResultReg = 0; local
663 unsigned ResultReg = createResultReg(RC); local
838 unsigned ResultReg = createResultReg(RC); local
903 ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr, unsigned Alignment, bool isZExt, bool allocReg) argument
1562 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); local
1589 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); local
1655 unsigned ResultReg = createResultReg(RC); local
1766 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); local
1815 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); local
2042 Register ResultReg = createResultReg(DstRC); local
2063 Register ResultReg = createResultReg(DstRC); local
2464 Register ResultReg; local
2698 unsigned ResultReg; local
2756 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); local
2798 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); local
3061 unsigned ResultReg = createResultReg(RC); local
[all...]
H A DARMInstructionSelector.cpp690 auto ResultReg = MIB.getReg(0); local
698 .addDef(ResultReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp166 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
436 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); local
438 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
439 Addr.Base.Reg = ResultReg;
455 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr, argument
462 // If ResultReg is given, it determines the register class of the load.
470 (ResultReg ? MRI.getRegClass(ResultReg) :
526 if (ResultReg == 0)
527 ResultReg
616 Register ResultReg = 0; local
1056 Register ResultReg = 0; local
1181 Register ResultReg = 0; local
1303 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass); local
1521 unsigned ResultReg = 0; local
1926 unsigned ResultReg = createResultReg(RC); local
2115 unsigned ResultReg = createResultReg(RC); local
2187 unsigned ResultReg = createResultReg(RC); local
2275 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp5520 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
5534 MRI.replaceRegWith(OldDstReg, ResultReg);
5537 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5601 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
5604 BuildMI(MBB, MII, DL, get(AMDGPU::V_CNDMASK_B32_e64), ResultReg)
5611 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5613 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5626 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
5635 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
5639 MRI.replaceRegWith(Dest.getReg(), ResultReg);
6015 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
6056 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); local
6080 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); local
6135 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
[all...]
H A DSIRegisterInfo.cpp1329 Register ResultReg = local
1336 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ResultReg)
1340 if (auto MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) {
1341 // Reuse ResultReg in intermediate step.
1342 Register ScaledReg = ResultReg;
1392 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg)
1411 FIOp.ChangeToRegister(ResultReg, false, false, true);
H A DSIISelLowering.cpp3368 unsigned ResultReg,
3388 .addReg(ResultReg)
3360 emitLoadM0FromVGPRLoop( const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, const MachineOperand &IdxReg, unsigned InitReg, unsigned ResultReg, unsigned PhiReg, unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode, bool IsIndirectSrc) argument
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFastISel.h90 Register ResultReg; member in struct:llvm::FastISel::CallLoweringInfo
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1348 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); local
1363 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1364 ResultReg = NextResult;
1368 MIRBuilder.buildTrunc(DstReg, ResultReg);
1370 MIRBuilder.buildIntToPtr(DstReg, ResultReg);
4992 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); local
5005 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
5006 ResultReg = NextResult;
5016 MIRBuilder.buildIntToPtr(DstReg, ResultReg);
H A DMachineIRBuilder.cpp637 for (unsigned ResultReg : ResultRegs)
638 MIB.addDef(ResultReg);

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