Lines Matching refs:ResultReg
194 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
303 Register ResultReg = createResultReg(RC);
311 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
316 TII.get(TargetOpcode::COPY), ResultReg)
319 return ResultReg;
326 unsigned ResultReg = createResultReg(RC);
336 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
344 TII.get(TargetOpcode::COPY), ResultReg)
347 return ResultReg;
354 unsigned ResultReg = createResultReg(RC);
362 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
370 TII.get(TargetOpcode::COPY), ResultReg)
373 return ResultReg;
379 unsigned ResultReg = createResultReg(RC);
384 ResultReg).addImm(Imm));
389 TII.get(TargetOpcode::COPY), ResultReg)
392 return ResultReg;
494 unsigned ResultReg = 0;
496 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
498 if (ResultReg)
499 return ResultReg;
508 ResultReg = createResultReg(TLI.getRegClassFor(VT));
511 TII.get(ARM::t2LDRpci), ResultReg)
515 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
517 TII.get(ARM::LDRcp), ResultReg)
521 return ResultReg;
663 unsigned ResultReg = createResultReg(RC);
664 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
667 TII.get(Opc), ResultReg)
670 return ResultReg;
838 unsigned ResultReg = createResultReg(RC);
841 TII.get(Opc), ResultReg)
844 Addr.Base.Reg = ResultReg;
903 bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
988 ResultReg = createResultReg(RC);
989 assert(ResultReg > 255 && "Expected an allocated virtual register.");
991 TII.get(Opc), ResultReg);
1000 .addReg(ResultReg));
1001 ResultReg = MoveReg;
1035 Register ResultReg;
1036 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1038 updateValueMap(I, ResultReg);
1562 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1564 TII.get(Opc), ResultReg).addReg(FP));
1565 updateValueMap(I, ResultReg);
1589 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1591 TII.get(Opc), ResultReg).addReg(Op));
1595 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1655 unsigned ResultReg = createResultReg(RC);
1660 ResultReg)
1668 ResultReg)
1674 updateValueMap(I, ResultReg);
1766 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1770 TII.get(Opc), ResultReg)
1772 updateValueMap(I, ResultReg);
1815 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1817 TII.get(Opc), ResultReg)
1819 updateValueMap(I, ResultReg);
2042 Register ResultReg = createResultReg(DstRC);
2044 TII.get(ARM::VMOVDRR), ResultReg)
2052 updateValueMap(I, ResultReg);
2063 Register ResultReg = createResultReg(DstRC);
2066 ResultReg).addReg(RVLocs[0].getLocReg());
2070 updateValueMap(I, ResultReg);
2464 Register ResultReg;
2465 RV = ARMEmitLoad(VT, ResultReg, Src);
2467 RV = ARMEmitStore(VT, ResultReg, Dest);
2698 unsigned ResultReg;
2714 ResultReg = createResultReg(RC);
2721 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2731 SrcReg = ResultReg;
2734 return ResultReg;
2756 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2757 if (ResultReg == 0) return false;
2758 updateValueMap(I, ResultReg);
2798 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2799 if(ResultReg == 0) return false;
2802 TII.get(Opc), ResultReg)
2813 updateValueMap(I, ResultReg);
2939 Register ResultReg = MI->getOperand(0).getReg();
2940 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
3061 unsigned ResultReg = createResultReg(RC);
3064 ResultReg).addReg(DstReg, getKillRegState(true));
3065 updateValueMap(&Arg, ResultReg);