Lines Matching refs:ResultReg
368 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
370 ResultReg)
374 return ResultReg;
391 unsigned ResultReg = createResultReg(RC);
393 ResultReg).addReg(ZeroReg, getKillRegState(true));
394 return ResultReg;
427 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
429 TII.get(TargetOpcode::COPY), ResultReg)
432 return ResultReg;
445 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
446 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
449 return ResultReg;
469 unsigned ResultReg;
479 ResultReg = createResultReg(&AArch64::GPR32RegClass);
482 ResultReg = createResultReg(&AArch64::GPR64RegClass);
486 ResultReg)
491 return ResultReg;
500 .addReg(ResultReg, RegState::Kill)
509 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
511 ResultReg)
517 return ResultReg;
1054 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
1056 ResultReg)
1061 Addr.setReg(ResultReg);
1065 unsigned ResultReg = 0;
1069 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1074 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1080 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1084 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1088 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
1091 if (!ResultReg)
1094 Addr.setReg(ResultReg);
1103 unsigned ResultReg;
1106 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset);
1108 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
1110 if (!ResultReg)
1112 Addr.setReg(ResultReg);
1210 unsigned ResultReg = 0;
1214 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,
1217 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,
1221 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags,
1224 if (ResultReg)
1225 return ResultReg;
1265 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1268 if (ResultReg)
1269 return ResultReg;
1290 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1293 if (ResultReg)
1294 return ResultReg;
1335 unsigned ResultReg;
1337 ResultReg = createResultReg(RC);
1339 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1344 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1347 return ResultReg;
1380 unsigned ResultReg;
1382 ResultReg = createResultReg(RC);
1384 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1388 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1392 return ResultReg;
1422 unsigned ResultReg;
1424 ResultReg = createResultReg(RC);
1426 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1435 return ResultReg;
1467 unsigned ResultReg;
1469 ResultReg = createResultReg(RC);
1471 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1476 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1480 return ResultReg;
1565 unsigned ResultReg;
1567 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);
1569 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);
1571 if (ResultReg)
1572 return ResultReg;
1578 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);
1579 return ResultReg;
1627 unsigned ResultReg = 0;
1630 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
1632 if (ResultReg)
1633 return ResultReg;
1652 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1654 if (ResultReg)
1655 return ResultReg;
1668 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1670 if (ResultReg)
1671 return ResultReg;
1681 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1684 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1686 return ResultReg;
1725 unsigned ResultReg =
1730 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1732 return ResultReg;
1768 unsigned ResultReg =
1773 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1775 return ResultReg;
1894 unsigned ResultReg = createResultReg(RC);
1896 TII.get(Opc), ResultReg);
1901 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
1903 ResultReg = ANDReg;
1913 .addReg(ResultReg, getKillRegState(true))
1915 ResultReg = Reg64;
1917 return ResultReg;
1928 unsigned ResultReg;
1933 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
1936 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
1939 if (!ResultReg)
1942 updateValueMap(I, ResultReg);
1954 unsigned ResultReg;
1959 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
1962 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
1965 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
1968 if (!ResultReg)
1971 updateValueMap(I, ResultReg);
2023 unsigned ResultReg =
2025 if (!ResultReg)
2051 ResultReg = std::prev(I)->getOperand(0).getReg();
2054 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg,
2058 updateValueMap(I, ResultReg);
2079 updateValueMap(IntExtVal, ResultReg);
2083 updateValueMap(I, ResultReg);
2575 unsigned ResultReg = 0;
2580 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2582 TII.get(TargetOpcode::COPY), ResultReg)
2586 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);
2590 if (ResultReg) {
2591 updateValueMap(I, ResultReg);
2599 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2627 ResultReg)
2632 updateValueMap(I, ResultReg);
2641 ResultReg)
2646 updateValueMap(I, ResultReg);
2701 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
2703 updateValueMap(SI, ResultReg);
2831 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
2833 updateValueMap(I, ResultReg);
2846 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
2848 ResultReg).addReg(Op);
2849 updateValueMap(I, ResultReg);
2862 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
2864 ResultReg).addReg(Op);
2865 updateValueMap(I, ResultReg);
2895 unsigned ResultReg = createResultReg(
2897 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2899 updateValueMap(I, ResultReg);
2943 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
2945 updateValueMap(I, ResultReg);
3051 unsigned ResultReg = createResultReg(RC);
3053 TII.get(TargetOpcode::COPY), ResultReg)
3055 updateValueMap(&Arg, ResultReg);
3176 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
3178 TII.get(TargetOpcode::COPY), ResultReg)
3182 CLI.ResultReg = ResultReg;
3366 unsigned ResultReg = emitLoad(VT, VT, Src);
3367 if (!ResultReg)
3370 if (!emitStore(VT, ResultReg, Dest))
3511 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
3513 TII.get(AArch64::ADDXri), ResultReg)
3518 updateValueMap(II, ResultReg);
3622 updateValueMap(II, CLI.ResultReg);
3645 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
3646 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
3648 updateValueMap(II, ResultReg);
3676 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
3677 if (!ResultReg)
3680 updateValueMap(II, ResultReg);
3978 unsigned ResultReg;
3999 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
4000 assert(ResultReg && "Unexpected AND instruction emission failure.");
4002 ResultReg = createResultReg(&AArch64::GPR32RegClass);
4004 TII.get(TargetOpcode::COPY), ResultReg)
4008 updateValueMap(I, ResultReg);
4021 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
4022 assert(ResultReg && "Unexpected AND instruction emission failure.");
4030 .addReg(ResultReg)
4032 ResultReg = Reg64;
4034 return ResultReg;
4104 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4107 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
4108 return ResultReg;
4132 unsigned ResultReg = createResultReg(RC);
4134 TII.get(TargetOpcode::COPY), ResultReg)
4136 return ResultReg;
4211 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4214 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
4215 return ResultReg;
4239 unsigned ResultReg = createResultReg(RC);
4241 TII.get(TargetOpcode::COPY), ResultReg)
4243 return ResultReg;
4332 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4335 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
4336 return ResultReg;
4360 unsigned ResultReg = createResultReg(RC);
4362 TII.get(TargetOpcode::COPY), ResultReg)
4364 return ResultReg;
4609 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
4611 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
4615 SrcReg = ResultReg;
4630 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4631 if (!ResultReg)
4634 updateValueMap(I, ResultReg);
4677 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,
4680 updateValueMap(I, ResultReg);
4729 unsigned ResultReg =
4732 if (ResultReg) {
4733 updateValueMap(I, ResultReg);
4748 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
4750 if (!ResultReg)
4753 updateValueMap(I, ResultReg);
4766 unsigned ResultReg = 0;
4799 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4802 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4805 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4808 if (!ResultReg)
4811 updateValueMap(I, ResultReg);
4825 unsigned ResultReg = 0;
4829 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4832 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4835 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4839 if (!ResultReg)
4842 updateValueMap(I, ResultReg);
4878 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);
4880 if (!ResultReg)
4883 updateValueMap(I, ResultReg);
4921 updateValueMap(I, CLI.ResultReg);
4945 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2);
4946 if (!ResultReg)
4948 updateValueMap(I, ResultReg);
4979 unsigned ResultReg;
4981 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true,
4984 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2);
4986 if (!ResultReg)
4989 updateValueMap(I, ResultReg);