Lines Matching refs:ResultReg
627 Register ResultReg =
630 if (!ResultReg)
634 updateValueMap(I, ResultReg);
661 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
663 if (!ResultReg)
667 updateValueMap(I, ResultReg);
677 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
679 if (!ResultReg)
685 updateValueMap(I, ResultReg);
961 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
963 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true));
1056 updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
1264 updateValueMap(CLI.CB, CLI.ResultReg, CLI.NumResultRegs);
1502 Register ResultReg = getRegForValue(II->getArgOperand(0));
1503 if (!ResultReg)
1505 updateValueMap(II, ResultReg);
1547 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1549 if (!ResultReg)
1552 updateValueMap(I, ResultReg);
1582 Register ResultReg;
1588 ResultReg = createResultReg(DstClass);
1590 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1595 if (!ResultReg)
1596 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1598 if (!ResultReg)
1601 updateValueMap(I, ResultReg);
1618 Register ResultReg = createResultReg(TyRegClass);
1620 TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg);
1622 updateValueMap(I, ResultReg);
1771 Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1773 if (ResultReg) {
1774 updateValueMap(I, ResultReg);
1797 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1799 if (!ResultReg)
1802 updateValueMap(I, ResultReg);
1824 unsigned ResultReg;
1827 ResultReg = I->second;
1829 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1840 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1842 updateValueMap(EVI, ResultReg);
2051 Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
2052 if (ResultReg)
2053 return ResultReg;
2098 Register ResultReg = createResultReg(RC);
2101 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
2102 return ResultReg;
2110 Register ResultReg = createResultReg(RC);
2114 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2120 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2123 return ResultReg;
2132 Register ResultReg = createResultReg(RC);
2137 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2145 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2147 return ResultReg;
2157 Register ResultReg = createResultReg(RC);
2163 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2173 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2175 return ResultReg;
2183 Register ResultReg = createResultReg(RC);
2187 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2195 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2197 return ResultReg;
2206 Register ResultReg = createResultReg(RC);
2210 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2220 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2222 return ResultReg;
2230 Register ResultReg = createResultReg(RC);
2233 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2239 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2241 return ResultReg;
2250 Register ResultReg = createResultReg(RC);
2255 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2265 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2267 return ResultReg;
2272 Register ResultReg = createResultReg(RC);
2276 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2281 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2283 return ResultReg;
2288 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2294 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
2295 return ResultReg;