Lines Matching refs:ResultReg
166 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
436 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
438 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
439 Addr.Base.Reg = ResultReg;
455 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
462 // If ResultReg is given, it determines the register class of the load.
470 (ResultReg ? MRI.getRegClass(ResultReg) :
526 if (ResultReg == 0)
527 ResultReg = createResultReg(UseRC);
542 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
578 ResultReg);
616 Register ResultReg = 0;
617 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
620 updateValueMap(I, ResultReg);
1056 Register ResultReg = 0;
1057 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1060 return ResultReg;
1181 Register ResultReg = 0;
1182 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1185 return ResultReg;
1303 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1352 ResultReg)
1355 updateValueMap(I, ResultReg);
1369 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1371 updateValueMap(I, ResultReg);
1521 unsigned ResultReg = 0;
1525 ResultReg = copyRegToRegClass(CpyRC, SourcePhysReg);
1529 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1531 ResultReg).addReg(SourcePhysReg);
1540 ResultReg = copyRegToRegClass(&PPC::GPRCRegClass, SourcePhysReg);
1543 assert(ResultReg && "ResultReg unset!");
1545 CLI.ResultReg = ResultReg;
1926 unsigned ResultReg = createResultReg(RC);
1928 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1931 updateValueMap(I, ResultReg);
2115 unsigned ResultReg = createResultReg(RC);
2120 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2129 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2134 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2137 return ResultReg;
2187 unsigned ResultReg = createResultReg(RC);
2189 ResultReg).addReg(TmpReg3).addImm(Lo);
2190 return ResultReg;
2275 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2277 ResultReg).addFrameIndex(SI->second).addImm(0);
2278 return ResultReg;
2288 // them. Thus ResultReg should be the def reg for the last redundant
2354 Register ResultReg = MI->getOperand(0).getReg();
2356 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,