Lines Matching refs:ResultReg
5520 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5534 MRI.replaceRegWith(OldDstReg, ResultReg);
5537 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5601 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5604 BuildMI(MBB, MII, DL, get(AMDGPU::V_CNDMASK_B32_e64), ResultReg)
5611 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5613 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5626 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5635 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
5639 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5640 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6015 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6026 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
6028 MRI.replaceRegWith(Dest.getReg(), ResultReg);
6032 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6056 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
6067 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
6073 MRI.replaceRegWith(Dest.getReg(), ResultReg);
6074 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6080 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
6086 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
6092 MRI.replaceRegWith(Dest.getReg(), ResultReg);
6093 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6135 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6155 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32), ResultReg)
6165 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32), ResultReg)
6179 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg)
6190 MRI.replaceRegWith(Dest.getReg(), ResultReg);
6191 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);