Searched refs:mmio (Results 1 - 25 of 429) sorted by last modified time

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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gpuvm.c647 bool mmio; local
651 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
653 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
660 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
661 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
667 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
1939 /* If the SG is not NULL, it's one we created for a doorbell or mmio
/linux-master/drivers/soundwire/
H A Damd_manager.c34 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);
35 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US,
41 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);
42 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val,
47 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);
48 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val,
56 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);
57 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US,
65 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);
66 return readl_poll_timeout(amd_manager->mmio
[all...]
/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c137 void __iomem *mmio; member in struct:rockchip_combphy_priv
156 temp = readl(priv->mmio + reg);
158 writel(temp, priv->mmio + reg);
338 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
339 if (IS_ERR(priv->mmio)) {
340 ret = PTR_ERR(priv->mmio);
407 val = readl(priv->mmio + PHYREG15);
409 writel(val, priv->mmio + PHYREG15);
417 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
424 writel(PHYREG18_PLL_LOOP, priv->mmio
[all...]
H A Dphy-rockchip-snps-pcie3.c50 void __iomem *mmio; member in struct:rockchip_p3phy_priv
236 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
237 if (IS_ERR(priv->mmio)) {
238 ret = PTR_ERR(priv->mmio);
/linux-master/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.h148 void __iomem *mmio; member in struct:etnaviv_gpu
168 writel(data, gpu->mmio + reg);
173 return readl(gpu->mmio + reg);
188 writel(data, gpu->mmio + gpu_fix_power_address(gpu, reg));
193 return readl(gpu->mmio + gpu_fix_power_address(gpu, reg));
H A Detnaviv_gpu.c1858 gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1859 if (IS_ERR(gpu->mmio))
1860 return PTR_ERR(gpu->mmio);
/linux-master/tools/testing/selftests/kvm/
H A Dset_memory_region_test.c80 TEST_ASSERT(!run->mmio.is_write, "Unexpected exit mmio write");
81 TEST_ASSERT(run->mmio.len == 8,
82 "Unexpected exit mmio size = %u", run->mmio.len);
84 TEST_ASSERT(run->mmio.phys_addr == MEM_REGION_GPA,
85 "Unexpected exit mmio address = 0x%llx",
86 run->mmio.phys_addr);
87 memcpy(run->mmio.data, &MMIO_VAL, 8);
/linux-master/drivers/tty/serial/
H A Dserial_core.c2047 int mmio; local
2054 mmio = uport->iotype >= UPIO_MEM;
2057 mmio ? "mmio:0x" : "port:",
2058 mmio ? (unsigned long long)uport->mapbase
2195 * * earlycon=<name>,io|mmio|mmio16|mmio32|mmio32be|mmio32native,<addr>,<options>
2196 * * console=<name>,io|mmio|mmio16|mmio32|mmio32be|mmio32native,<addr>,<options>
2209 if (strncmp(p, "mmio,", 5) == 0) {
/linux-master/arch/x86/kvm/
H A Dx86.c7862 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7977 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7978 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7980 vcpu->run->mmio.phys_addr = gpa;
11263 * for each mmio piece in the fragment
11271 * for each mmio piece in the fragment
11288 memcpy(frag->data, run->mmio.data, len);
11295 /* Go forward to the next mmio piece. */
11312 run->mmio.phys_addr = frag->gpa;
11314 memcpy(run->mmio
[all...]
/linux-master/tools/include/uapi/linux/
H A Dkvm.h252 } mmio; member in union:kvm_run::__anon162
596 __u64 addr; /* legal pio/mmio address */
/linux-master/drivers/pci/
H A Dquirks.c293 * key system devices. For devices that need to have mmio decoding always-on,
5791 void __iomem *mmio; local
5803 mmio = pci_iomap(pdev, 0, 0);
5804 if (mmio == NULL) {
5812 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5859 pci_iounmap(pdev, mmio);
/linux-master/drivers/ata/
H A Dahci.c964 void __iomem *mmio = hpriv->mmio; local
971 ctl = readl(mmio + HOST_CTL);
973 writel(ctl, mmio + HOST_CTL);
974 readl(mmio + HOST_CTL); /* flush */
1597 void __iomem *mmio; local
1602 mmio = hpriv->mmio;
1603 irq_stat = readl(mmio + HOST_IRQ_STAT);
1613 writel(irq_stat, mmio
[all...]
H A Dsata_sx4.c419 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; local
428 mmio += PDC_CHIP0_OFS;
466 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
470 ata_port_dbg(ap, "ata pkt buf ofs %u, prd size %u, mmio copied\n",
478 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; local
484 mmio += PDC_CHIP0_OFS;
500 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
504 ata_port_dbg(ap, "ata pkt buf ofs %u, mmio copied\n", i);
529 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
532 mmio
597 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
655 pdc20621_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc, unsigned int doing_hdma, void __iomem *mmio) argument
795 void __iomem *mmio = ap->ioaddr.cmd_addr; local
809 void __iomem *mmio = ap->ioaddr.cmd_addr; local
826 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; local
943 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
993 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1038 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1097 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1160 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1218 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1357 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
[all...]
H A Dsata_mv.c577 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
579 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
581 void __iomem *mmio);
582 int (*reset_hc)(struct ata_host *host, void __iomem *mmio,
584 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
585 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
604 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
606 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
608 void __iomem *mmio);
609 static int mv5_reset_hc(struct ata_host *host, void __iomem *mmio,
881 mv5_phy_base(void __iomem *mmio, unsigned int port) argument
1064 void __iomem *mmio = hpriv->base, *hc_mmio; local
2852 void __iomem *mmio = hpriv->base, *hc_mmio; local
2914 mv_pci_error(struct ata_host *host, void __iomem *mmio) argument
3024 void __iomem *mmio = hpriv->base; local
3038 void __iomem *mmio = hpriv->base; local
3049 mv5_reset_bus(struct ata_host *host, void __iomem *mmio) argument
3065 mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3070 mv5_read_preamp(struct mv_host_priv *hpriv, int idx, void __iomem *mmio) argument
3082 mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3095 mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3124 mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3148 mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int hc) argument
3166 mv5_reset_hc(struct ata_host *host, void __iomem *mmio, unsigned int n_hc) argument
3185 mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) argument
3207 mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3228 mv6_reset_hc(struct ata_host *host, void __iomem *mmio, unsigned int n_hc) argument
3283 mv6_read_preamp(struct mv_host_priv *hpriv, int idx, void __iomem *mmio) argument
3303 mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3308 mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3386 mv_soc_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3392 mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, void __iomem *mmio) argument
3407 mv_soc_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3432 mv_soc_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3445 mv_soc_reset_hc(struct ata_host *host, void __iomem *mmio, unsigned int n_hc) argument
3459 mv_soc_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3465 mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) argument
3470 mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3527 mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port_no) argument
3593 void __iomem *mmio = hpriv->base; local
3695 void __iomem *mmio = hpriv->base; local
3709 void __iomem *mmio = hpriv->base; local
3723 void __iomem *mmio = hpriv->base; local
3890 void __iomem *mmio = hpriv->base; local
[all...]
H A Dahci_st.c38 static void st_ahci_configure_oob(void __iomem *mmio) argument
47 old_val = readl(mmio + ST_AHCI_OOBR);
48 writel(old_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR);
49 writel(new_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR);
50 writel(new_val, mmio + ST_AHCI_OOBR);
167 st_ahci_configure_oob(hpriv->mmio);
220 st_ahci_configure_oob(hpriv->mmio);
/linux-master/arch/x86/kernel/
H A Dsev.c1532 enum insn_mmio_type mmio; local
1538 mmio = insn_decode_mmio(insn, &bytes);
1539 if (mmio == INSN_MMIO_DECODE_FAILED)
1542 if (mmio != INSN_MMIO_WRITE_IMM && mmio != INSN_MMIO_MOVS) {
1551 switch (mmio) {
/linux-master/drivers/gpu/drm/xe/
H A Dxe_ring_ops.c56 dw[i++] = reg.addr + gt->mmio.adj_offset;
H A Dxe_gt_types.h125 * @mmio: mmio info for GT. All GTs within a tile share the same
130 /** @mmio.fw: force wake for GT */
133 * @mmio.adj_limit: adjust MMIO address if address is below this
137 /** @mmio.adj_offset: offect to add to MMIO address when adjusting */
139 } mmio; member in struct:xe_gt
H A Dxe_device_types.h138 * @mmio: MMIO info for a tile.
146 /** @mmio.size: size of tile's MMIO space */
149 /** @mmio.regs: pointer to tile's MMIO space (starting with registers) */
151 } mmio; member in struct:xe_tile
304 /** @mmio: mmio info for device */
306 /** @mmio.size: size of MMIO space for device */
308 /** @mmio.regs: pointer to MMIO space for device */
310 } mmio; member in struct:xe_device
H A Dxe_device.h137 return &gt->mmio.fw;
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgf100.c360 nvkm_memory_unref(&chan->mmio);
451 /* allocate memory for a "mmio list" buffer that's used by the HUB
456 false, &chan->mmio);
464 ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm,
469 /* finally, fill in the mmio list and point the context at it */
470 nvkm_kmap(chan->mmio);
479 nvkm_done(chan->mmio);
2360 gf100_gr_mmio(gr, gr->func->mmio);
2544 .mmio = gf100_gr_pack_mmio,
/linux-master/drivers/video/fbdev/
H A Ds3fb.c40 u8 __iomem *mmio; member in struct:s3fb_info
195 return readb(par->mmio + DDC_MMIO_REG);
203 writeb(val, par->mmio + DDC_MMIO_REG);
1285 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
1286 if (par->mmio)
1292 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
1387 if (par->mmio)
1388 iounmap(par->mmio);
1417 if (par->mmio)
1418 iounmap(par->mmio);
[all...]
/linux-master/drivers/remoteproc/
H A Dqcom_wcnss.c540 void __iomem *mmio; local
576 mmio = devm_platform_ioremap_resource_byname(pdev, "pmu");
577 if (IS_ERR(mmio))
578 return PTR_ERR(mmio);
584 wcnss->pmu_cfg = mmio + data->pmu_offset;
585 wcnss->spare_out = mmio + data->spare_offset;
/linux-master/drivers/bus/mhi/ep/
H A Dmain.c1465 if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->mmio || !mhi_cntrl->irq)
/linux-master/arch/riscv/include/asm/
H A Dio.h23 #include <asm/mmio.h>

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