1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2/* 3 * SoundWire AMD Manager driver 4 * 5 * Copyright 2023-24 Advanced Micro Devices, Inc. 6 */ 7 8#include <linux/completion.h> 9#include <linux/device.h> 10#include <linux/io.h> 11#include <linux/jiffies.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/slab.h> 15#include <linux/soundwire/sdw.h> 16#include <linux/soundwire/sdw_registers.h> 17#include <linux/pm_runtime.h> 18#include <linux/wait.h> 19#include <sound/pcm_params.h> 20#include <sound/soc.h> 21#include "bus.h" 22#include "amd_init.h" 23#include "amd_manager.h" 24 25#define DRV_NAME "amd_sdw_manager" 26 27#define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus) 28 29static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager) 30{ 31 u32 val; 32 int ret; 33 34 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 35 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 36 AMD_SDW_TIMEOUT); 37 if (ret) 38 return ret; 39 40 /* SoundWire manager bus reset */ 41 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 42 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, 43 (val & AMD_SDW_BUS_RESET_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 44 if (ret) 45 return ret; 46 47 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 48 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val, 49 ACP_DELAY_US, AMD_SDW_TIMEOUT); 50 if (ret) { 51 dev_err(amd_manager->dev, "Failed to reset SoundWire manager instance%d\n", 52 amd_manager->instance); 53 return ret; 54 } 55 56 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 57 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 58 AMD_SDW_TIMEOUT); 59} 60 61static int amd_enable_sdw_manager(struct amd_sdw_manager *amd_manager) 62{ 63 u32 val; 64 65 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 66 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 67 AMD_SDW_TIMEOUT); 68} 69 70static int amd_disable_sdw_manager(struct amd_sdw_manager *amd_manager) 71{ 72 u32 val; 73 74 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 75 /* 76 * After invoking manager disable sequence, check whether 77 * manager has executed clock stop sequence. In this case, 78 * manager should ignore checking enable status register. 79 */ 80 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 81 if (val) 82 return 0; 83 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 84 AMD_SDW_TIMEOUT); 85} 86 87static void amd_enable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 88{ 89 u32 val; 90 91 mutex_lock(amd_manager->acp_sdw_lock); 92 val = sdw_manager_reg_mask_array[amd_manager->instance]; 93 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), val, val); 94 mutex_unlock(amd_manager->acp_sdw_lock); 95 96 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 97 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 98 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 99 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 100 writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 101} 102 103static void amd_disable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 104{ 105 u32 irq_mask; 106 107 mutex_lock(amd_manager->acp_sdw_lock); 108 irq_mask = sdw_manager_reg_mask_array[amd_manager->instance]; 109 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), 110 irq_mask, 0); 111 mutex_unlock(amd_manager->acp_sdw_lock); 112 113 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 114 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 115 writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 116} 117 118static int amd_deinit_sdw_manager(struct amd_sdw_manager *amd_manager) 119{ 120 amd_disable_sdw_interrupts(amd_manager); 121 return amd_disable_sdw_manager(amd_manager); 122} 123 124static void amd_sdw_set_frameshape(struct amd_sdw_manager *amd_manager) 125{ 126 u32 frame_size; 127 128 frame_size = (amd_manager->rows_index << 3) | amd_manager->cols_index; 129 writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE); 130} 131 132static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable) 133{ 134 u32 wake_ctrl; 135 136 wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 137 if (enable) 138 wake_ctrl |= AMD_SDW_WAKE_INTR_MASK; 139 else 140 wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK; 141 142 writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 143} 144 145static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg, 146 int cmd_offset) 147{ 148 u32 upper_data; 149 u32 lower_data = 0; 150 u16 addr; 151 u8 upper_addr, lower_addr; 152 u8 data = 0; 153 154 addr = msg->addr + cmd_offset; 155 upper_addr = (addr & 0xFF00) >> 8; 156 lower_addr = addr & 0xFF; 157 158 if (msg->flags == SDW_MSG_FLAG_WRITE) 159 data = msg->buf[cmd_offset]; 160 161 upper_data = FIELD_PREP(AMD_SDW_MCP_CMD_DEV_ADDR, msg->dev_num); 162 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_COMMAND, msg->flags + 2); 163 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_HIGH, upper_addr); 164 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_LOW, lower_addr); 165 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_DATA, data); 166 167 *upper_word = upper_data; 168 *lower_word = lower_data; 169} 170 171static u64 amd_sdw_send_cmd_get_resp(struct amd_sdw_manager *amd_manager, u32 lower_data, 172 u32 upper_data) 173{ 174 u64 resp; 175 u32 lower_resp, upper_resp; 176 u32 sts; 177 int ret; 178 179 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 180 !(sts & AMD_SDW_IMM_CMD_BUSY), ACP_DELAY_US, AMD_SDW_TIMEOUT); 181 if (ret) { 182 dev_err(amd_manager->dev, "SDW%x previous cmd status clear failed\n", 183 amd_manager->instance); 184 return ret; 185 } 186 187 if (sts & AMD_SDW_IMM_RES_VALID) { 188 dev_err(amd_manager->dev, "SDW%x manager is in bad state\n", amd_manager->instance); 189 writel(0x00, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 190 } 191 writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD); 192 writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD); 193 194 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 195 (sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 196 if (ret) { 197 dev_err(amd_manager->dev, "SDW%x cmd response timeout occurred\n", 198 amd_manager->instance); 199 return ret; 200 } 201 upper_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_UPPER_WORD); 202 lower_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_LOWER_QWORD); 203 204 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 205 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 206 !(sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 207 if (ret) { 208 dev_err(amd_manager->dev, "SDW%x cmd status retry failed\n", 209 amd_manager->instance); 210 return ret; 211 } 212 resp = upper_resp; 213 resp = (resp << 32) | lower_resp; 214 return resp; 215} 216 217static enum sdw_command_response 218amd_program_scp_addr(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 219{ 220 struct sdw_msg scp_msg = {0}; 221 u64 response_buf[2] = {0}; 222 u32 upper_data = 0, lower_data = 0; 223 int index; 224 225 scp_msg.dev_num = msg->dev_num; 226 scp_msg.addr = SDW_SCP_ADDRPAGE1; 227 scp_msg.buf = &msg->addr_page1; 228 scp_msg.flags = SDW_MSG_FLAG_WRITE; 229 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 230 response_buf[0] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 231 scp_msg.addr = SDW_SCP_ADDRPAGE2; 232 scp_msg.buf = &msg->addr_page2; 233 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 234 response_buf[1] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 235 236 for (index = 0; index < 2; index++) { 237 if (response_buf[index] == -ETIMEDOUT) { 238 dev_err_ratelimited(amd_manager->dev, 239 "SCP_addrpage command timeout for Slave %d\n", 240 msg->dev_num); 241 return SDW_CMD_TIMEOUT; 242 } else if (!(response_buf[index] & AMD_SDW_MCP_RESP_ACK)) { 243 if (response_buf[index] & AMD_SDW_MCP_RESP_NACK) { 244 dev_err_ratelimited(amd_manager->dev, 245 "SCP_addrpage NACKed for Slave %d\n", 246 msg->dev_num); 247 return SDW_CMD_FAIL; 248 } 249 dev_dbg_ratelimited(amd_manager->dev, "SCP_addrpage ignored for Slave %d\n", 250 msg->dev_num); 251 return SDW_CMD_IGNORED; 252 } 253 } 254 return SDW_CMD_OK; 255} 256 257static int amd_prep_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 258{ 259 int ret; 260 261 if (msg->page) { 262 ret = amd_program_scp_addr(amd_manager, msg); 263 if (ret) { 264 msg->len = 0; 265 return ret; 266 } 267 } 268 switch (msg->flags) { 269 case SDW_MSG_FLAG_READ: 270 case SDW_MSG_FLAG_WRITE: 271 break; 272 default: 273 dev_err(amd_manager->dev, "Invalid msg cmd: %d\n", msg->flags); 274 return -EINVAL; 275 } 276 return 0; 277} 278 279static enum sdw_command_response amd_sdw_fill_msg_resp(struct amd_sdw_manager *amd_manager, 280 struct sdw_msg *msg, u64 response, 281 int offset) 282{ 283 if (response & AMD_SDW_MCP_RESP_ACK) { 284 if (msg->flags == SDW_MSG_FLAG_READ) 285 msg->buf[offset] = FIELD_GET(AMD_SDW_MCP_RESP_RDATA, response); 286 } else { 287 if (response == -ETIMEDOUT) { 288 dev_err_ratelimited(amd_manager->dev, "command timeout for Slave %d\n", 289 msg->dev_num); 290 return SDW_CMD_TIMEOUT; 291 } else if (response & AMD_SDW_MCP_RESP_NACK) { 292 dev_err_ratelimited(amd_manager->dev, 293 "command response NACK received for Slave %d\n", 294 msg->dev_num); 295 return SDW_CMD_FAIL; 296 } 297 dev_err_ratelimited(amd_manager->dev, "command is ignored for Slave %d\n", 298 msg->dev_num); 299 return SDW_CMD_IGNORED; 300 } 301 return SDW_CMD_OK; 302} 303 304static unsigned int _amd_sdw_xfer_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg, 305 int cmd_offset) 306{ 307 u64 response; 308 u32 upper_data = 0, lower_data = 0; 309 310 amd_sdw_ctl_word_prep(&lower_data, &upper_data, msg, cmd_offset); 311 response = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 312 return amd_sdw_fill_msg_resp(amd_manager, msg, response, cmd_offset); 313} 314 315static enum sdw_command_response amd_sdw_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg) 316{ 317 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 318 int ret, i; 319 320 ret = amd_prep_msg(amd_manager, msg); 321 if (ret) 322 return SDW_CMD_FAIL_OTHER; 323 for (i = 0; i < msg->len; i++) { 324 ret = _amd_sdw_xfer_msg(amd_manager, msg, i); 325 if (ret) 326 return ret; 327 } 328 return SDW_CMD_OK; 329} 330 331static void amd_sdw_fill_slave_status(struct amd_sdw_manager *amd_manager, u16 index, u32 status) 332{ 333 switch (status) { 334 case SDW_SLAVE_ATTACHED: 335 case SDW_SLAVE_UNATTACHED: 336 case SDW_SLAVE_ALERT: 337 amd_manager->status[index] = status; 338 break; 339 default: 340 amd_manager->status[index] = SDW_SLAVE_RESERVED; 341 break; 342 } 343} 344 345static void amd_sdw_process_ping_status(u64 response, struct amd_sdw_manager *amd_manager) 346{ 347 u64 slave_stat; 348 u32 val; 349 u16 dev_index; 350 351 /* slave status response */ 352 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 353 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 354 dev_dbg(amd_manager->dev, "slave_stat:0x%llx\n", slave_stat); 355 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 356 val = (slave_stat >> (dev_index * 2)) & AMD_SDW_MCP_SLAVE_STATUS_MASK; 357 dev_dbg(amd_manager->dev, "val:0x%x\n", val); 358 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 359 } 360} 361 362static void amd_sdw_read_and_process_ping_status(struct amd_sdw_manager *amd_manager) 363{ 364 u64 response; 365 366 mutex_lock(&amd_manager->bus.msg_lock); 367 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 368 mutex_unlock(&amd_manager->bus.msg_lock); 369 amd_sdw_process_ping_status(response, amd_manager); 370} 371 372static u32 amd_sdw_read_ping_status(struct sdw_bus *bus) 373{ 374 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 375 u64 response; 376 u32 slave_stat; 377 378 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 379 /* slave status from ping response */ 380 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 381 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 382 dev_dbg(amd_manager->dev, "slave_stat:0x%x\n", slave_stat); 383 return slave_stat; 384} 385 386static int amd_sdw_compute_params(struct sdw_bus *bus) 387{ 388 struct sdw_transport_data t_data = {0}; 389 struct sdw_master_runtime *m_rt; 390 struct sdw_port_runtime *p_rt; 391 struct sdw_bus_params *b_params = &bus->params; 392 int port_bo, hstart, hstop, sample_int; 393 unsigned int rate, bps; 394 395 port_bo = 0; 396 hstart = 1; 397 hstop = bus->params.col - 1; 398 t_data.hstop = hstop; 399 t_data.hstart = hstart; 400 401 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 402 rate = m_rt->stream->params.rate; 403 bps = m_rt->stream->params.bps; 404 sample_int = (bus->params.curr_dr_freq / rate); 405 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 406 port_bo = (p_rt->num * 64) + 1; 407 dev_dbg(bus->dev, "p_rt->num=%d hstart=%d hstop=%d port_bo=%d\n", 408 p_rt->num, hstart, hstop, port_bo); 409 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, 410 false, SDW_BLK_GRP_CNT_1, sample_int, 411 port_bo, port_bo >> 8, hstart, hstop, 412 SDW_BLK_PKG_PER_PORT, 0x0); 413 414 sdw_fill_port_params(&p_rt->port_params, 415 p_rt->num, bps, 416 SDW_PORT_FLOW_MODE_ISOCH, 417 b_params->m_data_mode); 418 t_data.hstart = hstart; 419 t_data.hstop = hstop; 420 t_data.block_offset = port_bo; 421 t_data.sub_block_offset = 0; 422 } 423 sdw_compute_slave_ports(m_rt, &t_data); 424 } 425 return 0; 426} 427 428static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params, 429 unsigned int bank) 430{ 431 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 432 u32 frame_fmt_reg, dpn_frame_fmt; 433 434 dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num); 435 switch (amd_manager->instance) { 436 case ACP_SDW0: 437 frame_fmt_reg = sdw0_manager_dp_reg[p_params->num].frame_fmt_reg; 438 break; 439 case ACP_SDW1: 440 frame_fmt_reg = sdw1_manager_dp_reg[p_params->num].frame_fmt_reg; 441 break; 442 default: 443 return -EINVAL; 444 } 445 446 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 447 u32p_replace_bits(&dpn_frame_fmt, p_params->flow_mode, AMD_DPN_FRAME_FMT_PFM); 448 u32p_replace_bits(&dpn_frame_fmt, p_params->data_mode, AMD_DPN_FRAME_FMT_PDM); 449 u32p_replace_bits(&dpn_frame_fmt, p_params->bps - 1, AMD_DPN_FRAME_FMT_WORD_LEN); 450 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 451 return 0; 452} 453 454static int amd_sdw_transport_params(struct sdw_bus *bus, 455 struct sdw_transport_params *params, 456 enum sdw_reg_bank bank) 457{ 458 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 459 u32 dpn_frame_fmt; 460 u32 dpn_sampleinterval; 461 u32 dpn_hctrl; 462 u32 dpn_offsetctrl; 463 u32 dpn_lanectrl; 464 u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg; 465 u32 offset_reg, lane_ctrl_ch_en_reg; 466 467 switch (amd_manager->instance) { 468 case ACP_SDW0: 469 frame_fmt_reg = sdw0_manager_dp_reg[params->port_num].frame_fmt_reg; 470 sample_int_reg = sdw0_manager_dp_reg[params->port_num].sample_int_reg; 471 hctrl_dp0_reg = sdw0_manager_dp_reg[params->port_num].hctrl_dp0_reg; 472 offset_reg = sdw0_manager_dp_reg[params->port_num].offset_reg; 473 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 474 break; 475 case ACP_SDW1: 476 frame_fmt_reg = sdw1_manager_dp_reg[params->port_num].frame_fmt_reg; 477 sample_int_reg = sdw1_manager_dp_reg[params->port_num].sample_int_reg; 478 hctrl_dp0_reg = sdw1_manager_dp_reg[params->port_num].hctrl_dp0_reg; 479 offset_reg = sdw1_manager_dp_reg[params->port_num].offset_reg; 480 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 481 break; 482 default: 483 return -EINVAL; 484 } 485 writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER); 486 487 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 488 u32p_replace_bits(&dpn_frame_fmt, params->blk_pkg_mode, AMD_DPN_FRAME_FMT_BLK_PKG_MODE); 489 u32p_replace_bits(&dpn_frame_fmt, params->blk_grp_ctrl, AMD_DPN_FRAME_FMT_BLK_GRP_CTRL); 490 u32p_replace_bits(&dpn_frame_fmt, SDW_STREAM_PCM, AMD_DPN_FRAME_FMT_PCM_OR_PDM); 491 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 492 493 dpn_sampleinterval = params->sample_interval - 1; 494 writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg); 495 496 dpn_hctrl = FIELD_PREP(AMD_DPN_HCTRL_HSTOP, params->hstop); 497 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart); 498 writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg); 499 500 dpn_offsetctrl = FIELD_PREP(AMD_DPN_OFFSET_CTRL_1, params->offset1); 501 dpn_offsetctrl |= FIELD_PREP(AMD_DPN_OFFSET_CTRL_2, params->offset2); 502 writel(dpn_offsetctrl, amd_manager->mmio + offset_reg); 503 504 /* 505 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 506 * parameters. 507 */ 508 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 509 u32p_replace_bits(&dpn_lanectrl, params->lane_ctrl, AMD_DPN_CH_EN_LCTRL); 510 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg); 511 return 0; 512} 513 514static int amd_sdw_port_enable(struct sdw_bus *bus, 515 struct sdw_enable_ch *enable_ch, 516 unsigned int bank) 517{ 518 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 519 u32 dpn_ch_enable; 520 u32 lane_ctrl_ch_en_reg; 521 522 switch (amd_manager->instance) { 523 case ACP_SDW0: 524 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 525 break; 526 case ACP_SDW1: 527 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 528 break; 529 default: 530 return -EINVAL; 531 } 532 533 /* 534 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 535 * parameters. 536 */ 537 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 538 u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK); 539 if (enable_ch->enable) 540 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg); 541 else 542 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg); 543 return 0; 544} 545 546static int sdw_master_read_amd_prop(struct sdw_bus *bus) 547{ 548 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 549 struct fwnode_handle *link; 550 struct sdw_master_prop *prop; 551 u32 quirk_mask = 0; 552 u32 wake_en_mask = 0; 553 u32 power_mode_mask = 0; 554 char name[32]; 555 556 prop = &bus->prop; 557 /* Find manager handle */ 558 snprintf(name, sizeof(name), "mipi-sdw-link-%d-subproperties", bus->link_id); 559 link = device_get_named_child_node(bus->dev, name); 560 if (!link) { 561 dev_err(bus->dev, "Manager node %s not found\n", name); 562 return -EIO; 563 } 564 fwnode_property_read_u32(link, "amd-sdw-enable", &quirk_mask); 565 if (!(quirk_mask & AMD_SDW_QUIRK_MASK_BUS_ENABLE)) 566 prop->hw_disabled = true; 567 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH | 568 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY; 569 570 fwnode_property_read_u32(link, "amd-sdw-wakeup-enable", &wake_en_mask); 571 amd_manager->wake_en_mask = wake_en_mask; 572 fwnode_property_read_u32(link, "amd-sdw-power-mode", &power_mode_mask); 573 amd_manager->power_mode_mask = power_mode_mask; 574 575 fwnode_handle_put(link); 576 577 return 0; 578} 579 580static int amd_prop_read(struct sdw_bus *bus) 581{ 582 sdw_master_read_prop(bus); 583 sdw_master_read_amd_prop(bus); 584 return 0; 585} 586 587static const struct sdw_master_port_ops amd_sdw_port_ops = { 588 .dpn_set_port_params = amd_sdw_port_params, 589 .dpn_set_port_transport_params = amd_sdw_transport_params, 590 .dpn_port_enable_ch = amd_sdw_port_enable, 591}; 592 593static const struct sdw_master_ops amd_sdw_ops = { 594 .read_prop = amd_prop_read, 595 .xfer_msg = amd_sdw_xfer_msg, 596 .read_ping_status = amd_sdw_read_ping_status, 597}; 598 599static int amd_sdw_hw_params(struct snd_pcm_substream *substream, 600 struct snd_pcm_hw_params *params, 601 struct snd_soc_dai *dai) 602{ 603 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 604 struct sdw_amd_dai_runtime *dai_runtime; 605 struct sdw_stream_config sconfig; 606 struct sdw_port_config *pconfig; 607 int ch, dir; 608 int ret; 609 610 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 611 if (!dai_runtime) 612 return -EIO; 613 614 ch = params_channels(params); 615 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 616 dir = SDW_DATA_DIR_RX; 617 else 618 dir = SDW_DATA_DIR_TX; 619 dev_dbg(amd_manager->dev, "dir:%d dai->id:0x%x\n", dir, dai->id); 620 621 sconfig.direction = dir; 622 sconfig.ch_count = ch; 623 sconfig.frame_rate = params_rate(params); 624 sconfig.type = dai_runtime->stream_type; 625 626 sconfig.bps = snd_pcm_format_width(params_format(params)); 627 628 /* Port configuration */ 629 pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL); 630 if (!pconfig) { 631 ret = -ENOMEM; 632 goto error; 633 } 634 635 pconfig->num = dai->id; 636 pconfig->ch_mask = (1 << ch) - 1; 637 ret = sdw_stream_add_master(&amd_manager->bus, &sconfig, 638 pconfig, 1, dai_runtime->stream); 639 if (ret) 640 dev_err(amd_manager->dev, "add manager to stream failed:%d\n", ret); 641 642 kfree(pconfig); 643error: 644 return ret; 645} 646 647static int amd_sdw_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 648{ 649 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 650 struct sdw_amd_dai_runtime *dai_runtime; 651 int ret; 652 653 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 654 if (!dai_runtime) 655 return -EIO; 656 657 ret = sdw_stream_remove_master(&amd_manager->bus, dai_runtime->stream); 658 if (ret < 0) 659 dev_err(dai->dev, "remove manager from stream %s failed: %d\n", 660 dai_runtime->stream->name, ret); 661 return ret; 662} 663 664static int amd_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 665{ 666 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 667 struct sdw_amd_dai_runtime *dai_runtime; 668 669 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 670 if (stream) { 671 /* first paranoia check */ 672 if (dai_runtime) { 673 dev_err(dai->dev, "dai_runtime already allocated for dai %s\n", dai->name); 674 return -EINVAL; 675 } 676 677 /* allocate and set dai_runtime info */ 678 dai_runtime = kzalloc(sizeof(*dai_runtime), GFP_KERNEL); 679 if (!dai_runtime) 680 return -ENOMEM; 681 682 dai_runtime->stream_type = SDW_STREAM_PCM; 683 dai_runtime->bus = &amd_manager->bus; 684 dai_runtime->stream = stream; 685 amd_manager->dai_runtime_array[dai->id] = dai_runtime; 686 } else { 687 /* second paranoia check */ 688 if (!dai_runtime) { 689 dev_err(dai->dev, "dai_runtime not allocated for dai %s\n", dai->name); 690 return -EINVAL; 691 } 692 693 /* for NULL stream we release allocated dai_runtime */ 694 kfree(dai_runtime); 695 amd_manager->dai_runtime_array[dai->id] = NULL; 696 } 697 return 0; 698} 699 700static int amd_pcm_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 701{ 702 return amd_set_sdw_stream(dai, stream, direction); 703} 704 705static void *amd_get_sdw_stream(struct snd_soc_dai *dai, int direction) 706{ 707 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 708 struct sdw_amd_dai_runtime *dai_runtime; 709 710 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 711 if (!dai_runtime) 712 return ERR_PTR(-EINVAL); 713 714 return dai_runtime->stream; 715} 716 717static const struct snd_soc_dai_ops amd_sdw_dai_ops = { 718 .hw_params = amd_sdw_hw_params, 719 .hw_free = amd_sdw_hw_free, 720 .set_stream = amd_pcm_set_sdw_stream, 721 .get_stream = amd_get_sdw_stream, 722}; 723 724static const struct snd_soc_component_driver amd_sdw_dai_component = { 725 .name = "soundwire", 726}; 727 728static int amd_sdw_register_dais(struct amd_sdw_manager *amd_manager) 729{ 730 struct sdw_amd_dai_runtime **dai_runtime_array; 731 struct snd_soc_dai_driver *dais; 732 struct snd_soc_pcm_stream *stream; 733 struct device *dev; 734 int i, num_dais; 735 736 dev = amd_manager->dev; 737 num_dais = amd_manager->num_dout_ports + amd_manager->num_din_ports; 738 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 739 if (!dais) 740 return -ENOMEM; 741 742 dai_runtime_array = devm_kcalloc(dev, num_dais, 743 sizeof(struct sdw_amd_dai_runtime *), 744 GFP_KERNEL); 745 if (!dai_runtime_array) 746 return -ENOMEM; 747 amd_manager->dai_runtime_array = dai_runtime_array; 748 for (i = 0; i < num_dais; i++) { 749 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW%d Pin%d", amd_manager->instance, 750 i); 751 if (!dais[i].name) 752 return -ENOMEM; 753 if (i < amd_manager->num_dout_ports) 754 stream = &dais[i].playback; 755 else 756 stream = &dais[i].capture; 757 758 stream->channels_min = 2; 759 stream->channels_max = 2; 760 stream->rates = SNDRV_PCM_RATE_48000; 761 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 762 763 dais[i].ops = &amd_sdw_dai_ops; 764 dais[i].id = i; 765 } 766 767 return devm_snd_soc_register_component(dev, &amd_sdw_dai_component, 768 dais, num_dais); 769} 770 771static void amd_sdw_update_slave_status_work(struct work_struct *work) 772{ 773 struct amd_sdw_manager *amd_manager = 774 container_of(work, struct amd_sdw_manager, amd_sdw_work); 775 int retry_count = 0; 776 777 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 778 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 779 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 780 } 781 782update_status: 783 sdw_handle_slave_status(&amd_manager->bus, amd_manager->status); 784 /* 785 * During the peripheral enumeration sequence, the SoundWire manager interrupts 786 * are masked. Once the device number programming is done for all peripherals, 787 * interrupts will be unmasked. Read the peripheral device status from ping command 788 * and process the response. This sequence will ensure all peripheral devices enumerated 789 * and initialized properly. 790 */ 791 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 792 if (retry_count++ < SDW_MAX_DEVICES) { 793 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 794 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 795 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 796 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 797 amd_sdw_read_and_process_ping_status(amd_manager); 798 goto update_status; 799 } else { 800 dev_err_ratelimited(amd_manager->dev, 801 "Device0 detected after %d iterations\n", 802 retry_count); 803 } 804 } 805} 806 807static void amd_sdw_update_slave_status(u32 status_change_0to7, u32 status_change_8to11, 808 struct amd_sdw_manager *amd_manager) 809{ 810 u64 slave_stat; 811 u32 val; 812 int dev_index; 813 814 if (status_change_0to7 == AMD_SDW_SLAVE_0_ATTACHED) 815 memset(amd_manager->status, 0, sizeof(amd_manager->status)); 816 slave_stat = status_change_0to7; 817 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STATUS_8TO_11, status_change_8to11) << 32; 818 dev_dbg(amd_manager->dev, "status_change_0to7:0x%x status_change_8to11:0x%x\n", 819 status_change_0to7, status_change_8to11); 820 if (slave_stat) { 821 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 822 if (slave_stat & AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(dev_index)) { 823 val = (slave_stat >> AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(dev_index)) & 824 AMD_SDW_MCP_SLAVE_STATUS_MASK; 825 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 826 } 827 } 828 } 829} 830 831static void amd_sdw_process_wake_event(struct amd_sdw_manager *amd_manager) 832{ 833 pm_request_resume(amd_manager->dev); 834 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 835 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 836} 837 838static void amd_sdw_irq_thread(struct work_struct *work) 839{ 840 struct amd_sdw_manager *amd_manager = 841 container_of(work, struct amd_sdw_manager, amd_sdw_irq_thread); 842 u32 status_change_8to11; 843 u32 status_change_0to7; 844 845 status_change_8to11 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 846 status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 847 dev_dbg(amd_manager->dev, "[SDW%d] SDW INT: 0to7=0x%x, 8to11=0x%x\n", 848 amd_manager->instance, status_change_0to7, status_change_8to11); 849 if (status_change_8to11 & AMD_SDW_WAKE_STAT_MASK) 850 return amd_sdw_process_wake_event(amd_manager); 851 852 if (status_change_8to11 & AMD_SDW_PREQ_INTR_STAT) { 853 amd_sdw_read_and_process_ping_status(amd_manager); 854 } else { 855 /* Check for the updated status on peripheral device */ 856 amd_sdw_update_slave_status(status_change_0to7, status_change_8to11, amd_manager); 857 } 858 if (status_change_8to11 || status_change_0to7) 859 schedule_work(&amd_manager->amd_sdw_work); 860 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 861 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 862} 863 864int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager) 865{ 866 struct sdw_master_prop *prop; 867 int ret; 868 869 prop = &amd_manager->bus.prop; 870 if (!prop->hw_disabled) { 871 ret = amd_init_sdw_manager(amd_manager); 872 if (ret) 873 return ret; 874 amd_enable_sdw_interrupts(amd_manager); 875 ret = amd_enable_sdw_manager(amd_manager); 876 if (ret) 877 return ret; 878 amd_sdw_set_frameshape(amd_manager); 879 } 880 /* Enable runtime PM */ 881 pm_runtime_set_autosuspend_delay(amd_manager->dev, AMD_SDW_MASTER_SUSPEND_DELAY_MS); 882 pm_runtime_use_autosuspend(amd_manager->dev); 883 pm_runtime_mark_last_busy(amd_manager->dev); 884 pm_runtime_set_active(amd_manager->dev); 885 pm_runtime_enable(amd_manager->dev); 886 return 0; 887} 888 889static int amd_sdw_manager_probe(struct platform_device *pdev) 890{ 891 const struct acp_sdw_pdata *pdata = pdev->dev.platform_data; 892 struct resource *res; 893 struct device *dev = &pdev->dev; 894 struct sdw_master_prop *prop; 895 struct sdw_bus_params *params; 896 struct amd_sdw_manager *amd_manager; 897 int ret; 898 899 amd_manager = devm_kzalloc(dev, sizeof(struct amd_sdw_manager), GFP_KERNEL); 900 if (!amd_manager) 901 return -ENOMEM; 902 903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 904 if (!res) 905 return -ENOMEM; 906 907 amd_manager->acp_mmio = devm_ioremap(dev, res->start, resource_size(res)); 908 if (!amd_manager->acp_mmio) { 909 dev_err(dev, "mmio not found\n"); 910 return -ENOMEM; 911 } 912 amd_manager->instance = pdata->instance; 913 amd_manager->mmio = amd_manager->acp_mmio + 914 (amd_manager->instance * SDW_MANAGER_REG_OFFSET); 915 amd_manager->acp_sdw_lock = pdata->acp_sdw_lock; 916 amd_manager->cols_index = sdw_find_col_index(AMD_SDW_DEFAULT_COLUMNS); 917 amd_manager->rows_index = sdw_find_row_index(AMD_SDW_DEFAULT_ROWS); 918 amd_manager->dev = dev; 919 amd_manager->bus.ops = &amd_sdw_ops; 920 amd_manager->bus.port_ops = &amd_sdw_port_ops; 921 amd_manager->bus.compute_params = &amd_sdw_compute_params; 922 amd_manager->bus.clk_stop_timeout = 200; 923 amd_manager->bus.link_id = amd_manager->instance; 924 925 /* 926 * Due to BIOS compatibility, the two links are exposed within 927 * the scope of a single controller. If this changes, the 928 * controller_id will have to be updated with drv_data 929 * information. 930 */ 931 amd_manager->bus.controller_id = 0; 932 933 switch (amd_manager->instance) { 934 case ACP_SDW0: 935 amd_manager->num_dout_ports = AMD_SDW0_MAX_TX_PORTS; 936 amd_manager->num_din_ports = AMD_SDW0_MAX_RX_PORTS; 937 break; 938 case ACP_SDW1: 939 amd_manager->num_dout_ports = AMD_SDW1_MAX_TX_PORTS; 940 amd_manager->num_din_ports = AMD_SDW1_MAX_RX_PORTS; 941 break; 942 default: 943 return -EINVAL; 944 } 945 946 params = &amd_manager->bus.params; 947 948 params->col = AMD_SDW_DEFAULT_COLUMNS; 949 params->row = AMD_SDW_DEFAULT_ROWS; 950 prop = &amd_manager->bus.prop; 951 prop->clk_freq = &amd_sdw_freq_tbl[0]; 952 prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ; 953 prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ; 954 955 ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode); 956 if (ret) { 957 dev_err(dev, "Failed to register SoundWire manager(%d)\n", ret); 958 return ret; 959 } 960 ret = amd_sdw_register_dais(amd_manager); 961 if (ret) { 962 dev_err(dev, "CPU DAI registration failed\n"); 963 sdw_bus_master_delete(&amd_manager->bus); 964 return ret; 965 } 966 dev_set_drvdata(dev, amd_manager); 967 INIT_WORK(&amd_manager->amd_sdw_irq_thread, amd_sdw_irq_thread); 968 INIT_WORK(&amd_manager->amd_sdw_work, amd_sdw_update_slave_status_work); 969 return 0; 970} 971 972static void amd_sdw_manager_remove(struct platform_device *pdev) 973{ 974 struct amd_sdw_manager *amd_manager = dev_get_drvdata(&pdev->dev); 975 int ret; 976 977 pm_runtime_disable(&pdev->dev); 978 amd_disable_sdw_interrupts(amd_manager); 979 sdw_bus_master_delete(&amd_manager->bus); 980 ret = amd_disable_sdw_manager(amd_manager); 981 if (ret) 982 dev_err(&pdev->dev, "Failed to disable device (%pe)\n", ERR_PTR(ret)); 983} 984 985static int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager) 986{ 987 u32 val; 988 int ret; 989 990 ret = sdw_bus_prep_clk_stop(&amd_manager->bus); 991 if (ret < 0 && ret != -ENODATA) { 992 dev_err(amd_manager->dev, "prepare clock stop failed %d", ret); 993 return 0; 994 } 995 ret = sdw_bus_clk_stop(&amd_manager->bus); 996 if (ret < 0 && ret != -ENODATA) { 997 dev_err(amd_manager->dev, "bus clock stop failed %d", ret); 998 return 0; 999 } 1000 1001 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1002 (val & AMD_SDW_CLK_STOP_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 1003 if (ret) { 1004 dev_err(amd_manager->dev, "SDW%x clock stop failed\n", amd_manager->instance); 1005 return 0; 1006 } 1007 1008 amd_manager->clk_stopped = true; 1009 if (amd_manager->wake_en_mask) 1010 writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 1011 1012 dev_dbg(amd_manager->dev, "SDW%x clock stop successful\n", amd_manager->instance); 1013 return 0; 1014} 1015 1016static int amd_sdw_clock_stop_exit(struct amd_sdw_manager *amd_manager) 1017{ 1018 int ret; 1019 u32 val; 1020 1021 if (amd_manager->clk_stopped) { 1022 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1023 val |= AMD_SDW_CLK_RESUME_REQ; 1024 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1025 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1026 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1027 AMD_SDW_TIMEOUT); 1028 if (val & AMD_SDW_CLK_RESUME_DONE) { 1029 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1030 ret = sdw_bus_exit_clk_stop(&amd_manager->bus); 1031 if (ret < 0) 1032 dev_err(amd_manager->dev, "bus failed to exit clock stop %d\n", 1033 ret); 1034 amd_manager->clk_stopped = false; 1035 } 1036 } 1037 if (amd_manager->clk_stopped) { 1038 dev_err(amd_manager->dev, "SDW%x clock stop exit failed\n", amd_manager->instance); 1039 return 0; 1040 } 1041 dev_dbg(amd_manager->dev, "SDW%x clock stop exit successful\n", amd_manager->instance); 1042 return 0; 1043} 1044 1045static int amd_resume_child_device(struct device *dev, void *data) 1046{ 1047 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1048 int ret; 1049 1050 if (!slave->probed) { 1051 dev_dbg(dev, "skipping device, no probed driver\n"); 1052 return 0; 1053 } 1054 if (!slave->dev_num_sticky) { 1055 dev_dbg(dev, "skipping device, never detected on bus\n"); 1056 return 0; 1057 } 1058 ret = pm_request_resume(dev); 1059 if (ret < 0) { 1060 dev_err(dev, "pm_request_resume failed: %d\n", ret); 1061 return ret; 1062 } 1063 return 0; 1064} 1065 1066static int __maybe_unused amd_pm_prepare(struct device *dev) 1067{ 1068 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1069 struct sdw_bus *bus = &amd_manager->bus; 1070 int ret; 1071 1072 if (bus->prop.hw_disabled) { 1073 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1074 bus->link_id); 1075 return 0; 1076 } 1077 /* 1078 * When multiple peripheral devices connected over the same link, if SoundWire manager 1079 * device is not in runtime suspend state, observed that device alerts are missing 1080 * without pm_prepare on AMD platforms in clockstop mode0. 1081 */ 1082 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1083 ret = pm_request_resume(dev); 1084 if (ret < 0) { 1085 dev_err(bus->dev, "pm_request_resume failed: %d\n", ret); 1086 return 0; 1087 } 1088 } 1089 /* To force peripheral devices to system level suspend state, resume the devices 1090 * from runtime suspend state first. Without that unable to dispatch the alert 1091 * status to peripheral driver during system level resume as they are in runtime 1092 * suspend state. 1093 */ 1094 ret = device_for_each_child(bus->dev, NULL, amd_resume_child_device); 1095 if (ret < 0) 1096 dev_err(dev, "amd_resume_child_device failed: %d\n", ret); 1097 return 0; 1098} 1099 1100static int __maybe_unused amd_suspend(struct device *dev) 1101{ 1102 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1103 struct sdw_bus *bus = &amd_manager->bus; 1104 int ret; 1105 1106 if (bus->prop.hw_disabled) { 1107 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1108 bus->link_id); 1109 return 0; 1110 } 1111 1112 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1113 amd_sdw_wake_enable(amd_manager, false); 1114 return amd_sdw_clock_stop(amd_manager); 1115 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1116 /* 1117 * As per hardware programming sequence on AMD platforms, 1118 * clock stop should be invoked first before powering-off 1119 */ 1120 ret = amd_sdw_clock_stop(amd_manager); 1121 if (ret) 1122 return ret; 1123 return amd_deinit_sdw_manager(amd_manager); 1124 } 1125 return 0; 1126} 1127 1128static int __maybe_unused amd_suspend_runtime(struct device *dev) 1129{ 1130 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1131 struct sdw_bus *bus = &amd_manager->bus; 1132 int ret; 1133 1134 if (bus->prop.hw_disabled) { 1135 dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n", 1136 bus->link_id); 1137 return 0; 1138 } 1139 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1140 amd_sdw_wake_enable(amd_manager, true); 1141 return amd_sdw_clock_stop(amd_manager); 1142 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1143 ret = amd_sdw_clock_stop(amd_manager); 1144 if (ret) 1145 return ret; 1146 return amd_deinit_sdw_manager(amd_manager); 1147 } 1148 return 0; 1149} 1150 1151static int __maybe_unused amd_resume_runtime(struct device *dev) 1152{ 1153 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1154 struct sdw_bus *bus = &amd_manager->bus; 1155 int ret; 1156 u32 val; 1157 1158 if (bus->prop.hw_disabled) { 1159 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1160 bus->link_id); 1161 return 0; 1162 } 1163 1164 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1165 return amd_sdw_clock_stop_exit(amd_manager); 1166 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1167 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1168 if (val) { 1169 val |= AMD_SDW_CLK_RESUME_REQ; 1170 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1171 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1172 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1173 AMD_SDW_TIMEOUT); 1174 if (val & AMD_SDW_CLK_RESUME_DONE) { 1175 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1176 amd_manager->clk_stopped = false; 1177 } 1178 } 1179 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1180 amd_init_sdw_manager(amd_manager); 1181 amd_enable_sdw_interrupts(amd_manager); 1182 ret = amd_enable_sdw_manager(amd_manager); 1183 if (ret) 1184 return ret; 1185 amd_sdw_set_frameshape(amd_manager); 1186 } 1187 return 0; 1188} 1189 1190static const struct dev_pm_ops amd_pm = { 1191 .prepare = amd_pm_prepare, 1192 SET_SYSTEM_SLEEP_PM_OPS(amd_suspend, amd_resume_runtime) 1193 SET_RUNTIME_PM_OPS(amd_suspend_runtime, amd_resume_runtime, NULL) 1194}; 1195 1196static struct platform_driver amd_sdw_driver = { 1197 .probe = &amd_sdw_manager_probe, 1198 .remove_new = &amd_sdw_manager_remove, 1199 .driver = { 1200 .name = "amd_sdw_manager", 1201 .pm = &amd_pm, 1202 } 1203}; 1204module_platform_driver(amd_sdw_driver); 1205 1206MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1207MODULE_DESCRIPTION("AMD SoundWire driver"); 1208MODULE_LICENSE("Dual BSD/GPL"); 1209MODULE_ALIAS("platform:" DRV_NAME); 1210