1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright �� 2022-2023 Intel Corporation 4 */ 5 6#ifndef _XE_GT_TYPES_H_ 7#define _XE_GT_TYPES_H_ 8 9#include "xe_force_wake_types.h" 10#include "xe_gt_idle_types.h" 11#include "xe_hw_engine_types.h" 12#include "xe_hw_fence_types.h" 13#include "xe_reg_sr_types.h" 14#include "xe_sa_types.h" 15#include "xe_uc_types.h" 16 17struct xe_exec_queue_ops; 18struct xe_migrate; 19struct xe_ring_ops; 20 21enum xe_gt_type { 22 XE_GT_TYPE_UNINITIALIZED, 23 XE_GT_TYPE_MAIN, 24 XE_GT_TYPE_MEDIA, 25}; 26 27#define XE_MAX_DSS_FUSE_REGS 3 28#define XE_MAX_EU_FUSE_REGS 1 29 30typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)]; 31typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(32 * XE_MAX_EU_FUSE_REGS)]; 32 33struct xe_mmio_range { 34 u32 start; 35 u32 end; 36}; 37 38/* 39 * The hardware has multiple kinds of multicast register ranges that need 40 * special register steering (and future platforms are expected to add 41 * additional types). 42 * 43 * During driver startup, we initialize the steering control register to 44 * direct reads to a slice/subslice that are valid for the 'subslice' class 45 * of multicast registers. If another type of steering does not have any 46 * overlap in valid steering targets with 'subslice' style registers, we will 47 * need to explicitly re-steer reads of registers of the other type. 48 * 49 * Only the replication types that may need additional non-default steering 50 * are listed here. 51 */ 52enum xe_steering_type { 53 L3BANK, 54 MSLICE, 55 LNCF, 56 DSS, 57 OADDRM, 58 SQIDI_PSMI, 59 60 /* 61 * On some platforms there are multiple types of MCR registers that 62 * will always return a non-terminated value at instance (0, 0). We'll 63 * lump those all into a single category to keep things simple. 64 */ 65 INSTANCE0, 66 67 /* 68 * Register ranges that don't need special steering for each register: 69 * it's sufficient to keep the HW-default for the selector, or only 70 * change it once, on GT initialization. This needs to be the last 71 * steering type. 72 */ 73 IMPLICIT_STEERING, 74 NUM_STEERING_TYPES 75}; 76 77#define gt_to_tile(gt__) \ 78 _Generic(gt__, \ 79 const struct xe_gt * : (const struct xe_tile *)((gt__)->tile), \ 80 struct xe_gt * : (gt__)->tile) 81 82#define gt_to_xe(gt__) \ 83 _Generic(gt__, \ 84 const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)->xe), \ 85 struct xe_gt * : gt_to_tile(gt__)->xe) 86 87/** 88 * struct xe_gt - A "Graphics Technology" unit of the GPU 89 * 90 * A GT ("Graphics Technology") is the subset of a GPU primarily responsible 91 * for implementing the graphics, compute, and/or media IP. It encapsulates 92 * the hardware engines, programmable execution units, and GuC. Each GT has 93 * its own handling of power management (RC6+forcewake) and multicast register 94 * steering. 95 * 96 * A GPU/tile may have a single GT that supplies all graphics, compute, and 97 * media functionality, or the graphics/compute and media may be split into 98 * separate GTs within a tile. 99 */ 100struct xe_gt { 101 /** @tile: Backpointer to GT's tile */ 102 struct xe_tile *tile; 103 104 /** @info: GT info */ 105 struct { 106 /** @info.type: type of GT */ 107 enum xe_gt_type type; 108 /** @info.id: Unique ID of this GT within the PCI Device */ 109 u8 id; 110 /** @info.reference_clock: clock frequency */ 111 u32 reference_clock; 112 /** @info.engine_mask: mask of engines present on GT */ 113 u64 engine_mask; 114 /** 115 * @info.__engine_mask: mask of engines present on GT read from 116 * xe_pci.c, used to fake reading the engine_mask from the 117 * hwconfig blob. 118 */ 119 u64 __engine_mask; 120 /** @info.gmdid: raw GMD_ID value from hardware */ 121 u32 gmdid; 122 } info; 123 124 /** 125 * @mmio: mmio info for GT. All GTs within a tile share the same 126 * register space, but have their own copy of GSI registers at a 127 * specific offset, as well as their own forcewake handling. 128 */ 129 struct { 130 /** @mmio.fw: force wake for GT */ 131 struct xe_force_wake fw; 132 /** 133 * @mmio.adj_limit: adjust MMIO address if address is below this 134 * value 135 */ 136 u32 adj_limit; 137 /** @mmio.adj_offset: offect to add to MMIO address when adjusting */ 138 u32 adj_offset; 139 } mmio; 140 141 /** 142 * @reg_sr: table with registers to be restored on GT init/resume/reset 143 */ 144 struct xe_reg_sr reg_sr; 145 146 /** @reset: state for GT resets */ 147 struct { 148 /** 149 * @reset.worker: work so GT resets can done async allowing to reset 150 * code to safely flush all code paths 151 */ 152 struct work_struct worker; 153 } reset; 154 155 /** @tlb_invalidation: TLB invalidation state */ 156 struct { 157 /** @tlb_invalidation.seqno: TLB invalidation seqno, protected by CT lock */ 158#define TLB_INVALIDATION_SEQNO_MAX 0x100000 159 int seqno; 160 /** 161 * @tlb_invalidation.seqno_recv: last received TLB invalidation seqno, 162 * protected by CT lock 163 */ 164 int seqno_recv; 165 /** 166 * @tlb_invalidation.pending_fences: list of pending fences waiting TLB 167 * invaliations, protected by CT lock 168 */ 169 struct list_head pending_fences; 170 /** 171 * @tlb_invalidation.pending_lock: protects @tlb_invalidation.pending_fences 172 * and updating @tlb_invalidation.seqno_recv. 173 */ 174 spinlock_t pending_lock; 175 /** 176 * @tlb_invalidation.fence_tdr: schedules a delayed call to 177 * xe_gt_tlb_fence_timeout after the timeut interval is over. 178 */ 179 struct delayed_work fence_tdr; 180 /** @tlb_invalidation.lock: protects TLB invalidation fences */ 181 spinlock_t lock; 182 } tlb_invalidation; 183 184 /** 185 * @ccs_mode: Number of compute engines enabled. 186 * Allows fixed mapping of available compute slices to compute engines. 187 * By default only the first available compute engine is enabled and all 188 * available compute slices are allocated to it. 189 */ 190 u32 ccs_mode; 191 192 /** @usm: unified shared memory state */ 193 struct { 194 /** 195 * @usm.bb_pool: Pool from which batchbuffers, for USM operations 196 * (e.g. migrations, fixing page tables), are allocated. 197 * Dedicated pool needed so USM operations to not get blocked 198 * behind any user operations which may have resulted in a 199 * fault. 200 */ 201 struct xe_sa_manager *bb_pool; 202 /** 203 * @usm.reserved_bcs_instance: reserved BCS instance used for USM 204 * operations (e.g. mmigrations, fixing page tables) 205 */ 206 u16 reserved_bcs_instance; 207 /** @usm.pf_wq: page fault work queue, unbound, high priority */ 208 struct workqueue_struct *pf_wq; 209 /** @usm.acc_wq: access counter work queue, unbound, high priority */ 210 struct workqueue_struct *acc_wq; 211 /** 212 * @usm.pf_queue: Page fault queue used to sync faults so faults can 213 * be processed not under the GuC CT lock. The queue is sized so 214 * it can sync all possible faults (1 per physical engine). 215 * Multiple queues exists for page faults from different VMs are 216 * be processed in parallel. 217 */ 218 struct pf_queue { 219 /** @usm.pf_queue.gt: back pointer to GT */ 220 struct xe_gt *gt; 221#define PF_QUEUE_NUM_DW 128 222 /** @usm.pf_queue.data: data in the page fault queue */ 223 u32 data[PF_QUEUE_NUM_DW]; 224 /** 225 * @usm.pf_queue.tail: tail pointer in DWs for page fault queue, 226 * moved by worker which processes faults (consumer). 227 */ 228 u16 tail; 229 /** 230 * @usm.pf_queue.head: head pointer in DWs for page fault queue, 231 * moved by G2H handler (producer). 232 */ 233 u16 head; 234 /** @usm.pf_queue.lock: protects page fault queue */ 235 spinlock_t lock; 236 /** @usm.pf_queue.worker: to process page faults */ 237 struct work_struct worker; 238#define NUM_PF_QUEUE 4 239 } pf_queue[NUM_PF_QUEUE]; 240 /** 241 * @usm.acc_queue: Same as page fault queue, cannot process access 242 * counters under CT lock. 243 */ 244 struct acc_queue { 245 /** @usm.acc_queue.gt: back pointer to GT */ 246 struct xe_gt *gt; 247#define ACC_QUEUE_NUM_DW 128 248 /** @usm.acc_queue.data: data in the page fault queue */ 249 u32 data[ACC_QUEUE_NUM_DW]; 250 /** 251 * @usm.acc_queue.tail: tail pointer in DWs for access counter queue, 252 * moved by worker which processes counters 253 * (consumer). 254 */ 255 u16 tail; 256 /** 257 * @usm.acc_queue.head: head pointer in DWs for access counter queue, 258 * moved by G2H handler (producer). 259 */ 260 u16 head; 261 /** @usm.acc_queue.lock: protects page fault queue */ 262 spinlock_t lock; 263 /** @usm.acc_queue.worker: to process access counters */ 264 struct work_struct worker; 265#define NUM_ACC_QUEUE 4 266 } acc_queue[NUM_ACC_QUEUE]; 267 } usm; 268 269 /** @ordered_wq: used to serialize GT resets and TDRs */ 270 struct workqueue_struct *ordered_wq; 271 272 /** @uc: micro controllers on the GT */ 273 struct xe_uc uc; 274 275 /** @gtidle: idle properties of GT */ 276 struct xe_gt_idle gtidle; 277 278 /** @exec_queue_ops: submission backend exec queue operations */ 279 const struct xe_exec_queue_ops *exec_queue_ops; 280 281 /** 282 * @ring_ops: ring operations for this hw engine (1 per engine class) 283 */ 284 const struct xe_ring_ops *ring_ops[XE_ENGINE_CLASS_MAX]; 285 286 /** @fence_irq: fence IRQs (1 per engine class) */ 287 struct xe_hw_fence_irq fence_irq[XE_ENGINE_CLASS_MAX]; 288 289 /** @default_lrc: default LRC state */ 290 void *default_lrc[XE_ENGINE_CLASS_MAX]; 291 292 /** @hw_engines: hardware engines on the GT */ 293 struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES]; 294 295 /** @eclass: per hardware engine class interface on the GT */ 296 struct xe_hw_engine_class_intf eclass[XE_ENGINE_CLASS_MAX]; 297 298 /** @pcode: GT's PCODE */ 299 struct { 300 /** @pcode.lock: protecting GT's PCODE mailbox data */ 301 struct mutex lock; 302 } pcode; 303 304 /** @sysfs: sysfs' kobj used by xe_gt_sysfs */ 305 struct kobject *sysfs; 306 307 /** @freq: Main GT freq sysfs control */ 308 struct kobject *freq; 309 310 /** @mocs: info */ 311 struct { 312 /** @mocs.uc_index: UC index */ 313 u8 uc_index; 314 /** @mocs.wb_index: WB index, only used on L3_CCS platforms */ 315 u8 wb_index; 316 } mocs; 317 318 /** @fuse_topo: GT topology reported by fuse registers */ 319 struct { 320 /** @fuse_topo.g_dss_mask: dual-subslices usable by geometry */ 321 xe_dss_mask_t g_dss_mask; 322 323 /** @fuse_topo.c_dss_mask: dual-subslices usable by compute */ 324 xe_dss_mask_t c_dss_mask; 325 326 /** @fuse_topo.eu_mask_per_dss: EU mask per DSS*/ 327 xe_eu_mask_t eu_mask_per_dss; 328 } fuse_topo; 329 330 /** @steering: register steering for individual HW units */ 331 struct { 332 /** @steering.ranges: register ranges used for this steering type */ 333 const struct xe_mmio_range *ranges; 334 335 /** @steering.group_target: target to steer accesses to */ 336 u16 group_target; 337 /** @steering.instance_target: instance to steer accesses to */ 338 u16 instance_target; 339 } steering[NUM_STEERING_TYPES]; 340 341 /** 342 * @mcr_lock: protects the MCR_SELECTOR register for the duration 343 * of a steered operation 344 */ 345 spinlock_t mcr_lock; 346 347 /** @wa_active: keep track of active workarounds */ 348 struct { 349 /** @wa_active.gt: bitmap with active GT workarounds */ 350 unsigned long *gt; 351 /** @wa_active.engine: bitmap with active engine workarounds */ 352 unsigned long *engine; 353 /** @wa_active.lrc: bitmap with active LRC workarounds */ 354 unsigned long *lrc; 355 /** @wa_active.oob: bitmap with active OOB workaroudns */ 356 unsigned long *oob; 357 } wa_active; 358}; 359 360#endif 361