drivers/ata/sata_sx4.c

419 	void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
428 	mmio += PDC_CHIP0_OFS;
466 	writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
470 	ata_port_dbg(ap, "ata pkt buf ofs %u, prd size %u, mmio copied\n",
478 	void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
484 	mmio += PDC_CHIP0_OFS;
500 	writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
504 	ata_port_dbg(ap, "ata pkt buf ofs %u, mmio copied\n", i);
529 	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
532 	mmio += PDC_CHIP0_OFS;
534 	writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
535 	readl(mmio + PDC_20621_SEQCTL + (seq * 4));	/* flush */
537 	writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
538 	readl(mmio + PDC_HDMA_PKT_SUBMIT);	/* flush */
597 	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
603 	mmio += PDC_CHIP0_OFS;
620 		writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
621 		readl(mmio + PDC_20621_SEQCTL + (seq * 4));	/* flush */
658 					  void __iomem *mmio)
672 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
683 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
698 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
701 			writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
702 			readl(mmio + PDC_20621_SEQCTL + (seq * 4));
711 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
795 	void __iomem *mmio = ap->ioaddr.cmd_addr;
800 	tmp = readl(mmio + PDC_CTLSTAT);
803 	writel(tmp, mmio + PDC_CTLSTAT);
804 	readl(mmio + PDC_CTLSTAT); /* flush */
809 	void __iomem *mmio = ap->ioaddr.cmd_addr;
818 	tmp = readl(mmio + PDC_CTLSTAT);
820 	writel(tmp, mmio + PDC_CTLSTAT);
821 	readl(mmio + PDC_CTLSTAT); /* flush */
826 	void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
833 		tmp = readl(mmio);
840 		writel(tmp, mmio);
844 	writel(tmp, mmio);
845 	readl(mmio);	/* flush */
943 	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
947 	mmio += PDC_CHIP0_OFS;
953 	writel(0x01, mmio + PDC_GENERAL_CTLR);
954 	readl(mmio + PDC_GENERAL_CTLR);
955 	writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
956 	readl(mmio + PDC_DIMM_WINDOW_CTLR);
966 		writel(0x01, mmio + PDC_GENERAL_CTLR);
967 		readl(mmio + PDC_GENERAL_CTLR);
968 		writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
969 		readl(mmio + PDC_DIMM_WINDOW_CTLR);
977 		writel(0x01, mmio + PDC_GENERAL_CTLR);
978 		readl(mmio + PDC_GENERAL_CTLR);
979 		writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
980 		readl(mmio + PDC_DIMM_WINDOW_CTLR);
993 	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
997 	mmio += PDC_CHIP0_OFS;
1003 	writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1004 	readl(mmio + PDC_DIMM_WINDOW_CTLR);
1009 	writel(0x01, mmio + PDC_GENERAL_CTLR);
1010 	readl(mmio + PDC_GENERAL_CTLR);
1015 		writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1016 		readl(mmio + PDC_DIMM_WINDOW_CTLR);
1018 		writel(0x01, mmio + PDC_GENERAL_CTLR);
1019 		readl(mmio + PDC_GENERAL_CTLR);
1026 		writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1027 		readl(mmio + PDC_DIMM_WINDOW_CTLR);
1029 		writel(0x01, mmio + PDC_GENERAL_CTLR);
1030 		readl(mmio + PDC_GENERAL_CTLR);
1038 	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1044 	mmio += PDC_CHIP0_OFS;
1050 	writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1051 	readl(mmio + PDC_I2C_ADDR_DATA);
1055 	       mmio + PDC_I2C_CONTROL);
1058 		status = readl(mmio + PDC_I2C_CONTROL);
1060 			status = readl(mmio + PDC_I2C_ADDR_DATA);
1097 	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1117 	mmio += PDC_CHIP0_OFS;
1150 	writel(data, mmio + PDC_DIMM0_CONTROL);
1151 	readl(mmio + PDC_DIMM0_CONTROL);
1160 	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1163 	mmio += PDC_CHIP0_OFS;
1173 	writel(data, mmio + PDC_SDRAM_CONTROL);
1174 	readl(mmio + PDC_SDRAM_CONTROL);
1186 		writel(data, mmio + PDC_SDRAM_CONTROL);
1187 		readl(mmio + PDC_SDRAM_CONTROL);
1194 	writel(data, mmio + PDC_SDRAM_CONTROL);
1198 		data = readl(mmio + PDC_SDRAM_CONTROL);
1218 	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1221 	mmio += PDC_CHIP0_OFS;
1226 	writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1227 	time_period = readl(mmio + PDC_TIME_PERIOD);
1231 	writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1232 	readl(mmio + PDC_TIME_CONTROL);
1242 	tcount = readl(mmio + PDC_TIME_COUNTER);
1272 	writel(pci_status, mmio + PDC_CTL_STATUS);
1273 	readl(mmio + PDC_CTL_STATUS);
1357 	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1360 	mmio += PDC_CHIP0_OFS;
1365 	tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1367 	writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1372 	tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1374 	writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1375 	readl(mmio + PDC_HDMA_CTLSTAT);		/* flush */
1379 	tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1381 	writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1382 	readl(mmio + PDC_HDMA_CTLSTAT);		/* flush */
1424 		ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");