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302b84e8 |
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28-Mar-2024 |
Bjorn Helgaas <bhelgaas@google.com> |
Revert "PCI: Mark LSI FW643 to avoid bus reset" This reverts commit 29a43dc130ce65d365a8ea9e1cc4bc51005a353e. 29a43dc130ce ("PCI: Mark LSI FW643 to avoid bus reset") by Edmund was based on the assumption that the LSI / Agere FW643 has a defect such that it can't recover after a Secondary Bus Reset (SBR). But Takashi Sakamoto reported that SBR works fine on this same FW643 device in an AMD Ryzen 5 2400G system, so apparently there is some other aspect of Edmund's system that accounts for the issue. The down side of 29a43dc130ce is that when the FW643 is assigned to a VM, avoiding the SBR means we leak data out of the VM. Revert 29a43dc130ce until we figure out a better solution. In the meantime, we can use the sysfs "reset_method" interface to restrict the available reset methods. Link: https://lore.kernel.org/r/20240328212302.1582483-1-helgaas@kernel.org Fixes: 29a43dc130ce ("PCI: Mark LSI FW643 to avoid bus reset") Reported-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Link: https://lore.kernel.org/r/20240325012135.36861-1-o-takashi@sakamocchi.jp Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
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#
627c6db2 |
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04-Mar-2024 |
Paul Menzel <pmenzel@molgen.mpg.de> |
PCI/DPC: Quirk PIO log size for Intel Raptor Lake Root Ports Commit 5459c0b70467 ("PCI/DPC: Quirk PIO log size for certain Intel Root Ports") and commit 3b8803494a06 ("PCI/DPC: Quirk PIO log size for Intel Ice Lake Root Ports") add quirks for Ice, Tiger and Alder Lake Root Ports. System firmware for Raptor Lake still has the bug, so Linux logs the warning below on several Raptor Lake systems like Dell Precision 3581 with Intel Raptor Lake processor (0W18NX) system firmware/BIOS version 1.10.1. pci 0000:00:07.0: [8086:a76e] type 01 class 0x060400 pci 0000:00:07.0: DPC: RP PIO log size 0 is invalid pci 0000:00:07.1: [8086:a73f] type 01 class 0x060400 pci 0000:00:07.1: DPC: RP PIO log size 0 is invalid Apply the quirk for Raptor Lake Root Ports as well. This also enables the DPC driver to dump the RP PIO Log registers when DPC is triggered. Link: https://lore.kernel.org/r/20240305113057.56468-1-pmenzel@molgen.mpg.de Reported-by: Niels van Aert <nvaert1986@hotmail.com> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218560 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: <stable@vger.kernel.org> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Niels van Aert <nvaert1986@hotmail.com>
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29a43dc1 |
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27-Feb-2024 |
Edmund Raile <edmund.raile@proton.me> |
PCI: Mark LSI FW643 to avoid bus reset Apparently the LSI / Agere FW643 can't recover after a Secondary Bus Reset and requires a power-off or suspend/resume and rescan. VFIO resets a device before assigning it to a VM, and the FW643 doesn't support any other reset methods, so this problem prevented assignment of FW643 to VMs. Prevent use of Secondary Bus Reset for this device. With this change, the FW643 can be assigned to VMs with VFIO. Note that it will not be reset, resulting in leaking state between VMs and host. Link: https://lore.kernel.org/r/20240227131401.17913-1-edmund.raile@proton.me Signed-off-by: Edmund Raile <edmund.raile@proton.me> [bhelgaas: commit log, comment] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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baf67aef |
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19-Feb-2024 |
Jörg Wedekind <joerg@wedekind.de> |
PCI: Mark 3ware-9650SE Root Port Extended Tags as broken Per PCIe r6.1, sec 2.2.6.2 and 7.5.3.4, a Requester may not use 8-bit Tags unless its Extended Tag Field Enable is set, but all Receivers/Completers must handle 8-bit Tags correctly regardless of their Extended Tag Field Enable. Some devices do not handle 8-bit Tags as Completers, so add a quirk for them. If we find such a device, we disable Extended Tags for the entire hierarchy to make peer-to-peer DMA possible. The 3ware 9650SE seems to have issues with handling 8-bit tags. Mark it as broken. This fixes PCI Parity Errors like : 3w-9xxx: scsi0: ERROR: (0x06:0x000C): PCI Parity Error: clearing. 3w-9xxx: scsi0: ERROR: (0x06:0x000D): PCI Abort: clearing. 3w-9xxx: scsi0: ERROR: (0x06:0x000E): Controller Queue Error: clearing. 3w-9xxx: scsi0: ERROR: (0x06:0x0010): Microcontroller Error: clearing. Link: https://lore.kernel.org/r/20240219132811.8351-1-joerg@wedekind.de Fixes: 60db3a4d8cc9 ("PCI: Enable PCIe Extended Tags if supported") Closes: https://bugzilla.kernel.org/show_bug.cgi?id=202425 Signed-off-by: Jörg Wedekind <joerg@wedekind.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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dc4e6f21 |
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06-Nov-2021 |
Puranjay Mohan <puranjay12@gmail.com> |
PCI: Use resource names in PCI log messages Use the pci_resource_name() to get the name of the resource and use it while printing log messages. [bhelgaas: rename to match struct resource * names, also use names in other BAR messages] Link: https://lore.kernel.org/r/20211106112606.192563-3-puranjay12@gmail.com Signed-off-by: Puranjay Mohan <puranjay12@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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e367e3c7 |
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11-Dec-2023 |
LeoLiuoc <LeoLiu-oc@zhaoxin.com> |
PCI: Add ACS quirk for more Zhaoxin Root Ports Add more Root Port Device IDs to pci_quirk_zhaoxin_pcie_ports_acs() for some new Zhaoxin platforms. Fixes: 299bd044a6f3 ("PCI: Add ACS quirk for Zhaoxin Root/Downstream Ports") Link: https://lore.kernel.org/r/20231211091543.735903-1-LeoLiu-oc@zhaoxin.com Signed-off-by: LeoLiuoc <LeoLiu-oc@zhaoxin.com> [bhelgaas: update subject, drop changelog, add Fixes, add stable tag, fix whitespace, wrap code comment] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: <stable@vger.kernel.org> # 5.7
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e585a37e |
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20-Nov-2023 |
Guilherme G. Piccoli <gpiccoli@igalia.com> |
PCI: Only override AMD USB controller if required By running a Van Gogh device (Steam Deck), the following message was noticed in the kernel log: pci 0000:04:00.3: PCI class overridden (0x0c03fe -> 0x0c03fe) so dwc3 driver can claim this instead of xhci Effectively this means the quirk executed but changed nothing, since the class of this device was already the proper one (likely adjusted by newer firmware versions). Check and perform the override only if necessary. Link: https://lore.kernel.org/r/20231120160531.361552-1-gpiccoli@igalia.com Signed-off-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Huang Rui <ray.huang@amd.com> Cc: Vicki Pfau <vi@endrift.com>
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3ed48c80 |
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15-Nov-2023 |
Ido Schimmel <idosch@nvidia.com> |
PCI: Add no PM reset quirk for NVIDIA Spectrum devices Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset (i.e., they advertise NoSoftRst-). However, this transition does not have any effect on the device: It continues to be operational and network ports remain up. Advertising this support makes it seem as if a PM reset is viable for these devices. Mark it as unavailable to skip it when testing reset methods. Before: # cat /sys/bus/pci/devices/0000\:03\:00.0/reset_method pm bus After: # cat /sys/bus/pci/devices/0000\:03\:00.0/reset_method bus Signed-off-by: Ido Schimmel <idosch@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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0fce6e5c |
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26-Oct-2023 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
PCI: Simplify pcie_capability_clear_and_set_word() to ..._clear_word() When using pcie_capability_clear_and_set_word() but not actually *setting* anything, use pcie_capability_clear_word() instead. Link: https://lore.kernel.org/r/20231026121924.2164-1-ilpo.jarvinen@linux.intel.com Link: https://lore.kernel.org/r/20231026121924.2164-2-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> [bhelgaas: squash] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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9a9eec47 |
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18-Oct-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/DPC: Use FIELD_GET() Use FIELD_GET() to remove dependencies on the field position, i.e., the shift value. No functional change intended. Link: https://lore.kernel.org/r/20231018113254.17616-5-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
a18615b1 |
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08-Sep-2023 |
Bartosz Pawlowski <bartosz.pawlowski@intel.com> |
PCI: Disable ATS for specific Intel IPU E2000 devices Due to a hardware issue in A and B steppings of Intel IPU E2000, it expects wrong endianness in ATS invalidation message body. This problem can lead to outdated translations being returned as valid and finally cause system instability. To prevent such issues, add quirk_intel_e2000_no_ats() to disable ATS for vulnerable IPU E2000 devices. Link: https://lore.kernel.org/r/20230908143606.685930-3-bartosz.pawlowski@intel.com Signed-off-by: Bartosz Pawlowski <bartosz.pawlowski@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Alexander Lobakin <aleksander.lobakin@intel.com>
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f18b1137 |
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08-Sep-2023 |
Bartosz Pawlowski <bartosz.pawlowski@intel.com> |
PCI: Extract ATS disabling to a helper function Introduce quirk_no_ats() helper function to provide a standard way to disable ATS capability in PCI quirks. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230908143606.685930-2-bartosz.pawlowski@intel.com Signed-off-by: Bartosz Pawlowski <bartosz.pawlowski@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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d15f1805 |
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11-Sep-2023 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
PCI: Do error check on own line to split long "if" conditions Placing PCI error code check inside "if" condition usually results in need to split lines. Combined with additional conditions the "if" condition becomes messy. Convert to the usual error handling pattern with an additional variable to improve code readability. In addition, reverse the logic in pci_find_vsec_capability() to get rid of &&. No functional changes intended. Link: https://lore.kernel.org/r/20230911125354.25501-5-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> [bhelgaas: PCI_POSSIBLE_ERROR()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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7e6f3b6d |
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27-Sep-2023 |
Vicki Pfau <vi@endrift.com> |
PCI: Prevent xHCI driver from claiming AMD VanGogh USB3 DRD device The AMD VanGogh SoC contains a DesignWare USB3 Dual-Role Device that can be operated as either a USB Host or a USB Device, similar to on the AMD Nolan platform. be6646bfbaec ("PCI: Prevent xHCI driver from claiming AMD Nolan USB3 DRD device") added a quirk to let the dwc3 driver claim the Nolan device since it provides more specific support. Extend that quirk to include the VanGogh SoC USB3 device. Link: https://lore.kernel.org/r/20230927202212.2388216-1-vi@endrift.com Signed-off-by: Vicki Pfau <vi@endrift.com> [bhelgaas: include be6646bfbaec reference, add stable tag] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v3.19+
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83c08814 |
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03-Oct-2023 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
PCI: Use PCI_HEADER_TYPE_* instead of literals Replace literals under drivers/pci/ with PCI_HEADER_TYPE_MASK, PCI_HEADER_TYPE_NORMAL, and PCI_HEADER_TYPE_MFD. Also replace !! boolean conversions with FIELD_GET(). Link: https://lore.kernel.org/r/20231003125300.5541-4-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # for Renesas R-Car
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c9260693 |
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21-Sep-2023 |
Lukas Wunner <lukas@wunner.de> |
PCI: Lengthen reset delay for VideoPropulsion Torrent QN16e card Commit ac91e6980563 ("PCI: Unify delay handling for reset and resume") shortened an unconditional 1 sec delay after a Secondary Bus Reset to 100 msec for PCIe (per PCIe r6.1 sec 6.6.1). The 1 sec delay is only required for Conventional PCI. But it turns out that there are PCIe devices which require a longer delay than prescribed before first config space access after reset recovery or resume from D3cold: Chad reports that a "VideoPropulsion Torrent QN16e" MPEG QAM Modulator "raises a PCI system error (PERR), as reported by the IPMI event log, and the hardware itself would suffer a catastrophic event, cycling the server" unless the longer delay is observed. The card is specified to conform to PCIe r1.0 and indeed only supports Gen1 speed (2.5 GT/s) according to lspci. PCIe r1.0 sec 7.6 prescribes the same 100 msec delay as PCIe r6.1 sec 6.6.1: To allow components to perform internal initialization, system software must wait for at least 100 ms from the end of a reset (cold/warm/hot) before it is permitted to issue Configuration Requests The behavior of the Torrent QN16e card thus appears to be a quirk. Treat it as such and lengthen the reset delay for this specific device. Fixes: ac91e6980563 ("PCI: Unify delay handling for reset and resume") Link: https://lore.kernel.org/r/47727e792c7f0282dc144e3ec8ce8eb6e713394e.1695304512.git.lukas@wunner.de Reported-by: Chad Schroeder <CSchroeder@sonifi.com> Closes: https://lore.kernel.org/linux-pci/DM6PR16MB2844903E34CAB910082DF019B1FAA@DM6PR16MB2844.namprd16.prod.outlook.com/ Tested-by: Chad Schroeder <CSchroeder@sonifi.com> Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v5.4+
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5260bd6d |
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08-Sep-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
Revert "PCI: Mark NVIDIA T4 GPUs to avoid bus reset" This reverts commit d5af729dc2071273f14cbb94abbc60608142fd83. d5af729dc207 ("PCI: Mark NVIDIA T4 GPUs to avoid bus reset") avoided Secondary Bus Reset on the T4 because the reset seemed to not work when the T4 was directly attached to a Root Port. But NVIDIA thinks the issue is probably related to some issue with the Root Port, not with the T4. The T4 provides neither PM nor FLR reset, so masking bus reset compromises this device for assignment scenarios. Revert d5af729dc207 as requested by Wu Zongyong. This will leave SBR broken in the specific configuration Wu tested, as it was in v6.5, so Wu will debug that further. Link: https://lore.kernel.org/r/ZPqMCDWvITlOLHgJ@wuzongyong-alibaba Link: https://lore.kernel.org/r/20230908201104.GA305023@bhelgaas Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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86b4ad7d |
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24-Aug-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Fix typos in docs and comments Fix typos in docs and comments. Link: https://lore.kernel.org/r/20230824193712.542167-11-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
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26409dd0 |
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15-Aug-2023 |
Lizhi Hou <lizhi.hou@amd.com> |
of: unittest: Add pci_dt_testdrv pci driver pci_dt_testdrv is bound to QEMU PCI Test Device. It reads overlay_pci_node fdt fragment and apply it to Test Device. Then it calls of_platform_default_populate() to populate the platform devices. Tested-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://lore.kernel.org/r/1692120000-46900-6-git-send-email-lizhi.hou@amd.com Signed-off-by: Rob Herring <robh@kernel.org>
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ae9813db |
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15-Aug-2023 |
Lizhi Hou <lizhi.hou@amd.com> |
PCI: Add quirks to generate device tree node for Xilinx Alveo U50 The Xilinx Alveo U50 PCI card exposes multiple hardware peripherals on its PCI BAR. The card firmware provides a flattened device tree to describe the hardware peripherals on its BARs. This allows U50 driver to load the flattened device tree and generate the device tree node for hardware peripherals underneath. To generate device tree node for U50 card, add PCI quirks to call of_pci_make_dev_node() for U50. Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://lore.kernel.org/r/1692120000-46900-4-git-send-email-lizhi.hou@amd.com Signed-off-by: Rob Herring <robh@kernel.org>
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#
d5af729d |
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10-Apr-2023 |
Wu Zongyong <wuzongyong@linux.alibaba.com> |
PCI: Mark NVIDIA T4 GPUs to avoid bus reset NVIDIA T4 GPUs do not work with SBR. This problem is found when the T4 card is direct attached to a Root Port only. Avoid bus reset by marking T4 GPUs PCI_DEV_FLAGS_NO_BUS_RESET. Fixes: 4c207e7121fa ("PCI: Mark some NVIDIA GPUs to avoid bus reset") Link: https://lore.kernel.org/r/2dcebea53a6eb9bd212ec6d8974af2e5e0333ef6.1681129861.git.wuzongyong@linux.alibaba.com Signed-off-by: Wu Zongyong <wuzongyong@linux.alibaba.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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0fb53e64 |
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23-Jun-2023 |
Kelvin Cao <kelvin.cao@microchip.com> |
PCI: switchtec: Add support for PCIe Gen5 devices Advertise support of Gen5 devices in the driver's device ID table and add the same IDs for the switchtec quirks. Also update driver code to accommodate them. Link: https://lore.kernel.org/r/20230624000003.2315364-3-kelvin.cao@microchip.com Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
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f768c75d |
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03-Jul-2023 |
Niklas Schnelle <schnelle@linux.ibm.com> |
PCI: Make quirk using inw() depend on HAS_IOPORT In the future inw() and friends will not be compiled on architectures without I/O port support. Co-developed-by: Arnd Bergmann <arnd@kernel.org> Link: https://lore.kernel.org/r/20230703135255.2202721-2-schnelle@linux.ibm.com Signed-off-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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a89c8224 |
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11-Jun-2023 |
Maciej W. Rozycki <macro@orcam.me.uk> |
PCI: Work around PCIe link training failures Attempt to handle cases such as with a downstream port of the ASMedia ASM2824 PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches should negotiate a link speed of 5.0GT/s, falling back to 2.5GT/s if necessary. Instead the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time. Limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly. Removing the speed restriction afterwards makes the two devices switch to 5.0GT/s then. Make use of these observations and detect the inability to train the link by checking for the Data Link Layer Link Active status bit being off while the Link Bandwidth Management Status indicating that hardware has changed the link speed or width in an attempt to correct unreliable link operation. Restrict the speed to 2.5GT/s then with the Target Link Speed field, request a retrain and wait 200ms for the data link to go up. If this is successful, lift the restriction, letting the devices negotiate a higher speed. Also check for a 2.5GT/s speed restriction the firmware may have already arranged and lift it too with ports of devices known to continue working afterwards (currently only ASM2824), that already report their data link being up. [bhelgaas: reorder and squash stubs from https://lore.kernel.org/r/alpine.DEB.2.21.2306111619570.64925@angie.orcam.me.uk to avoid adding stubs that do nothing] Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203022037020.56670@angie.orcam.me.uk/ Link: https://source.denx.de/u-boot/u-boot/-/commit/a398a51ccc68 Link: https://lore.kernel.org/r/alpine.DEB.2.21.2305310038540.59226@angie.orcam.me.uk Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
07a8d698 |
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11-Jun-2023 |
Maciej W. Rozycki <macro@orcam.me.uk> |
PCI: Execute quirk_enable_clear_retrain_link() earlier Make quirk_enable_clear_retrain_link() an early quirk so that any later fixups can rely on dev->clear_retrain_link to have been already initialised. [bhelgaas: reorder to just before it becomes possible to call pcie_retrain_link() earlier] Link: https://lore.kernel.org/r/alpine.DEB.2.21.2305310049000.59226@angie.orcam.me.uk Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
88d34171 |
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07-Jun-2023 |
Robin Murphy <robin.murphy@arm.com> |
PCI: Add function 1 DMA alias quirk for Marvell 88SE9235 Marvell's own product brief implies the 92xx series are a closely related family, and sure enough it turns out that 9235 seems to need the same quirk as the other three, although possibly only when certain ports are used. Link: https://lore.kernel.org/linux-iommu/2a699a99-545c-1324-e052-7d2f41fed1ae@yahoo.co.uk/ Link: https://lore.kernel.org/r/731507e05d70239aec96fcbfab6e65d8ce00edd2.1686157165.git.robin.murphy@arm.com Reported-by: Jason Adriaanse <jason_a69@yahoo.co.uk> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Cc: stable@vger.kernel.org
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#
0ac448e0 |
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07-May-2023 |
Mike Pastore <mike@oobak.org> |
PCI: Delay after FLR of Solidigm P44 Pro NVMe Prevent KVM hang when a Solidgm P44 Pro NVMe is passed through to a guest via IOMMU and the guest is subsequently rebooted. A similar issue was identified and patched by 51ba09452d11 ("PCI: Delay after FLR of Intel DC P3700 NVMe") and the same fix can be applied for this case. (Intel spun off their NAND and SSD business as Solidigm and sold it to SK Hynix in late 2021.) Link: https://lore.kernel.org/r/20230507073519.9737-1-mike@oobak.org Signed-off-by: Mike Pastore <mike@oobak.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
3b880349 |
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11-May-2023 |
Mika Westerberg <mika.westerberg@linux.intel.com> |
PCI/DPC: Quirk PIO log size for Intel Ice Lake Root Ports Commit 5459c0b70467 ("PCI/DPC: Quirk PIO log size for certain Intel Root Ports") added quirks for Tiger and Alder Lake Root Ports but missed that the same issue exists also in the previous generation, Ice Lake. Apply the quirk for Ice Lake Root Ports as well. This prevents kernel complaints like: DPC: RP PIO log size 0 is invalid and also enables the DPC driver to dump the RP PIO Log registers when DPC is triggered. [bhelgaas: add dmesg warning and RP PIO Log dump info] Closes: https://bugzilla.kernel.org/show_bug.cgi?id=209943 Link: https://lore.kernel.org/r/20230511121905.73949-1-mika.westerberg@linux.intel.com Reported-by: Mark Blakeney <mark.blakeney@bullet-systems.net> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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a5a6dd26 |
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13-Apr-2023 |
Alex Williamson <alex.williamson@redhat.com> |
PCI/PM: Extend D3hot delay for NVIDIA HDA controllers Assignment of NVIDIA Ampere-based GPUs have seen a regression since the below referenced commit, where the reduced D3hot transition delay appears to introduce a small window where a D3hot->D0 transition followed by a bus reset can wedge the device. The entire device is subsequently unavailable, returning -1 on config space read and is unrecoverable without a host reset. This has been observed with RTX A2000 and A5000 GPU and audio functions assigned to a Windows VM, where shutdown of the VM places the devices in D3hot prior to vfio-pci performing a bus reset when userspace releases the devices. The issue has roughly a 2-3% chance of occurring per shutdown. Restoring the HDA controller d3hot_delay to the effective value before the below commit has been shown to resolve the issue. NVIDIA confirms this change should be safe for all of their HDA controllers. Fixes: 3e347969a577 ("PCI/PM: Reduce D3hot delay with usleep_range()") Link: https://lore.kernel.org/r/20230413194042.605768-1-alex.williamson@redhat.com Reported-by: Zhiyi Guo <zhguo@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tarun Gupta <targupta@nvidia.com> Cc: Abhishek Sahu <abhsahu@nvidia.com> Cc: Tarun Gupta <targupta@nvidia.com>
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d089d69c |
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10-Jan-2023 |
Alvaro Karsz <alvaro.karsz@solid-run.com> |
PCI: Avoid FLR for SolidRun SNET DPU rev 1 This patch fixes a FLR bug on the SNET DPU rev 1 by setting the PCI_DEV_FLAGS_NO_FLR_RESET flag. As there is a quirk to avoid FLR (quirk_no_flr), I added a new quirk to check the rev ID before calling to quirk_no_flr. Without this patch, a SNET DPU rev 1 may hang when FLR is applied. Signed-off-by: Alvaro Karsz <alvaro.karsz@solid-run.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Message-Id: <20230110165638.123745-3-alvaro.karsz@solid-run.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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a2b9b123 |
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07-Feb-2023 |
Mengyuan Lou <mengyuanlou@net-swift.com> |
PCI: Add ACS quirk for Wangxun NICs Wangxun has verified there is no peer-to-peer between functions for the below selection of SFxxx, RP1000 and RP2000 NICS. They may be multi-function devices, but the hardware does not advertise ACS capability. Add an ACS quirk for these devices so the functions can be in independent IOMMU groups. Link: https://lore.kernel.org/r/20230207102419.44326-1-mengyuanlou@net-swift.com Signed-off-by: Mengyuan Lou <mengyuanlou@net-swift.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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63ba51db |
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27-Jan-2023 |
Damien Le Moal <damien.lemoal@opensource.wdc.com> |
PCI: Avoid FLR for AMD FCH AHCI adapters PCI passthrough to VMs does not work with AMD FCH AHCI adapters: the guest OS fails to correctly probe devices attached to the controller due to FIS communication failures: ata4: softreset failed (1st FIS failed) ... ata4.00: qc timeout after 5000 msecs (cmd 0xec) ata4.00: failed to IDENTIFY (I/O error, err_mask=0x4) Forcing the "bus" reset method before unbinding & binding the adapter to the vfio-pci driver solves this issue, e.g.: echo "bus" > /sys/bus/pci/devices/<ID>/reset_method gives a working guest OS, indicating that the default FLR reset method doesn't work correctly. Apply quirk_no_flr() to AMD FCH AHCI devices to work around this issue. Link: https://lore.kernel.org/r/20230128013951.523247-1-damien.lemoal@opensource.wdc.com Reported-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
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#
5459c0b7 |
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16-Aug-2022 |
Mika Westerberg <mika.westerberg@linux.intel.com> |
PCI/DPC: Quirk PIO log size for certain Intel Root Ports Some Root Ports on Intel Tiger Lake and Alder Lake systems support the RP Extensions for DPC and the RP PIO Log registers but incorrectly advertise an RP PIO Log Size of zero. This means the kernel complains that: DPC: RP PIO log size 0 is invalid and if DPC is triggered, the DPC driver will not dump the RP PIO Log registers when it should. This is caused by a BIOS bug and should be fixed the BIOS for future CPUs. Add a quirk to set the correct RP PIO Log size for the affected Root Ports. Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943 Link: https://lore.kernel.org/r/20220816102042.69125-1-mika.westerberg@linux.intel.com Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
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abb4970a |
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22-Jul-2022 |
Stafford Horne <shorne@gmail.com> |
PCI: Move isa_dma_bridge_buggy out of asm/dma.h The isa_dma_bridge_buggy symbol is only used for x86_32, and only x86_32 platforms or quirks ever set it. Add a new linux/isa-dma.h header that #defines isa_dma_bridge_buggy to 0 except on x86_32, where we keep it as a variable, and remove all the arch- specific definitions. [bhelgaas: commit log] Suggested-by: Arnd Bergmann <arnd@arndb.de> Suggested-by: Christoph Hellwig <hch@infradead.org> Link: https://lore.kernel.org/r/20220722214944.831438-3-shorne@gmail.com Signed-off-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
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bf32b8f9 |
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21-Jul-2022 |
Vidya Sagar <vidyas@nvidia.com> |
PCI: Disable MSI for Tegra234 Root Ports Tegra234 PCIe Root Ports don't generate MSI interrupts for PME and AER events. Since PCIe spec (r6.0 sec 6.1.4.3) doesn't support using a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid Root Port service drivers registering their respective ISRs with MSI interrupt and to let only INTx be used for all events. Link: https://lore.kernel.org/r/20220721142052.25971-8-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
afd306a6 |
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09-Jun-2022 |
Pavan Chebbi <pavan.chebbi@broadcom.com> |
PCI: Add ACS quirk for Broadcom BCM5750x NICs The Broadcom BCM5750x NICs may be multi-function devices. They do not advertise ACS capability. Peer-to-peer transactions are not possible between the individual functions, so it is safe to treat them as fully isolated. Add an ACS quirk for these devices so the functions can be in independent IOMMU groups and attached individually to userspace applications using VFIO. Link: https://lore.kernel.org/r/1654796507-28610-1-git-send-email-michael.chan@broadcom.com Signed-off-by: Pavan Chebbi <pavan.chebbi@broadcom.com> Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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03038d84 |
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04-Apr-2022 |
Mika Westerberg <mika.westerberg@linux.intel.com> |
PCI/ASPM: Make Intel DG2 L1 acceptable latency unlimited Intel DG2 discrete graphics PCIe endpoints advertise L1 acceptable exit latency to be < 1us even though they can actually tolerate unlimited exit latencies just fine. Quirk the L1 acceptable exit latency for these endpoints to be unlimited so ASPM L1 can be enabled. [bhelgaas: use FIELD_GET/FIELD_PREP, wordsmith comment & commit log] Link: https://lore.kernel.org/r/20220405093810.76613-1-mika.westerberg@linux.intel.com Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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63cd736f |
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21-Mar-2022 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Avoid broken MSI on SB600 USB devices Some ATI SB600 USB adapters advertise MSI, but if INTx is disabled by setting PCI_COMMAND_INTX_DISABLE, MSI doesn't work either. The PCI/PCIe specs do not require software to set PCI_COMMAND_INTX_DISABLE when enabling MSI, but Linux has done that for many years. Mick reported that 306c54d0edb6 ("usb: hcd: Try MSI interrupts on PCI devices") broke these devices. Prior to 306c54d0edb6, they used INTx. Starting with 306c54d0edb6, they use MSI, and and the fact that Linux sets PCI_COMMAND_INTX_DISABLE means both INTx and MSI are disabled on these devices. Avoid this SB600 defect by disabling MSI so we use INTx as before. Fixes: 306c54d0edb6 ("usb: hcd: Try MSI interrupts on PCI devices") Link: https://lore.kernel.org/r/20220321183446.1108325-1-helgaas@kernel.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=215690 Link: https://lore.kernel.org/all/PxIByDyBRcsbpcmVhGSNDFAoUcMmb78ctXCkw6fbpx25TGlCHvA6SJjjFkNr1FfQZMntYPTNyvEnblxzAZ8a6jP9ddLpKeCN6Chi_2FuexU=@protonmail.com/ Link: https://lore.kernel.org/r/20220314101448.90074-1-andriy.shevchenko@linux.intel.com BugLink: https://lore.kernel.org/all/20200702143045.23429-1-andriy.shevchenko@linux.intel.com/ Reported-by: Mick Lorain <micklorain@protonmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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3f1271b5 |
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22-Feb-2022 |
Alex Deucher <alexander.deucher@amd.com> |
PCI: Mark all AMD Navi10 and Navi14 GPU ATS as broken There are enough VBIOS escapes without the proper workaround that some users still hit this. Microsoft never productized ATS on Windows so OEM platforms that were Windows-only didn't always validate ATS. The advantages of ATS are not worth it compared to the potential instabilities on harvested boards. Disable ATS on all Navi10 and Navi14 boards. Symptoms include: amdgpu 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0007 address=0xffffc02000 flags=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=07:00.0 domain=0x0007 address=0xffffc02000 flags=0x0000] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout, signaled seq=6047, emitted seq=6049 amdgpu 0000:07:00.0: amdgpu: GPU reset begin! amdgpu 0000:07:00.0: amdgpu: GPU reset succeeded, trying to resume amdgpu 0000:07:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring sdma0 test failed (-110) [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <sdma_v4_0> failed -110 amdgpu 0000:07:00.0: amdgpu: GPU reset(1) failed Related commits: e8946a53e2a6 ("PCI: Mark AMD Navi14 GPU ATS as broken") a2da5d8cc0b0 ("PCI: Mark AMD Raven iGPU ATS as broken in some platforms") 45beb31d3afb ("PCI: Mark AMD Navi10 GPU rev 0x00 ATS as broken") 5e89cd303e3a ("PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken") d28ca864c493 ("PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken") 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken") [bhelgaas: add symptoms and related commits] Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1760 Link: https://lore.kernel.org/r/20220222160801.841643-1-alexander.deucher@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Guchun Chen <guchun.chen@amd.com>
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500b55b0 |
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21-Dec-2021 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Work around Intel I210 ROM BAR overlap defect Per PCIe r5, sec 7.5.1.2.4, a device must not claim accesses to its Expansion ROM unless both the Memory Space Enable and the Expansion ROM Enable bit are set. But apparently some Intel I210 NICs don't work correctly if the ROM BAR overlaps another BAR, even if the Expansion ROM is disabled. Michael reported that on a Kontron SMARC-sAL28 ARM64 system with U-Boot v2021.01-rc3, the ROM BAR overlaps BAR 3, and networking doesn't work at all: BAR 0: 0x40000000 (32-bit, non-prefetchable) [size=1M] BAR 3: 0x40200000 (32-bit, non-prefetchable) [size=16K] ROM: 0x40200000 (disabled) [size=1M] NETDEV WATCHDOG: enP2p1s0 (igb): transmit queue 0 timed out Hardware name: Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier (DT) igb 0002:01:00.0 enP2p1s0: Reset adapter Previously, pci_std_update_resource() wrote the assigned ROM address to the BAR only when the ROM was enabled. This meant that the I210 ROM BAR could be left with an address assigned by firmware, which might overlap with other BARs. Quirk these I210 devices so pci_std_update_resource() always writes the assigned address to the ROM BAR, whether or not the ROM is enabled. Link: https://lore.kernel.org/r/20211223163754.GA1267351@bhelgaas Link: https://lore.kernel.org/r/20201230185317.30915-1-michael@walle.cc Link: https://bugzilla.kernel.org/show_bug.cgi?id=211105 Reported-by: Michael Walle <michael@walle.cc> Tested-by: Michael Walle <michael@walle.cc> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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ccd36795 |
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07-Jan-2022 |
Krzysztof Wilczyński <kw@linux.com> |
PCI: Correct misspelled words Fix a number of misspelled words, and while at it, correct two phrases used to indicate a status of an operation where words used have been cleverly truncated and thus always trigger a spellchecking error while performing a static code analysis over the PCI tree. [bhelgaas: reverse sense of quirk ternary] Link: https://lore.kernel.org/r/20220107225942.121484-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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e4453758 |
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01-Dec-2021 |
Yifeng Li <tomli@tomli.me> |
PCI: Add function 1 DMA alias quirk for Marvell 88SE9125 SATA controller Like other SATA controller chips in the Marvell 88SE91xx series, the Marvell 88SE9125 has the same DMA requester ID hardware bug that prevents it from working under IOMMU. Add it to the list of devices that need the quirk. Without this patch, device initialization fails with DMA errors: ata8: softreset failed (1st FIS failed) DMAR: DRHD: handling fault status reg 2 DMAR: [DMA Write NO_PASID] Request device [03:00.1] fault addr 0xfffc0000 [fault reason 0x02] Present bit in context entry is clear DMAR: DRHD: handling fault status reg 2 DMAR: [DMA Read NO_PASID] Request device [03:00.1] fault addr 0xfffc0000 [fault reason 0x02] Present bit in context entry is clear After applying the patch, the controller can be successfully initialized: ata8: SATA link up 1.5 Gbps (SStatus 113 SControl 330) ata8.00: ATAPI: PIONEER BD-RW BDR-207M, 1.21, max UDMA/100 ata8.00: configured for UDMA/100 scsi 7:0:0:0: CD-ROM PIONEER BD-RW BDR-207M 1.21 PQ: 0 ANSI: 5 Link: https://lore.kernel.org/r/YahpKVR+McJVDdkD@work Reported-by: Sam Bingner <sam@bingner.com> Tested-by: Sam Bingner <sam@bingner.com> Tested-by: Yifeng Li <tomli@tomli.me> Signed-off-by: Yifeng Li <tomli@tomli.me> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Wilczyński <kw@linux.com> Cc: stable@vger.kernel.org
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bb17b158 |
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18-Nov-2021 |
Kelvin Cao <kelvin.cao@microchip.com> |
PCI/switchtec: Add Gen4 automotive device IDs Advertise support of the Gen4 automotive variants in module's device ID table and add the same IDs to the list of switchtec quirks. Link: https://lore.kernel.org/r/20211119003803.2333-2-kelvin.cao@microchip.com Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
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0c9e032a |
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15-Nov-2021 |
Heikki Krogerus <heikki.krogerus@linux.intel.com> |
PCI: Convert to device_create_managed_software_node() In quirk_huawei_pcie_sva(), device_add_properties() is used to inject additional device properties, but there is no device_remove_properties() call anywhere to remove those properties. The assumption is most likely that the device is never removed, and the properties therefore do not also never need to be removed. Even though it is unlikely that the device is ever removed in this case, it is safer to make sure that the properties are also removed if the device ever does get unregistered. To achieve this, instead of adding a separate quirk for the case of device removal where device_remove_properties() is called, using device_create_managed_software_node() instead of device_add_properties(). Both functions create a software node (a type of fwnode) that holds the device properties, which is then assigned to the device very much the same way. The difference between the two functions is, that device_create_managed_software_node() guarantees that the software node (together with the properties) is removed when the device is removed. The function device_add_property() does not guarantee that, so the properties added with it should always be removed with device_remove_properties(). Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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f21082fb |
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04-Nov-2021 |
Marc Zyngier <maz@kernel.org> |
PCI: Add MSI masking quirk for Nvidia ION AHCI The ION AHCI device pretends that MSI masking isn't a thing, while it actually implements it and needs MSIs to be unmasked to work. Add a quirk to that effect. Reported-by: Rui Salvaterra <rsalvaterra@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Rui Salvaterra <rsalvaterra@gmail.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: Bjorn Helgaas <helgaas@kernel.org> Link: https://lore.kernel.org/r/CALjTZvbzYfBuLB+H=fj2J+9=DxjQ2Uqcy0if_PvmJ-nU-qEgkg@mail.gmail.com Link: https://lore.kernel.org/r/20211104180130.3825416-3-maz@kernel.org
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acd61ffb |
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09-Sep-2021 |
Nathan Rossi <nathan.rossi@digi.com> |
PCI: Add ACS quirk for Pericom PI7C9X2G switches The Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 PCIe switches have an erratum for ACS P2P Request Redirect behaviour when used in the cut-through forwarding mode. The recommended work around for this issue is to use the switch in store and forward mode. The erratum results in packets being queued and not being delivered upstream, which can be observed as very poor downstream device performance and/or dropped device-generated data/interrupts. Add a fixup so that when enabling or resuming the downstream port we check if it has enabled ACS P2P Request Redirect, and if so, change the device (via the upstream port) to use the store and forward operating mode. Link: https://bugzilla.kernel.org/show_bug.cgi?id=177471 Link: https://lore.kernel.org/r/20210910025823.196508-1-nathan@nathanrossi.com Tested-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Nathan Rossi <nathan.rossi@digi.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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fd1ae23b |
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12-Oct-2021 |
Krzysztof Wilczyński <kw@linux.com> |
PCI: Prefer 'unsigned int' over bare 'unsigned' The bare "unsigned" type implicitly means "unsigned int", but the preferred coding style is to use the complete type name. Update the bare use of "unsigned" to the preferred "unsigned int". No change to functionality intended. See a1ce18e4f941 ("checkpatch: warn on bare unsigned or signed declarations without int"). Link: https://lore.kernel.org/r/20211013014136.1117543-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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b2105b9f |
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06-Oct-2021 |
Krzysztof Wilczyński <kw@linux.com> |
PCI: Correct misspelled and remove duplicated words Correct a number of misspelled words and remove any words that were duplicated in the PCI tree. No change to functionality intended. Link: https://lore.kernel.org/r/20211006233827.147328-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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e3f4bd34 |
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09-Apr-2021 |
Ingmar Klein <ingmar_klein@web.de> |
PCI: Mark Atheros QCA6174 to avoid bus reset When passing the Atheros QCA6174 through to a virtual machine, the VM hangs at the point where the ath10k driver loads. Add a quirk to avoid bus resets on this device, which avoids the hang. [bhelgaas: commit log] Link: https://lore.kernel.org/r/08982e05-b6e8-5a8d-24ab-da1488ee50a8@web.de Signed-off-by: Ingmar Klein <ingmar_klein@web.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pali Rohár <pali@kernel.org> Cc: stable@vger.kernel.org
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60b78ed0 |
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03-Sep-2021 |
Evan Quan <evan.quan@amd.com> |
PCI: Add AMD GPU multi-function power dependencies Some AMD GPUs have built-in USB xHCI and USB Type-C UCSI controllers with power dependencies between the GPU and the other functions as in 6d2e369f0d4c ("PCI: Add NVIDIA GPU multi-function power dependencies"). Add device link support for the AMD integrated USB xHCI and USB Type-C UCSI controllers. Without this, runtime power management, including GPU resume and temp and fan sensors don't work correctly. Reported-at: https://gitlab.freedesktop.org/drm/amd/-/issues/1704 Link: https://lore.kernel.org/r/20210903063311.3606226-1-evan.quan@amd.com Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
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8304a3a1 |
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12-Jul-2021 |
Zhangfei Gao <zhangfei.gao@linaro.org> |
PCI: Set dma-can-stall for HiSilicon chips HiSilicon KunPeng920 and KunPeng930 have devices that appear as PCI but are actually on the AMBA bus. These fake PCI devices can support SVA via the SMMU stall feature. DT systems can indicate this in the device tree, but ACPI systems don't have that mechanism, so add a "dma-can-stall" property manually for them. [bhelgaas: add text from Robin as comment near quirk] Link: https://lore.kernel.org/r/1626144876-11352-4-git-send-email-zhangfei.gao@linaro.org Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Robin Murphy <robin.murphy@arm.com>
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8c09e896 |
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12-Jul-2021 |
Zhangfei Gao <zhangfei.gao@linaro.org> |
PCI: Allow PASID on fake PCIe devices without TLP prefixes Some systems, e.g., HiSilicon KunPeng920 and KunPeng930, have devices that appear as PCI but are actually on the AMBA bus. Some of these fake PCI devices support a PASID-like feature and they do have a working PASID capability even though they do not use the PCIe Transport Layer Protocol and do not support TLP prefixes. Add a pasid_no_tlp bit for this "PASID works without TLP prefixes" case and update pci_enable_pasid() so it can enable PASID on these devices. Set this bit for HiSilicon KunPeng920 and KunPeng930. [bhelgaas: squashed, commit log] Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/1626144876-11352-2-git-send-email-zhangfei.gao@linaro.org Link: https://lore.kernel.org/r/1626144876-11352-3-git-send-email-zhangfei.gao@linaro.org Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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7cae7849 |
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18-Jun-2021 |
Alex Williamson <alex.williamson@redhat.com> |
PCI/ACS: Enforce pci=noats with Transaction Blocking PCIe Address Translation Services (ATS) provides a mechanism for a device to provide an on-device caching translation agent (device IOTLB). We already have a means to disable support for this feature via the pci=noats option. For untrusted and externally facing devices, we not only disable ATS support for the device, but we use Access Control Services (ACS) Transaction Blocking to actively prevent devices from sending TLPs with non-default AT field values. Extend pci=noats to also make use of PCI_ACS_TB so that not only is ATS disabled at the device, but blocked at the downstream ports. This provides a means to further lock-down ATS for cases such as device assignment, where it may not be the hardware configuration of the device that makes it untrusted, but the driver running on the device. Link: https://lore.kernel.org/r/162404966325.2362347.12176138291577486015.stgit@omen Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rajat Jain <rajatja@google.com>
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#
32837d8a |
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10-Aug-2021 |
George Cherian <george.cherian@marvell.com> |
PCI: Add ACS quirks for Cavium multi-function devices Some Cavium endpoints are implemented as multi-function devices without ACS capability, but they actually don't support peer-to-peer transactions. Add ACS quirks to declare DMA isolation for the following devices: - BGX device found on Octeon-TX (8xxx) - CGX device found on Octeon-TX2 (9xxx) - RPM device found on Octeon-TX3 (10xxx) Link: https://lore.kernel.org/r/20210810122425.1115156-1-george.cherian@marvell.com Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
9bdc81ce |
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17-Aug-2021 |
Amey Narkhede <ameynarkhede03@gmail.com> |
PCI: Change the type of probe argument in reset functions Change the type of probe argument in functions which implement reset methods from int to bool to make the context and intent clear. Suggested-by: Alex Williamson <alex.williamson@redhat.com> Link: https://lore.kernel.org/r/20210817180500.1253-10-ameynarkhede03@gmail.com Signed-off-by: Amey Narkhede <ameynarkhede03@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
4ec36dfe |
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17-Aug-2021 |
Amey Narkhede <ameynarkhede03@gmail.com> |
PCI: Remove reset_fn field from pci_dev "reset_fn" indicates whether the device supports any reset mechanism. Remove the use of reset_fn in favor of the reset_methods array that tracks supported reset mechanisms of a device and their ordering. The octeon driver incorrectly used reset_fn to detect whether the device supports FLR or not. Use pcie_reset_flr() to probe whether it supports FLR. Co-developed-by: Alex Williamson <alex.williamson@redhat.com> Link: https://lore.kernel.org/r/20210817180500.1253-5-ameynarkhede03@gmail.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Amey Narkhede <ameynarkhede03@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
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#
56f107d7 |
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17-Aug-2021 |
Amey Narkhede <ameynarkhede03@gmail.com> |
PCI: Add pcie_reset_flr() with 'probe' argument Most reset methods are of the form "pci_*_reset(dev, probe)". pcie_flr() was an exception because it relied on a separate pcie_has_flr() function instead of taking a "probe" argument. Add "pcie_reset_flr(dev, probe)" to follow the convention. Remove pcie_has_flr(). Some pcie_flr() callers that did not use pcie_has_flr() remain. [bhelgaas: commit log, rework pcie_reset_flr() to use dev->devcap directly] Link: https://lore.kernel.org/r/20210817180500.1253-3-ameynarkhede03@gmail.com Signed-off-by: Amey Narkhede <ameynarkhede03@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
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d08c8b85 |
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29-Jul-2021 |
Wasim Khan <wasim.khan@nxp.com> |
PCI: Add ACS quirks for NXP LX2xx0 and LX2xx2 platforms Root Ports in NXP LX2xx0 and LX2xx2, where each Root Port is a Root Complex with unique segment numbers, do provide isolation features to disable peer transactions and validate bus numbers in requests, but do not provide an actual PCIe ACS capability. Add ACS quirks for NXP LX2xx0 A/C/E/N and LX2xx2 A/C/E/N platforms. LX2xx0A : without security features + CAN-FD LX2160A (0x8d81) - 16 cores LX2120A (0x8da1) - 12 cores LX2080A (0x8d83) - 8 cores LX2xx0C : security features + CAN-FD LX2160C (0x8d80) - 16 cores LX2120C (0x8da0) - 12 cores LX2080C (0x8d82) - 8 cores LX2xx0E : security features + CAN LX2160E (0x8d90) - 16 cores LX2120E (0x8db0) - 12 cores LX2080E (0x8d92) - 8 cores LX2xx0N : without security features + CAN LX2160N (0x8d91) - 16 cores LX2120N (0x8db1) - 12 cores LX2080N (0x8d93) - 8 cores LX2xx2A : without security features + CAN-FD LX2162A (0x8d89) - 16 cores LX2122A (0x8da9) - 12 cores LX2082A (0x8d8b) - 8 cores LX2xx2C : security features + CAN-FD LX2162C (0x8d88) - 16 cores LX2122C (0x8da8) - 12 cores LX2082C (0x8d8a) - 8 cores LX2xx2E : security features + CAN LX2162E (0x8d98) - 16 cores LX2122E (0x8db8) - 12 cores LX2082E (0x8d9a) - 8 cores LX2xx2N : without security features + CAN LX2162N (0x8d99) - 16 cores LX2122N (0x8db9) - 12 cores LX2082N (0x8d9b) - 8 cores [bhelgaas: put PCI_VENDOR_ID_NXP definition next to PCI_VENDOR_ID_FREESCALE as a clue that they share the same Device ID namespace] Link: https://lore.kernel.org/r/20210729121747.1823086-1-wasim.khan@oss.nxp.com Link: https://lore.kernel.org/r/20210803180021.3252886-1-wasim.khan@oss.nxp.com Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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b12d93e9 |
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24-Jun-2021 |
Marek Behún <kabel@kernel.org> |
PCI: Restrict ASMedia ASM1062 SATA Max Payload Size Supported The ASMedia ASM1062 SATA controller advertises Max_Payload_Size_Supported of 512, but in fact it cannot handle incoming TLPs with payload size of 512. We discovered this issue on PCIe controllers capable of MPS = 512 (Aardvark and DesignWare), where the issue presents itself as an External Abort. Bjorn Helgaas says: Probably ASM1062 reports a Malformed TLP error when it receives a data payload of 512 bytes, and Aardvark, DesignWare, etc convert this to an arm64 External Abort. [1] To avoid this problem, limit the ASM1062 Max Payload Size Supported to 256 bytes, so we set the Max Payload Size of devices that may send TLPs to the ASM1062 to 256 or less. [1] https://lore.kernel.org/linux-pci/20210601170907.GA1949035@bjorn-Precision-5520/ BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=212695 Link: https://lore.kernel.org/r/20210624171418.27194-2-kabel@kernel.org Reported-by: Rötti <espressobinboardarmbiantempmailaddress@posteo.de> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Wilczyński <kw@linux.com> Reviewed-by: Pali Rohár <pali@kernel.org> Cc: stable@vger.kernel.org
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b8da302e |
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24-Jun-2021 |
Marek Behún <kabel@kernel.org> |
PCI: Call Max Payload Size-related fixup quirks early pci_device_add() calls HEADER fixups after pci_configure_device(), which configures Max Payload Size. Convert MPS-related fixups to EARLY fixups so pci_configure_mps() takes them into account. Fixes: 27d868b5e6cfa ("PCI: Set MPS to match upstream bridge") Link: https://lore.kernel.org/r/20210624171418.27194-1-kabel@kernel.org Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
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e0bff432 |
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21-Jul-2021 |
Marcin Bachry <hegel666@gmail.com> |
PCI: Increase D3 delay for AMD Renoir/Cezanne XHCI The Renoir XHCI controller apparently doesn't resume reliably with the standard D3hot-to-D0 delay. Increase it to 20ms. [Alex: I talked to the AMD USB hardware team and the AMD Windows team and they are not aware of any HW errata or specific issues. The HW works fine in Windows. I was told Windows uses a rather generous default delay of 100ms for PCI state transitions.] Link: https://lore.kernel.org/r/20210722025858.220064-1-alexander.deucher@amd.com Signed-off-by: Marcin Bachry <hegel666@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Prike Liang <prike.liang@amd.com> Cc: Shyam Sundar S K <shyam-sundar.s-k@amd.com>
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4694ae37 |
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20-May-2021 |
Konstantin Kharlamov <Hi-Angel@yandex.ru> |
PCI: Leave Apple Thunderbolt controllers on for s2idle or standby On Macbook 2013, resuming from suspend-to-idle or standby resulted in the external monitor no longer being detected, a stacktrace, and errors like this in dmesg: pcieport 0000:06:00.0: can't change power state from D3hot to D0 (config space inaccessible) The reason is that we know how to turn power to the Thunderbolt controller *off* via the SXIO/SXFP/SXLF methods, but we don't know how to turn power back on. We have to rely on firmware to turn the power back on. When going to the "suspend-to-idle" or "standby" system sleep states, firmware is not involved either on the suspend side or the resume side, so we can't use SXIO/SXFP/SXLF to turn the power off. Skip SXIO/SXFP/SXLF when firmware isn't involved in suspend, e.g., when we're going to the "suspend-to-idle" or "standby" system sleep states. Fixes: 1df5172c5c25 ("PCI: Suspend/resume quirks for Apple thunderbolt") Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=212767 Link: https://lore.kernel.org/r/20210520235501.917397-1-Hi-Angel@yandex.ru Signed-off-by: Konstantin Kharlamov <Hi-Angel@yandex.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lukas Wunner <lukas@wunner.de> Cc: stable@vger.kernel.org
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#
411e2a43 |
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24-May-2021 |
Chiqijun <chiqijun@huawei.com> |
PCI: Work around Huawei Intelligent NIC VF FLR erratum pcie_flr() starts a Function Level Reset (FLR), waits 100ms (the maximum time allowed for FLR completion by PCIe r5.0, sec 6.6.2), and waits for the FLR to complete. It assumes the FLR is complete when a config read returns valid data. When we do an FLR on several Huawei Intelligent NIC VFs at the same time, firmware on the NIC processes them serially. The VF may respond to config reads before the firmware has completed its reset processing. If we bind a driver to the VF (e.g., by assigning the VF to a virtual machine) in the interval between the successful config read and completion of the firmware reset processing, the NIC VF driver may fail to load. Prevent this driver failure by waiting for the NIC firmware to complete its reset processing. Not all NIC firmware supports this feature. [bhelgaas: commit log] Link: https://support.huawei.com/enterprise/en/doc/EDOC1100063073/87950645/vm-oss-occasionally-fail-to-load-the-in200-driver-when-the-vf-performs-flr Link: https://lore.kernel.org/r/20210414132301.1793-1-chiqijun@huawei.com Signed-off-by: Chiqijun <chiqijun@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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#
db2f77e2 |
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21-May-2021 |
Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com> |
PCI: Add ACS quirk for Broadcom BCM57414 NIC The Broadcom BCM57414 NIC may be a multi-function device. While it does not advertise an ACS capability, peer-to-peer transactions are not possible between the individual functions, so it is safe to treat them as fully isolated. Add an ACS quirk for this device so the functions can be in independent IOMMU groups and attached individually to userspace applications using VFIO. [bhelgaas: commit log] Link: https://lore.kernel.org/r/1621645997-16251-1-git-send-email-michael.chan@broadcom.com Signed-off-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com> Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
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e8946a53 |
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01-Jun-2021 |
Evan Quan <evan.quan@amd.com> |
PCI: Mark AMD Navi14 GPU ATS as broken Observed unexpected GPU hang during runpm stress test on 0x7341 rev 0x00. Further debugging shows broken ATS is related. Disable ATS on this part. Similar issues on other devices: a2da5d8cc0b0 ("PCI: Mark AMD Raven iGPU ATS as broken in some platforms") 45beb31d3afb ("PCI: Mark AMD Navi10 GPU rev 0x00 ATS as broken") 5e89cd303e3a ("PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken") Suggested-by: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20210602021255.939090-1-evan.quan@amd.com Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Wilczyński <kw@linux.com> Cc: stable@vger.kernel.org
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ce00322c |
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24-May-2021 |
Chiqijun <chiqijun@huawei.com> |
PCI: Work around Huawei Intelligent NIC VF FLR erratum pcie_flr() starts a Function Level Reset (FLR), waits 100ms (the maximum time allowed for FLR completion by PCIe r5.0, sec 6.6.2), and waits for the FLR to complete. It assumes the FLR is complete when a config read returns valid data. When we do an FLR on several Huawei Intelligent NIC VFs at the same time, firmware on the NIC processes them serially. The VF may respond to config reads before the firmware has completed its reset processing. If we bind a driver to the VF (e.g., by assigning the VF to a virtual machine) in the interval between the successful config read and completion of the firmware reset processing, the NIC VF driver may fail to load. Prevent this driver failure by waiting for the NIC firmware to complete its reset processing. Not all NIC firmware supports this feature. [bhelgaas: commit log] Link: https://support.huawei.com/enterprise/en/doc/EDOC1100063073/87950645/vm-oss-occasionally-fail-to-load-the-in200-driver-when-the-vf-performs-flr Link: https://lore.kernel.org/r/20210414132301.1793-1-chiqijun@huawei.com Signed-off-by: Chiqijun <chiqijun@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Cc: stable@vger.kernel.org
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4c207e71 |
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07-Jun-2021 |
Shanker Donthineni <sdonthineni@nvidia.com> |
PCI: Mark some NVIDIA GPUs to avoid bus reset Some NVIDIA GPU devices do not work with SBR. Triggering SBR leaves the device inoperable for the current system boot. It requires a system hard-reboot to get the GPU device back to normal operating condition post-SBR. For the affected devices, enable NO_BUS_RESET quirk to avoid the issue. This issue will be fixed in the next generation of hardware. Link: https://lore.kernel.org/r/20210608054857.18963-8-ameynarkhede03@gmail.com Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Sinan Kaya <okaya@kernel.org> Cc: stable@vger.kernel.org
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b5cf198e |
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15-Mar-2021 |
Antti Järvinen <antti.jarvinen@gmail.com> |
PCI: Mark TI C667X to avoid bus reset Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS automatically disables LTSSM when Secondary Bus Reset is received and device stops working. Prevent bus reset for these devices. With this change, the device can be assigned to VMs with VFIO, but it will leak state between VMs. Reference: https://e2e.ti.com/support/processors/f/791/t/954382 Link: https://lore.kernel.org/r/20210315102606.17153-1-antti.jarvinen@gmail.com Signed-off-by: Antti Järvinen <antti.jarvinen@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Cc: stable@vger.kernel.org
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557853f4 |
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30-Mar-2021 |
Marc Zyngier <maz@kernel.org> |
PCI: Refactor HT advertising of NO_MSI flag The few quirks that deal with NO_MSI tend to be copy-paste heavy. Refactor them so that the hierarchy of conditions is slightly cleaner. Link: https://lore.kernel.org/r/20210330151145.997953-15-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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0349a070 |
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08-Apr-2021 |
Raphael Norwitz <raphael.norwitz@nutanix.com> |
PCI: Delay after FLR of Intel DC P4510 NVMe Like the Intel DC P3700 NVMe, the Intel P4510 NVMe exhibits a timeout failure when the driver tries to interact with the device too soon after an FLR. Add a device-specific reset method that delays 250ms after doing an FLR. Link: https://lore.kernel.org/r/20210408190521.16897-1-raphael.norwitz@nutanix.com Signed-off-by: Alay Shah <alay.shah@nutanix.com> Signed-off-by: Suresh Gumpula <suresh.gumpula@nutanix.com> Signed-off-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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d06a113f |
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29-Mar-2021 |
Heiner Kallweit <hkallweit1@gmail.com> |
IB/mthca: Disable parity reporting For Mellanox Tavor devices, we previously set dev->broken_parity_status, which does not change the device's behavior; it merely prevents the EDAC PCI error reporting from warning about Master Data Parity Error, Signaled System Error, or Detected Parity Error for this device. Instead, disable Parity Error Response so the device doesn't report parity errors in the first place. [bhelgaas: split out pci_disable_parity(), commit log, keep quirk static] Link: https://lore.kernel.org/r/20210330174318.1289680-3-helgaas@kernel.org Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
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05998379 |
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10-Nov-2020 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller Add function 1 DMA alias quirk for Marvell 88SS9215 PCIe SSD Controller. Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 Link: https://lore.kernel.org/r/20201110220516.697934-1-helgaas@kernel.org Reported-by: John Smith <LK7S2ED64JHGLKj75shg9klejHWG49h5hk@protonmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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a2da5d8c |
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10-Dec-2020 |
Alex Deucher <alexander.deucher@amd.com> |
PCI: Mark AMD Raven iGPU ATS as broken in some platforms Edgar reported [1] AMD Raven iGPU errors on several of his systems. There is no root cause. Turn off ATS on these systems to avoid the issue. [1] https://lore.kernel.org/linux-iommu/MWHPR10MB1310CDB6829DDCF5EA84A14689150@MWHPR10MB1310.namprd10.prod.outlook.com/ [bhelgaas: commit log] Link: https://lore.kernel.org/r/MWHPR10MB131082779A86BE4CCCF190B789CB0@MWHPR10MB1310.namprd10.prod.outlook.com Reported-by: Edgar Merger <Edgar.Merger@emerson.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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778f7c19 |
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13-Nov-2020 |
Jaehoon Chung <jh80.chung@samsung.com> |
PCI: dwc: exynos: Rework the driver to support Exynos5433 variant Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM: dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe variant found in the Exynos5433 SoCs. The main difference in Exynos5433 variant is lack of the MSI support (the MSI interrupt is not even routed to the CPU). [mszyprow: reworked the driver to support only Exynos5433 variant, simplified code, rebased onto current kernel code, added regulator support, converted to the regular platform driver, removed MSI related code, rewrote commit message, added help] Link: https://lore.kernel.org/r/20201113170139.29956-6-m.szyprowski@samsung.com Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Jingoo Han <jingoohan1@gmail.com>
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695cd09c |
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05-Nov-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
PCI: Use predefined Pericom Vendor ID Pericom has predefined Vendor ID, use it instead of hard-coded value. Link: https://lore.kernel.org/r/20201106100526.17726-2-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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f83c3794 |
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05-Nov-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
PCI: Disable MSI for Pericom PCIe-USB adapter Pericom PCIe-USB adapter advertises MSI, but documentation says "The MSI Function is not implemented on this device" in chapters 7.3.27, 7.3.29-7.3.31, and Alberto found that MSI in fact does not work. Disable MSI for these devices. Datasheet: https://www.diodes.com/assets/Datasheets/PI7C9X440SL.pdf Fixes: 306c54d0edb6 ("usb: hcd: Try MSI interrupts on PCI devices") Link: https://lore.kernel.org/linux-usb/20201030134826.GP4077@smile.fi.intel.com/ Link: https://lore.kernel.org/r/20201106100526.17726-1-andriy.shevchenko@linux.intel.com Reported-by: alberto.vignani@fastwebnet.it Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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3789af9a |
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30-Jul-2020 |
Krzysztof Wilczyński <kw@linux.com> |
PCI/PM: Rename pci_dev.d3_delay to d3hot_delay PCI devices support two variants of the D3 power state: D3hot (main power present) D3cold (main power removed). Previously struct pci_dev contained: unsigned int d3_delay; /* D3->D0 transition time in ms */ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ "d3_delay" refers specifically to the D3hot state. Rename it to "d3hot_delay" to avoid ambiguity and align with the ACPI "_DSM for Specifying Device Readiness Durations" in the PCI Firmware spec r3.2, sec 4.6.9. There is no change to the functionality. Link: https://lore.kernel.org/r/20200730210848.1578826-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
76fc8e85 |
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07-Jul-2020 |
Rajat Jain <rajatja@google.com> |
PCI/ACS: Enable Translation Blocking for external devices Translation Blocking is a required feature for Downstream Ports (Root Ports or Switch Downstream Ports) that implement ACS. When enabled, the Port checks the Address Type (AT) of each upstream Memory Request it receives. The default AT (00b) means "untranslated" and the IOMMU can decide whether to treat the address as I/O virtual or physical. If AT is not the default, i.e., if the Memory Request contains an already-translated (physical) address, the Port blocks the request and reports an ACS error. When enabling ACS, enable Translation Blocking for external-facing ports and untrusted (external) devices. This is to help prevent attacks from external devices that initiate DMA with physical addresses that bypass the IOMMU. [bhelgaas: commit log, simplify setting bit and drop warning; TB is required for Downstream Ports with ACS, so we should never see the warning] Link: https://lore.kernel.org/r/20200707224604.3737893-4-rajatja@google.com Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
2b9941e0 |
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19-May-2020 |
Mika Westerberg <mika.westerberg@linux.intel.com> |
PCI / thunderbolt: Switch to use device links instead of PCI quirk On older Apple systems there is currently a PCI quirk in place to block resume of tunneled PCIe ports until NHI (Thunderbolt controller) is resumed. This makes sure the PCIe tunnels are re-established before PCI core notices it. With device links the same thing can be done without quirks. The driver core will make sure the supplier (NHI) is resumed before consumers (PCIe downstream ports). For this reason switch the Thunderbolt driver to use device links and remove the PCI quirk. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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#
df561f66 |
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23-Aug-2020 |
Gustavo A. R. Silva <gustavoars@kernel.org> |
treewide: Use fallthrough pseudo-keyword Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case. [1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
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#
b361663c |
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21-Jul-2020 |
Robert Hancock <hancockrwd@gmail.com> |
PCI/ASPM: Disable ASPM on ASMedia ASM1083/1085 PCIe-to-PCI bridge Recently ASPM handling was changed to allow ASPM on PCIe-to-PCI/PCI-X bridges. Unfortunately the ASMedia ASM1083/1085 PCIe to PCI bridge device doesn't seem to function properly with ASPM enabled. On an Asus PRIME H270-PRO motherboard, it causes errors like these: pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) pcieport 0000:00:1c.0: AER: device [8086:a292] error status/mask=00003000/00002000 pcieport 0000:00:1c.0: AER: [12] Timeout pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0 pcieport 0000:00:1c.0: AER: can't find device of ID00e0 In addition to flooding the kernel log, this also causes the machine to wake up immediately after suspend is initiated. The device advertises ASPM L0s and L1 support in the Link Capabilities register, but the ASMedia web page for ASM1083 [1] claims "No PCIe ASPM support". Windows 10 (build 2004) enables L0s, but it also logs correctable PCIe errors. Add a quirk to disable ASPM for this device. [1] https://www.asmedia.com.tw/eng/e_show_products.php?cate_index=169&item=114 [bhelgaas: commit log] Fixes: 66ff14e59e8a ("PCI/ASPM: Allow ASPM on links to PCIe-to-PCI/PCI-X Bridges") Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=208667 Link: https://lore.kernel.org/r/20200722021803.17958-1-hancockrwd@gmail.com Signed-off-by: Robert Hancock <hancockrwd@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
090688fa |
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22-Jul-2020 |
Hanjun Guo <guohanjun@huawei.com> |
PCI: Release IVRS table in AMD ACS quirk The acpi_get_table() should be coupled with acpi_put_table() if the mapped table is not used at runtime to release the table mapping. In pci_quirk_amd_sb_acs(), IVRS table is just used for checking AMD IOMMU is supported, not used at runtime, so put the table after using it. Fixes: 15b100dfd1c9 ("PCI: Claim ACS support for AMD southbridge devices") Link: https://lore.kernel.org/r/1595411068-15440-1-git-send-email-guohanjun@huawei.com Signed-off-by: Hanjun Guo <guohanjun@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
45beb31d |
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28-Jul-2020 |
Kai-Heng Feng <kai.heng.feng@canonical.com> |
PCI: Mark AMD Navi10 GPU rev 0x00 ATS as broken We are seeing AMD Radeon Pro W5700 doesn't work when IOMMU is enabled: iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01a0] iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01c0] The error also makes graphics driver fail to probe the device. It appears to be the same issue as commit 5e89cd303e3a ("PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken") addresses, and indeed the same ATS quirk can workaround the issue. See-also: 5e89cd303e3a ("PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken") See-also: d28ca864c493 ("PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken") See-also: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken") Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=208725 Link: https://lore.kernel.org/r/20200728104554.28927-1-kai.heng.feng@canonical.com Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
52fbf5bd |
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07-Jul-2020 |
Rajat Jain <rajatja@google.com> |
PCI: Cache ACS capability offset in device Currently the ACS capability is being looked up at a number of places. Read and store it once at enumeration so that it can be used by all later. No functional change intended. Link: https://lore.kernel.org/r/20200707224604.3737893-2-rajatja@google.com Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
16bbbc87 |
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29-Jun-2020 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Replace lkml.org, spinics, gmane with lore.kernel.org The lkml.org, spinics.net, and gmane.org archives are not very reliable and, in some cases, not even easily accessible. Replace links to them with links to lore.kernel.org, the archives hosted by kernel.org. I found the gmane items via the Wayback Machine archive at https://web.archive.org/. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
7ecd4a81 |
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26-Jun-2020 |
Alexander A. Klimov <grandmaster@al2klimov.de> |
PCI: Replace http:// links with https:// Replace http:// links with https:// links. This reduces the likelihood of man-in-the-middle attacks when developers open these links. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. [bhelgaas: also update samsung.com links, drop sourceforge link] Link: https://lore.kernel.org/r/20200627103050.71712-1-grandmaster@al2klimov.de Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
3247bd10 |
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28-May-2020 |
Ashok Raj <ashok.raj@intel.com> |
PCI: Add ACS quirk for Intel Root Complex Integrated Endpoints All Intel platforms guarantee that all root complex implementations must send transactions up to IOMMU for address translations. Hence for Intel RCiEP devices, we can assume some ACS-type isolation even without an ACS capability. From the Intel VT-d spec, r3.1, sec 3.16 ("Root-Complex Peer to Peer Considerations"): When DMA remapping is enabled, peer-to-peer requests through the Root-Complex must be handled as follows: - The input address in the request is translated (through first-level, second-level or nested translation) to a host physical address (HPA). The address decoding for peer addresses must be done only on the translated HPA. Hardware implementations are free to further limit peer-to-peer accesses to specific host physical address regions (or to completely disallow peer-forwarding of translated requests). - Since address translation changes the contents (address field) of the PCI Express Transaction Layer Packet (TLP), for PCI Express peer-to-peer requests with ECRC, the Root-Complex hardware must use the new ECRC (re-computed with the translated address) if it decides to forward the TLP as a peer request. - Root-ports, and multi-function root-complex integrated endpoints, may support additional peer-to-peer control features by supporting PCI Express Access Control Services (ACS) capability. Refer to ACS capability in PCI Express specifications for details. Since Linux didn't give special treatment to allow this exception, certain RCiEP MFD devices were grouped in a single IOMMU group. This doesn't permit a single device to be assigned to a guest for instance. In one vendor system: Device 14.x were grouped in a single IOMMU group. /sys/kernel/iommu_groups/5/devices/0000:00:14.0 /sys/kernel/iommu_groups/5/devices/0000:00:14.2 /sys/kernel/iommu_groups/5/devices/0000:00:14.3 After this patch: /sys/kernel/iommu_groups/5/devices/0000:00:14.0 /sys/kernel/iommu_groups/5/devices/0000:00:14.2 /sys/kernel/iommu_groups/6/devices/0000:00:14.3 <<< new group 14.0 and 14.2 are integrated devices, but legacy end points, whereas 14.3 was a PCIe-compliant RCiEP. 00:14.3 Network controller: Intel Corporation Device 9df0 (rev 30) Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00 This permits assigning this device to a guest VM. [bhelgaas: drop "Fixes" tag since this doesn't fix a bug in that commit] Link: https://lore.kernel.org/r/1590699462-7131-1-git-send-email-ashok.raj@intel.com Tested-by: Darrel Goeddel <dgoeddel@forcepoint.com> Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Cc: stable@vger.kernel.org Cc: Lu Baolu <baolu.lu@linux.intel.com> Cc: Mark Scott <mscott@forcepoint.com>, Cc: Romil Sharma <rsharma@forcepoint.com>
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#
5727043c |
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24-May-2020 |
Kevin Buettner <kevinb@redhat.com> |
PCI: Avoid FLR for AMD Starship USB 3.0 The AMD Starship USB 3.0 host controller advertises Function Level Reset support, but it apparently doesn't work. Add a quirk to prevent use of FLR on this device. Without this quirk, when attempting to assign (pass through) an AMD Starship USB 3.0 host controller to a guest OS, the system becomes increasingly unresponsive over the course of several minutes, eventually requiring a hard reset. Shortly after attempting to start the guest, I see these messages: vfio-pci 0000:05:00.3: not ready 1023ms after FLR; waiting vfio-pci 0000:05:00.3: not ready 2047ms after FLR; waiting vfio-pci 0000:05:00.3: not ready 4095ms after FLR; waiting vfio-pci 0000:05:00.3: not ready 8191ms after FLR; waiting And then eventually: vfio-pci 0000:05:00.3: not ready 65535ms after FLR; giving up INFO: NMI handler (perf_event_nmi_handler) took too long to run: 0.000 msecs perf: interrupt took too long (642744 > 2500), lowering kernel.perf_event_max_sample_rate to 1000 INFO: NMI handler (perf_event_nmi_handler) took too long to run: 82.270 msecs INFO: NMI handler (perf_event_nmi_handler) took too long to run: 680.608 msecs INFO: NMI handler (perf_event_nmi_handler) took too long to run: 100.952 msecs ... watchdog: BUG: soft lockup - CPU#3 stuck for 22s! [qemu-system-x86:7487] Tested on a Micro-Star International Co., Ltd. MS-7C59/Creator TRX40 motherboard with an AMD Ryzen Threadripper 3970X. Link: https://lore.kernel.org/r/20200524003529.598434ff@f31-4.lan Signed-off-by: Kevin Buettner <kevinb@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
0d14f06c |
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20-May-2020 |
Marcos Scriven <marcos@scriven.org> |
PCI: Avoid FLR for AMD Matisse HD Audio & USB 3.0 The AMD Matisse HD Audio & USB 3.0 devices advertise Function Level Reset support, but hang when an FLR is triggered. To reproduce the problem, attach the device to a VM, then detach and try to attach again. Rename the existing quirk_intel_no_flr(), which was not Intel-specific, to quirk_no_flr(), and apply it to prevent the use of FLR on these AMD devices. Link: https://lore.kernel.org/r/CAAri2DpkcuQZYbT6XsALhx2e6vRqPHwtbjHYeiH7MNp4zmt1RA@mail.gmail.com Signed-off-by: Marcos Scriven <marcos@scriven.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
6ae72bfa |
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09-May-2020 |
Yicong Yang <yangyicong@hisilicon.com> |
PCI: Unify pcie_find_root_port() and pci_find_pcie_root_port() Previously we used pcie_find_root_port() to find a Root Port from a PCIe device and pci_find_pcie_root_port() to find a Root Port from a Conventional PCI device. Unify the two functions and use pcie_find_root_port() to find a Root Port from either a Conventional PCI device or a PCIe device. Then there is no need to distinguish the type of the device. Link: https://lore.kernel.org/r/1589019568-5216-1-git-send-email-yangyicong@hisilicon.com Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kalle Valo <kvalo@codeaurora.org> # wireless Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> # thunderbolt
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#
68f5fc4e |
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08-May-2020 |
Kai-Heng Feng <kai.heng.feng@canonical.com> |
PCI: Avoid Pericom USB controller OHCI/EHCI PME# defect Both Pericom OHCI and EHCI devices advertise PME# support from all power states: 06:00.0 USB controller [0c03]: Pericom Semiconductor PI7C9X442SL USB OHCI Controller [12d8:400e] (rev 01) (prog-if 10 [OHCI]) Subsystem: Pericom Semiconductor PI7C9X442SL USB OHCI Controller [12d8:400e] Capabilities: [80] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) 06:00.2 USB controller [0c03]: Pericom Semiconductor PI7C9X442SL USB EHCI Controller [12d8:400f] (rev 01) (prog-if 20 [EHCI]) Subsystem: Pericom Semiconductor PI7C9X442SL USB EHCI Controller [12d8:400f] Capabilities: [80] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) But testing shows that it's unreliable: there is a 20% chance PME# won't be asserted when a USB device is plugged. Remove PME support for both devices to make USB plugging work reliably. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=205981 Link: https://lore.kernel.org/r/20200508065343.32751-2-kai.heng.feng@canonical.com Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
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#
0a8f4102 |
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08-Apr-2020 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Move Apex Edge TPU class quirk to fix BAR assignment Some Google Apex Edge TPU devices have a class code of 0 (PCI_CLASS_NOT_DEFINED). This prevents the PCI core from assigning resources for the Apex BARs because __dev_sort_resources() ignores classless devices, host bridges, and IOAPICs. On x86, firmware typically assigns those resources, so this was not a problem. But on some architectures, firmware does *not* assign BARs, and since the PCI core didn't do it either, the Apex device didn't work correctly: apex 0000:01:00.0: can't enable device: BAR 0 [mem 0x00000000-0x00003fff 64bit pref] not claimed apex 0000:01:00.0: error enabling PCI device f390d08d8b87 ("staging: gasket: apex: fixup undefined PCI class") added a quirk to fix the class code, but it was in the apex driver, and if the driver was built as a module, it was too late to help. Move the quirk to the PCI core, where it will always run early enough that the PCI core will assign resources if necessary. Link: https://lore.kernel.org/r/CAEzXK1r0Er039iERnc2KJ4jn7ySNUOG9H=Ha8TD8XroVqiZjgg@mail.gmail.com Fixes: f390d08d8b87 ("staging: gasket: apex: fixup undefined PCI class") Reported-by: Luís Mendes <luis.p.mendes@gmail.com> Debugged-by: Luís Mendes <luis.p.mendes@gmail.com> Tested-by: Luis Mendes <luis.p.mendes@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Todd Poynor <toddpoynor@google.com>
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#
299bd044 |
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27-Mar-2020 |
Raymond Pang <RaymondPang-oc@zhaoxin.com> |
PCI: Add ACS quirk for Zhaoxin Root/Downstream Ports Many Zhaoxin Root Ports and Switch Downstream Ports do provide ACS-like capability but have no ACS Capability Structure. Peer-to-Peer transactions could be blocked between these ports, so add quirk so devices behind them could be assigned to different IOMMU group. Link: https://lore.kernel.org/r/20200327091148.5190-4-RaymondPang-oc@zhaoxin.com Signed-off-by: Raymond Pang <RaymondPang-oc@zhaoxin.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
0325837c |
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27-Mar-2020 |
Raymond Pang <RaymondPang-oc@zhaoxin.com> |
PCI: Add ACS quirk for Zhaoxin multi-function devices Some Zhaoxin endpoints are implemented as multi-function devices without an ACS capability, but they actually don't support peer-to-peer transactions. Add ACS quirks to declare DMA isolation. Link: https://lore.kernel.org/r/20200327091148.5190-3-RaymondPang-oc@zhaoxin.com Signed-off-by: Raymond Pang <RaymondPang-oc@zhaoxin.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
2880325b |
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19-Dec-2019 |
Kai-Heng Feng <kai.heng.feng@canonical.com> |
PCI: Avoid ASMedia XHCI USB PME# from D0 defect The ASMedia USB XHCI Controller claims to support generating PME# while in D0: 01:00.0 USB controller: ASMedia Technology Inc. Device 2142 (prog-if 30 [XHCI]) Subsystem: SUNIX Co., Ltd. Device 312b Capabilities: [78] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable+ DSel=0 DScale=0 PME- However PME# only gets asserted when plugging USB 2.0 or USB 1.1 devices, but not for USB 3.0 devices. Remove PCI_PM_CAP_PME_D0 to avoid using PME under D0. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=205919 Link: https://lore.kernel.org/r/20191219192006.16270-1-kai.heng.feng@canonical.com Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
b88bf6c3 |
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20-Feb-2020 |
Sean V Kelley <sean.v.kelley@linux.intel.com> |
PCI: Add boot interrupt quirk mechanism for Xeon chipsets The following was observed by Kar Hin Ong with RT patchset: Backtrace: irq 19: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 3329 Comm: irq/34-nipalk Tainted:4.14.87-rt49 #1 Hardware name: National Instruments NI PXIe-8880/NI PXIe-8880, BIOS 2.1.5f1 01/09/2020 Call Trace: <IRQ> ? dump_stack+0x46/0x5e ? __report_bad_irq+0x2e/0xb0 ? note_interrupt+0x242/0x290 ? nNIKAL100_memoryRead16+0x8/0x10 [nikal] ? handle_irq_event_percpu+0x55/0x70 ? handle_irq_event+0x4f/0x80 ? handle_fasteoi_irq+0x81/0x180 ? handle_irq+0x1c/0x30 ? do_IRQ+0x41/0xd0 ? common_interrupt+0x84/0x84 </IRQ> ... handlers: [<ffffffffb3297200>] irq_default_primary_handler threaded [<ffffffffb3669180>] usb_hcd_irq Disabling IRQ #19 The problem being that this device is triggering boot interrupts due to threaded interrupt handling and masking of the IO-APIC. These boot interrupts are then forwarded on to the legacy PCH's PIRQ lines where there is no handler present for the device. Whenever a PCI device fires interrupt (INTx) to Pin 20 of IOAPIC 2 (GSI 44), the kernel receives two interrupts: 1. Interrupt from Pin 20 of IOAPIC 2 -> Expected 2. Interrupt from Pin 19 of IOAPIC 1 -> UNEXPECTED Quirks for disabling boot interrupts (preferred) or rerouting the handler exist but do not address these Xeon chipsets' mechanism: https://lore.kernel.org/lkml/12131949181903-git-send-email-sassmann@suse.de/ Add a new mechanism via PCI CFG for those chipsets supporting CIPINTRC register's dis_intx_rout2ich bit. Link: https://lore.kernel.org/r/20200220192930.64820-2-sean.v.kelley@linux.intel.com Reported-by: Kar Hin Ong <kar.hin.ong@ni.com> Tested-by: Kar Hin Ong <kar.hin.ong@ni.com> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org
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#
5e89cd30 |
|
14-Jan-2020 |
Alex Deucher <alexander.deucher@amd.com> |
PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken To account for parts of the chip that are "harvested" (disabled) due to silicon flaws, caches on some AMD GPUs must be initialized before ATS is enabled. ATS is normally enabled by the IOMMU driver before the GPU driver loads, so this cache initialization would have to be done in a quirk, but that's too complex to be practical. For Navi14 (device ID 0x7340), this initialization is done by the VBIOS, but apparently some boards went to production with an older VBIOS that doesn't do it. Disable ATS for those boards. Link: https://lore.kernel.org/r/20200114205523.1054271-3-alexander.deucher@amd.com Bug: https://gitlab.freedesktop.org/drm/amd/issues/1015 See-also: d28ca864c493 ("PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken") See-also: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken") [bhelgaas: squash into one patch, simplify slightly, commit log] Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
|
#
7a30ebb9 |
|
14-Jan-2020 |
Kelvin Cao <kelvin.cao@microchip.com> |
PCI/switchtec: Add Gen4 device IDs Now that Gen4 is properly supported, advertise support in the module's device ID table and add the same IDs to the list of switchtec quirks. [logang@deltatee.com: add commit message and quirk IDs] Link: https://lore.kernel.org/r/20200115035648.2578-8-logang@deltatee.com Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
4bdc0d67 |
|
06-Jan-2020 |
Christoph Hellwig <hch@lst.de> |
remove ioremap_nocache and devm_ioremap_nocache ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
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#
7b90dfc4 |
|
10-Dec-2019 |
James Sewart <jamessewart@arista.com> |
PCI: Add DMA alias quirk for PLX PEX NTB The PLX PEX NTB forwards DMA transactions using Requester IDs that don't exist as PCI devices. The devfn for a transaction is used as an index into a lookup table storing the origin of a transaction on the other side of the bridge. Alias all possible devfns to the NTB device so that any transaction coming in is governed by the mappings for the NTB. Signed-off-by: James Sewart <jamessewart@arista.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
|
#
09298542 |
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10-Dec-2019 |
James Sewart <jamessewart@arista.com> |
PCI: Add nr_devfns parameter to pci_add_dma_alias() Add a "nr_devfns" parameter to pci_add_dma_alias() so it can be used to create DMA aliases for a range of devfns. [bhelgaas: incorporate nr_devfns fix from James, update quirk_pex_vca_alias() and setup_aliases()] Signed-off-by: James Sewart <jamessewart@arista.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
3030df20 |
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26-Nov-2019 |
Daniel Drake <drake@endlessm.com> |
PCI: Increase D3 delay for AMD Ryzen5/7 XHCI controllers On Asus UX434DA (AMD Ryzen7 3700U) and Asus X512DK (AMD Ryzen5 3500U), the XHCI controller fails to resume from runtime suspend or s2idle, and USB becomes unusable from that point. xhci_hcd 0000:03:00.4: Refused to change power state, currently in D3 xhci_hcd 0000:03:00.4: enabling device (0000 -> 0002) xhci_hcd 0000:03:00.4: WARN: xHC restore state timeout xhci_hcd 0000:03:00.4: PCI post-resume error -110! xhci_hcd 0000:03:00.4: HC died; cleaning up During suspend, a transition to D3cold is attempted, however the affected platforms do not seem to cut the power to the PCI device when in this state, so the device stays in D3hot. Upon resume, the D3hot-to-D0 transition is successful only if the D3 delay is increased to 20ms. The transition failure does not appear to be detectable as a CRS condition. Add a PCI quirk to increase the delay on the affected hardware. Link: https://bugzilla.kernel.org/show_bug.cgi?id=205587 Link: http://lkml.kernel.org/r/CAD8Lp47Vh69gQjROYG69=waJgL7hs1PwnLonL9+27S_TcRhixA@mail.gmail.com Link: https://lore.kernel.org/r/20191127053836.31624-2-drake@endlessm.com Signed-off-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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62fe23df |
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26-Nov-2019 |
Daniel Drake <drake@endlessm.com> |
PCI: Add generic quirk for increasing D3hot delay Separate the D3 delay increase functionality out of quirk_radeon_pm() into its own function so that it can be shared with other quirks, including the AMD Ryzen XHCI quirk that will be introduced in a followup commit. Tweak the function name and message to indicate more clearly that the delay relates to a D3hot-to-D0 transition. Link: https://lore.kernel.org/r/20191127053836.31624-1-drake@endlessm.com Signed-off-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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574f2903 |
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11-Dec-2019 |
Wei Liu <wei.liu@kernel.org> |
PCI: iproc: Apply quirk_paxc_bridge() for module as well as built-in Previously quirk_paxc_bridge() was applied when the iproc driver was built-in, but not when it was compiled as a module. This happened because it was under #ifdef CONFIG_PCIE_IPROC_PLATFORM: PCIE_IPROC_PLATFORM=y causes CONFIG_PCIE_IPROC_PLATFORM to be defined, but PCIE_IPROC_PLATFORM=m causes CONFIG_PCIE_IPROC_PLATFORM_MODULE to be defined. Move quirk_paxc_bridge() to pcie-iproc.c and drop the #ifdef so the quirk is always applied, whether iproc is built-in or a module. [bhelgaas: commit log, move to pcie-iproc.c, not pcie-iproc-platform.c] Link: https://lore.kernel.org/r/20191211174511.89713-1-wei.liu@kernel.org Signed-off-by: Wei Liu <wei.liu@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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9d09e5a9 |
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15-Oct-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Fix typos Fix typos in drivers/pci. Comment and whitespace changes only. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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7cf2cba4 |
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06-Sep-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Unify ACS quirk desired vs provided checking Most of the ACS quirks have a similar pattern of: acs_flags &= ~( <controls provided by this device> ); return acs_flags ? 0 : 1; Pull this out into a helper function to simplify the quirks slightly. The helper function is also a convenient place for comments about what the list of ACS controls means. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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c8de8ed2 |
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05-Sep-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Make ACS quirk implementations more uniform The ACS quirks differ in needless ways, which makes them look more different than they really are. Reorder the ACS flags in order of definitions in the spec: PCI_ACS_SV Source Validation PCI_ACS_TB Translation Blocking PCI_ACS_RR P2P Request Redirect PCI_ACS_CR P2P Completion Redirect PCI_ACS_UF Upstream Forwarding PCI_ACS_EC P2P Egress Control PCI_ACS_DT Direct Translated P2P (PCIe r5.0, sec 7.7.8.2) and use similar code structure in all. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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f338bb9f |
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10-Nov-2019 |
George Cherian <george.cherian@marvell.com> |
PCI: Apply Cavium ACS quirk to ThunderX2 and ThunderX3 Enhance the ACS quirk for Cavium Processors. Add the root port vendor IDs for ThunderX2 and ThunderX3 series of processors. [bhelgaas: add Fixes: and stable tag] Fixes: f2ddaf8dfd4a ("PCI: Apply Cavium ThunderX ACS quirk to more Root Ports") Link: https://lore.kernel.org/r/20191111024243.GA11408@dc5-eodlnx05.marvell.com Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Robert Richter <rrichter@marvell.com> Cc: stable@vger.kernel.org # v4.12+
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56b4cd4b |
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17-Sep-2019 |
Slawomir Pawlowski <slawomir.pawlowski@intel.com> |
PCI: Add DMA alias quirk for Intel VCA NTB Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). Similarly to MIC x200, we need to add DMA aliases to allow buffer access when IOMMU is enabled. Add aliases to allow computational unit access to host memory. These aliases mark the whole VCA device as one IOMMU group. All possible slot numbers (0x20) are used, since we are unable to tell what slot is used on other side. This quirk is intended for both host and computational unit sides. The VCA devices have up to five functions: four for DMA channels and one additional. Link: https://lore.kernel.org/r/5683A335CC8BE1438C3C30C49DCC38DF637CED8E@IRSMSX102.ger.corp.intel.com Signed-off-by: Slawomir Pawlowski <slawomir.pawlowski@intel.com> Signed-off-by: Przemek Kitszel <przemyslawx.kitszel@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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d8558ac8 |
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18-Sep-2019 |
Steffen Liebergeld <steffen.liebergeld@kernkonzept.com> |
PCI: Fix Intel ACS quirk UPDCR register address According to documentation [0] the correct offset for the Upstream Peer Decode Configuration Register (UPDCR) is 0x1014. It was previously defined as 0x1114. d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports") intended to enforce isolation between PCI devices allowing them to be put into separate IOMMU groups. Due to the wrong register offset the intended isolation was not fully enforced. This is fixed with this patch. Please note that I did not test this patch because I have no hardware that implements this register. [0] https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf (page 325) Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports") Link: https://lore.kernel.org/r/7a3505df-79ba-8a28-464c-88b83eefffa6@kernkonzept.com Signed-off-by: Steffen Liebergeld <steffen.liebergeld@kernkonzept.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Ashok Raj <ashok.raj@intel.com> Cc: stable@vger.kernel.org # v3.15+
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c9c13ba4 |
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27-Sep-2019 |
Denis Efremov <efremov@linux.com> |
PCI: Add PCI_STD_NUM_BARS for the number of standard BARs Code that iterates over all standard PCI BARs typically uses PCI_STD_RESOURCE_END. However, that requires the unusual test "i <= PCI_STD_RESOURCE_END" rather than something the typical "i < PCI_STD_NUM_BARS". Add a definition for PCI_STD_NUM_BARS and change loops to use the more idiomatic C style to help avoid fencepost errors. Link: https://lore.kernel.org/r/20190927234026.23342-1-efremov@linux.com Link: https://lore.kernel.org/r/20190927234308.23935-1-efremov@linux.com Link: https://lore.kernel.org/r/20190916204158.6889-3-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sebastian Ott <sebott@linux.ibm.com> # arch/s390/ Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> # video/fbdev/ Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> # pci/controller/dwc/ Acked-by: Jack Wang <jinpu.wang@cloud.ionos.com> # scsi/pm8001/ Acked-by: Martin K. Petersen <martin.petersen@oracle.com> # scsi/pm8001/ Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # memstick/
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738cb37b |
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12-Sep-2019 |
Jonathan Chocron <jonnyc@amazon.com> |
PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root Port The Root Port (identified by [1c36:0031]) doesn't support MSI-X. On some platforms it is configured to not advertise the capability at all, while on others it (mistakenly) does. This causes a panic during initialization by the pcieport driver, since it tries to configure the MSI-X capability. Specifically, when trying to access the MSI-X table a "non-existing addr" exception occurs. Example stacktrace snippet: SError Interrupt on CPU2, code 0xbf000000 -- SError CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33 Hardware name: Annapurna Labs Alpine V3 EVP (DT) pstate: 80000005 (Nzcv daif -PAN -UAO) pc : __pci_enable_msix_range+0x4e4/0x608 lr : __pci_enable_msix_range+0x498/0x608 sp : ffffff80117db700 x29: ffffff80117db700 x28: 0000000000000001 x27: 0000000000000001 x26: 0000000000000000 x25: ffffffd3e9d8c0b0 x24: 0000000000000000 x23: 0000000000000000 x22: 0000000000000000 x21: 0000000000000001 x20: 0000000000000000 x19: ffffffd3e9d8c000 x18: ffffffffffffffff x17: 0000000000000000 x16: 0000000000000000 x15: ffffff80116496c8 x14: ffffffd3e9844503 x13: ffffffd3e9844502 x12: 0000000000000038 x11: ffffffffffffff00 x10: 0000000000000040 x9 : ffffff801165e270 x8 : ffffff801165e268 x7 : 0000000000000002 x6 : 00000000000000b2 x5 : ffffffd3e9d8c2c0 x4 : 0000000000000000 x3 : 0000000000000000 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffffd3e9844680 Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33 Hardware name: Annapurna Labs Alpine V3 EVP (DT) Call trace: dump_backtrace+0x0/0x140 show_stack+0x14/0x20 dump_stack+0xa8/0xcc panic+0x140/0x334 nmi_panic+0x6c/0x70 arm64_serror_panic+0x74/0x88 __pte_error+0x0/0x28 el1_error+0x84/0xf8 __pci_enable_msix_range+0x4e4/0x608 pci_alloc_irq_vectors_affinity+0xdc/0x150 pcie_port_device_register+0x2b8/0x4e0 pcie_portdrv_probe+0x34/0xf0 Notice that this quirk also disables MSI (which may work, but hasn't been tested nor has a current use case), since currently there is no standard way to disable only MSI-X. Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
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76e67e9e |
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12-Sep-2019 |
Ali Saidi <alisaidi@amazon.com> |
PCI: Add ACS quirk for Amazon Annapurna Labs root ports The Amazon's Annapurna Labs root ports don't advertise an ACS capability, but they don't allow peer-to-peer transactions and do validate bus numbers through the SMMU. Additionally, it's not possible for one RP to pass traffic to another RP. Signed-off-by: Ali Saidi <alisaidi@amazon.com> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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46b2c32d |
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19-Aug-2019 |
Abhinav Ratna <abhinav.ratna@broadcom.com> |
PCI: Add ACS quirk for iProc PAXB iProc PAXB Root Ports don't advertise an ACS capability, but they do not allow peer-to-peer transactions between Root Ports. Add an ACS quirk so each Root Port can be in a separate IOMMU group. [bhelgaas: commit log, comment, use common implementation style] Link: https://lore.kernel.org/r/1566275985-25670-1-git-send-email-srinath.mannam@broadcom.com Signed-off-by: Abhinav Ratna <abhinav.ratna@broadcom.com> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Scott Branden <scott.branden@broadcom.com>
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7ce2e76a |
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27-Aug-2019 |
Krzysztof Wilczynski <kw@linux.com> |
PCI: Move ASPM declarations to linux/pci.h Move ASPM definitions and function prototypes from include/linux/pci-aspm.h to include/linux/pci.h so users only need to include <linux/pci.h>: PCIE_LINK_STATE_L0S PCIE_LINK_STATE_L1 PCIE_LINK_STATE_CLKPM pci_disable_link_state() pci_disable_link_state_locked() pcie_no_aspm() No functional changes intended. Link: https://lore.kernel.org/r/20190827095620.11213-1-kw@linux.com Signed-off-by: Krzysztof Wilczynski <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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ad54567a |
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01-Aug-2019 |
Lyude Paul <lyude@redhat.com> |
PCI: Reset both NVIDIA GPU and HDA in ThinkPad P50 workaround quirk_reset_lenovo_thinkpad_50_nvgpu() resets NVIDIA GPUs to work around an apparent BIOS defect. It previously used pci_reset_function(), and the available method was a bus reset, which was fine because there was only one function on the bus. After b516ea586d71 ("PCI: Enable NVIDIA HDA controllers"), there are now two functions (the HDA controller and the GPU itself) on the bus, so the reset fails. Use pci_reset_bus() explicitly instead of pci_reset_function() since it's OK to reset both devices. [bhelgaas: commit log, add e0547c81bfcf] Fixes: b516ea586d71 ("PCI: Enable NVIDIA HDA controllers") Fixes: e0547c81bfcf ("PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessary") Link: https://lore.kernel.org/r/20190801220117.14952-1-lyude@redhat.com Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ben Skeggs <bskeggs@redhat.com> Cc: Lukas Wunner <lukas@wunner.de> Cc: Daniel Drake <drake@endlessm.com> Cc: Aaron Plattner <aplattner@nvidia.com> Cc: Peter Wu <peter@lekensteyn.nl> Cc: Ilia Mirkin <imirkin@alum.mit.edu> Cc: Karol Herbst <kherbst@redhat.com> Cc: Maik Freudenberg <hhfeuer@gmx.de>
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8c7e96d3 |
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13-Aug-2019 |
Vidya Sagar <vidyas@nvidia.com> |
PCI: Disable MSI for Tegra root ports Tegra PCIe rootports don't generate MSI interrupts for PME and AER events. Since PCIe spec (Ref: r4.0 sec 7.7.1.2 and 7.7.2.2) doesn't support using a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root ports service drivers registering their respective ISRs with MSI interrupt and to let only INTx be used for all events. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
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b516ea58 |
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07-Jul-2019 |
Lukas Wunner <lukas@wunner.de> |
PCI: Enable NVIDIA HDA controllers Many NVIDIA GPUs can be configured as either a single-function video device or a multi-function device with video at function 0 and an HDA audio controller at function 1. The HDA controller can be enabled or disabled by a bit in the function 0 config space. Some BIOSes leave the HDA disabled, which means the HDMI connector from the NVIDIA GPU may not work. Sometimes the BIOS enables the HDA if an HDMI cable is connected at boot time, but that doesn't handle hotplug cases. Enable the HDA controller on device enumeration and resume and re-read the header type, which tells us whether the GPU is a multi-function device. This quirk is limited to NVIDIA PCI devices with the VGA Controller device class. This is expected to correspond to product configurations where the NVIDIA GPU has connectors attached. Other products where the device class is 3D Controller are expected to correspond to configurations where the NVIDIA GPU is dedicated (dGPU) and has no connectors. See original post (URL below) for more details. This commit takes inspiration from an earlier patch by Daniel Drake. Link: https://lore.kernel.org/r/20190708051744.24039-1-drake@endlessm.com v2 Link: https://lore.kernel.org/r/20190613063514.15317-1-drake@endlessm.com v1 Link: https://devtalk.nvidia.com/default/topic/1024022 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75985 Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Daniel Drake <drake@endlessm.com> [bhelgaas: commit log, log message, return early if already enabled] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Aaron Plattner <aplattner@nvidia.com> Cc: Peter Wu <peter@lekensteyn.nl> Cc: Ilia Mirkin <imirkin@alum.mit.edu> Cc: Karol Herbst <kherbst@redhat.com> Cc: Maik Freudenberg <hhfeuer@gmx.de>
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6d2e369f |
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06-Jun-2019 |
Abhishek Sahu <abhsahu@nvidia.com> |
PCI: Add NVIDIA GPU multi-function power dependencies The NVIDIA Turing GPU is a multi-function PCI device with the following functions: - Function 0: VGA display controller - Function 1: Audio controller - Function 2: USB xHCI Host controller - Function 3: USB Type-C UCSI controller Function 0 is tightly coupled with other functions in the hardware. When function 0 is in D3, it gates power for hardware blocks used by other functions, which means those functions only work when function 0 is in D0. If any of these functions (1/2/3) are in D0, then function 0 should also be in D0. Commit 07f4f97d7b4b ("vga_switcheroo: Use device link for HDA controller") already creates a device link to show the dependency of function 1 on function 0 of this GPU. Create additional device links to express the dependencies of functions 2 and 3 on function 0. This means function 0 will be in D0 if any other function is in D0. [bhelgaas: I think the PCI spec expectation is that functions can be power-managed independently, so I don't think this device is technically compliant. For example, the PCIe r5.0 spec, sec 1.4, says "the PCI/PCIe hardware/software model includes architectural constructs necessary to discover, configure, and use a Function, without needing Function-specific knowledge" and sec 5.1 says "D states are associated with a particular Function" and "PM provides ... a mechanism to identify power management capabilities of a given Function [and] the ability to transition a Function into a certain power management state."] Link: https://lore.kernel.org/lkml/20190606092225.17960-3-abhsahu@nvidia.com Signed-off-by: Abhishek Sahu <abhsahu@nvidia.com> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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a17beb1a |
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06-Jun-2019 |
Abhishek Sahu <abhsahu@nvidia.com> |
PCI: Generalize multi-function power dependency device links Although not allowed by the PCI specs, some multi-function devices have power dependencies between the functions. For example, function 1 may not work unless function 0 is in the D0 power state. The existing quirk_gpu_hda() adds a device link to express this dependency for GPU and HDA devices, but it really is not specific to those device types. Generalize it and rename it to pci_create_device_link() so we can create dependencies between any "consumer" and "producer" functions of a multi-function device, where the consumer is only functional if the producer is in D0. This reorganization should not affect any functionality. Link: https://lore.kernel.org/lkml/20190606092225.17960-2-abhsahu@nvidia.com Signed-off-by: Abhishek Sahu <abhsahu@nvidia.com> [bhelgaas: commit log, reword diagnostic] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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34c6b710 |
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19-Apr-2019 |
Mohan Kumar <mohankumar718@gmail.com> |
PCI: Replace dev_printk(KERN_DEBUG) with dev_info(), etc Replace dev_printk(KERN_DEBUG) with dev_info(), etc to be more consistent with other logging and avoid checkpatch warnings. The KERN_DEBUG messages could be converted to dev_dbg(), but that depends on CONFIG_DYNAMIC_DEBUG and DEBUG, and we want most of these messages to *always* be in the dmesg log. Link: https://lore.kernel.org/lkml/1555733240-19875-1-git-send-email-mohankumar718@gmail.com Signed-off-by: Mohan Kumar <mohankumar718@gmail.com> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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25da8dba |
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19-Apr-2019 |
Mohan Kumar <mohankumar718@gmail.com> |
PCI: Replace printk(KERN_INFO) with pr_info(), etc Replace printk() with pr_*() to be more consistent with other logging and avoid checkpatch warnings. Link: https://lore.kernel.org/lkml/1555733026-19609-1-git-send-email-mohankumar718@gmail.com Link: https://lore.kernel.org/lkml/1555733130-19804-1-git-send-email-mohankumar718@gmail.com Signed-off-by: Mohan Kumar <mohankumar718@gmail.com> [bhelgaas: squash in similar changes from second patch in series] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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7db4af43 |
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07-May-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Use dev_printk() when possible Use dev_printk() when possible. This makes messages more consistent with other device-related messages and, in some cases, adds useful information. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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e0547c81 |
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12-Feb-2019 |
Lyude Paul <lyude@redhat.com> |
PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessary On ThinkPad P50 SKUs with an Nvidia Quadro M1000M instead of the M2000M variant, the BIOS does not always reset the secondary Nvidia GPU during reboot if the laptop is configured in Hybrid Graphics mode. The reason is unknown, but the following steps and possibly a good bit of patience will reproduce the issue: 1. Boot up the laptop normally in Hybrid Graphics mode 2. Make sure nouveau is loaded and that the GPU is awake 3. Allow the Nvidia GPU to runtime suspend itself after being idle 4. Reboot the machine, the more sudden the better (e.g. sysrq-b may help) 5. If nouveau loads up properly, reboot the machine again and go back to step 2 until you reproduce the issue This results in some very strange behavior: the GPU will be left in exactly the same state it was in when the previously booted kernel started the reboot. This has all sorts of bad side effects: for starters, this completely breaks nouveau starting with a mysterious EVO channel failure that happens well before we've actually used the EVO channel for anything: nouveau 0000:01:00.0: disp: chid 0 mthd 0000 data 00000400 00001000 00000002 This causes a timeout trying to bring up the GR ctx: nouveau 0000:01:00.0: timeout WARNING: CPU: 0 PID: 12 at drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c:1547 gf100_grctx_generate+0x7b2/0x850 [nouveau] Hardware name: LENOVO 20EQS64N0B/20EQS64N0B, BIOS N1EET82W (1.55 ) 12/18/2018 Workqueue: events_long drm_dp_mst_link_probe_work [drm_kms_helper] ... nouveau 0000:01:00.0: gr: wait for idle timeout (en: 1, ctxsw: 0, busy: 1) nouveau 0000:01:00.0: gr: wait for idle timeout (en: 1, ctxsw: 0, busy: 1) nouveau 0000:01:00.0: fifo: fault 01 [WRITE] at 0000000000008000 engine 00 [GR] client 15 [HUB/SCC_NB] reason c4 [] on channel -1 [0000000000 unknown] The GPU never manages to recover. Booting without loading nouveau causes issues as well, since the GPU starts sending spurious interrupts that cause other device's IRQs to get disabled by the kernel: irq 16: nobody cared (try booting with the "irqpoll" option) ... handlers: [<000000007faa9e99>] i801_isr [i2c_i801] Disabling IRQ #16 ... serio: RMI4 PS/2 pass-through port at rmi4-00.fn03 i801_smbus 0000:00:1f.4: Timeout waiting for interrupt! i801_smbus 0000:00:1f.4: Transaction timeout rmi4_f03 rmi4-00.fn03: rmi_f03_pt_write: Failed to write to F03 TX register (-110). i801_smbus 0000:00:1f.4: Timeout waiting for interrupt! i801_smbus 0000:00:1f.4: Transaction timeout rmi4_physical rmi4-00: rmi_driver_set_irq_bits: Failed to change enabled interrupts! This causes the touchpad and sometimes other things to get disabled. Since this happens without nouveau, we can't fix this problem from nouveau itself. Add a PCI quirk for the specific P50 variant of this GPU. Make sure the GPU is advertising NoReset- so we don't reset the GPU when the machine is in Dedicated graphics mode (where the GPU being initialized by the BIOS is normal and expected). Map the GPU MMIO space and read the magic 0x2240c register, which will have bit 1 set if the device was POSTed during a previous boot. Once we've confirmed all of this, reset the GPU and re-disable it - bringing it back to a healthy state. Link: https://bugzilla.kernel.org/show_bug.cgi?id=203003 Link: https://lore.kernel.org/lkml/20190212220230.1568-1-lyude@redhat.com Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: nouveau@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: Karol Herbst <kherbst@redhat.com> Cc: Ben Skeggs <skeggsb@gmail.com> Cc: stable@vger.kernel.org
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#
6afb7e26 |
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07-Jan-2019 |
James Prestwood <james.prestwood@linux.intel.com> |
PCI: Mark Atheros AR9462 to avoid bus reset When using PCI passthrough with this device, the host machine locks up completely when starting the VM, requiring a hard reboot. Add a quirk to avoid bus resets on this device. Fixes: c3e59ee4e766 ("PCI: Mark Atheros AR93xx to avoid bus reset") Link: https://lore.kernel.org/linux-pci/20190107213248.3034-1-james.prestwood@linux.intel.com Signed-off-by: James Prestwood <james.prestwood@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.14+
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#
d28ca864 |
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08-Apr-2019 |
Nikolai Kostrigin <nickel@altlinux.org> |
PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken ATS is broken on the Radeon R7 GPU (at least for Stoney Ridge based laptop) and causes IOMMU stalls and system failure. Disable ATS on these devices to make them usable again with IOMMU enabled. Thanks to Joerg Roedel <jroedel@suse.de> for help. [bhelgaas: In the email thread mentioned below, Alex suspects the real problem is in sbios or iommu, so it may affect only certain systems, and it may affect other devices in those systems as well. However, per Joerg we lack the ability to debug further, so this quirk is the best we can do for now.] Link: https://bugzilla.kernel.org/show_bug.cgi?id=194521 Link: https://lore.kernel.org/lkml/20190408103725.30426-1-nickel@altlinux.org Fixes: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken") Signed-off-by: Nikolai Kostrigin <nickel@altlinux.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joerg Roedel <jroedel@suse.de> CC: stable@vger.kernel.org
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#
d75f773c |
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25-Mar-2019 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
treewide: Switch printk users from %pf and %pF to %ps and %pS, respectively %pF and %pf are functionally equivalent to %pS and %ps conversion specifiers. The former are deprecated, therefore switch the current users to use the preferred variant. The changes have been produced by the following command: git grep -l '%p[fF]' | grep -v '^\(tools\|Documentation\)/' | \ while read i; do perl -i -pe 's/%pf/%ps/g; s/%pF/%pS/g;' $i; done And verifying the result. Link: http://lkml.kernel.org/r/20190325193229.23390-1-sakari.ailus@linux.intel.com Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: sparclinux@vger.kernel.org Cc: linux-um@lists.infradead.org Cc: xen-devel@lists.xenproject.org Cc: linux-acpi@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: drbd-dev@lists.linbit.com Cc: linux-block@vger.kernel.org Cc: linux-mmc@vger.kernel.org Cc: linux-nvdimm@lists.01.org Cc: linux-pci@vger.kernel.org Cc: linux-scsi@vger.kernel.org Cc: linux-btrfs@vger.kernel.org Cc: linux-f2fs-devel@lists.sourceforge.net Cc: linux-mm@kvack.org Cc: ceph-devel@vger.kernel.org Cc: netdev@vger.kernel.org Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Acked-by: David Sterba <dsterba@suse.com> (for btrfs) Acked-by: Mike Rapoport <rppt@linux.ibm.com> (for mm/memblock.c) Acked-by: Bjorn Helgaas <bhelgaas@google.com> (for drivers/pci) Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Petr Mladek <pmladek@suse.com>
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#
4ec73791 |
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29-Mar-2019 |
Stefan Mätje <stefan.maetje@esd.eu> |
PCI: Work around Pericom PCIe-to-PCI bridge Retrain Link erratum Due to an erratum in some Pericom PCIe-to-PCI bridges in reverse mode (conventional PCI on primary side, PCIe on downstream side), the Retrain Link bit needs to be cleared manually to allow the link training to complete successfully. If it is not cleared manually, the link training is continuously restarted and no devices below the PCI-to-PCIe bridge can be accessed. That means drivers for devices below the bridge will be loaded but won't work and may even crash because the driver is only reading 0xffff. See the Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf for details. Devices known as affected so far are: PI7C9X110, PI7C9X111SL, PI7C9X130. Add a new flag, clear_retrain_link, in struct pci_dev. Quirks for affected devices set this bit. Note that pcie_retrain_link() lives in aspm.c because that's currently the only place we use it, but this erratum is not specific to ASPM, and we may retrain links for other reasons in the future. Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu> [bhelgaas: apply regardless of CONFIG_PCIEASPM] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> CC: stable@vger.kernel.org
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#
9cde402a |
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05-Apr-2019 |
Andre Przywara <andre.przywara@arm.com> |
PCI: Add function 1 DMA alias quirk for Marvell 9170 SATA controller There is a Marvell 88SE9170 PCIe SATA controller I found on a board here. Some quick testing with the ARM SMMU enabled reveals that it suffers from the same requester ID mixup problems as the other Marvell chips listed already. Add the PCI vendor/device ID to the list of chips which need the workaround. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org
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#
f57a98e1 |
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06-Feb-2019 |
Thinh Nguyen <thinh.nguyen@synopsys.com> |
PCI: Work around Synopsys duplicate Device ID (HAPS USB3, NXP i.MX) There are at least four different parts with the same Vendor and Device ID ([16c3:abcd]): 1) Synopsys HAPS USB3 controller 2) Synopsys PCIe Root Port in Freescale/NXP i.MX6Q (reported by Lucas) 3) Synopsys PCIe Root Port in Freescale/NXP i.MX6QP (reported by Lukas) 4) Synopsys PCIe Root Port in Freescale/NXP i.MX7D (reported by Trent) The HAPS USB3 controller has a Class Code of PCI_CLASS_SERIAL_USB_XHCI, which means the XHCI driver would normally claim it. Previously, quirk_synopsys_haps() changed the Class Code of all [16c3:abcd] devices, including the Root Ports, to PCI_CLASS_SERIAL_USB_DEVICE to prevent the XHCI driver from claiming them so dwc3-haps can claim them instead. Changing the Class Code of the Root Ports prevents the PCI core from handling them as bridges, so devices below them don't work. Restrict the quirk so it only changes the Class Code for devices that start with the PCI_CLASS_SERIAL_USB_XHCI Class Code, leaving the Root Ports alone. Fixes: 03e6742584af ("PCI: Override Synopsys USB 3.x HAPS device class") Reported-by: Lukas F. Hartmann <lukas@mntmn.com> Reported-by: Trent Piepho <tpiepho@impinj.com> Reported-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
01926f6b |
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01-Feb-2019 |
Shunyong Yang <shunyong.yang@hxt-semitech.com> |
PCI: Add ACS quirk for HXT SD4800 The design of HXT SD4800 ACS feature is the same as QCOM QDF2xxx. Add an ACS quirk for the SD4800. Signed-off-by: Shunyong Yang <shunyong.yang@hxt-semitech.com> [bhelgaas: split to separate patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Sinan Kaya <okaya@kernel.org> CC: Joey Zheng <yu.zheng@hxt-semitech.com>
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#
1d09d577 |
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14-Jan-2019 |
Mathieu Malaterre <malat@debian.org> |
PCI: Mark expected switch fall-through There is a plan to build the kernel with -Wimplicit-fallthrough and these places in the code produced warnings (W=1). Fix them up. Signed-off-by: Mathieu Malaterre <malat@debian.org> [bhelgaas: squash into one patch, drop extra changelog detail] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
03e67425 |
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10-Dec-2018 |
Thinh Nguyen <thinh.nguyen@synopsys.com> |
PCI: Override Synopsys USB 3.x HAPS device class Synopsys USB 3.x host HAPS platform has a class code of PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these devices should use dwc3-haps driver. Change these devices' class code to PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming them. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
742bbe1e |
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05-Oct-2018 |
Logan Gunthorpe <logang@deltatee.com> |
PCI: Fix Switchtec DMA aliasing quirk dmesg noise Currently the Switchtec quirk runs on all endpoints in the switch, including all the upstream and downstream ports. These other functions do not contain BARs, so the quirk fails when trying to map the BAR and prints the error "Cannot iomap Switchtec device". The user will see a few of these useless and scary errors, one for each port in the switch. At most, the quirk should only run on either a management endpoint (PCI_CLASS_MEMORY_OTHER) or an NTB endpoint (PCI_CLASS_BRIDGE_OTHER). However, the quirk is useless except in NTB applications, so we will only run it when the class is PCI_CLASS_BRIDGE_OTHER. Switch to using DECLARE_PCI_FIXUP_CLASS_FINAL and only match PCI_CLASS_BRIDGE_OTHER. Reported-by: Stephen Bates <sbates@raithlin.com> Fixes: ad281ecf1c7d ("PCI: Add DMA alias quirk for Microsemi Switchtec NTB") Signed-off-by: Logan Gunthorpe <logang@deltatee.com> [bhelgaas: split SWITCHTEC_QUIRK() introduction to separate patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Doug Meyer <dmeyer@gigaio.com> Cc: Kurt Schwemmer <kurt.schwemmer@microsemi.com>
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#
01d5d7fa |
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10-Oct-2018 |
Logan Gunthorpe <logang@deltatee.com> |
PCI: Add macro for Switchtec quirk declarations Add SWITCHTEC_QUIRK() to reduce redundancy in declaring devices that use quirk_switchtec_ntb_dma_alias(). By itself, this is no functional change, but a subsequent patch updates SWITCHTEC_QUIRK() to fix ad281ecf1c7d ("PCI: Add DMA alias quirk for Microsemi Switchtec NTB"). Fixes: ad281ecf1c7d ("PCI: Add DMA alias quirk for Microsemi Switchtec NTB") Signed-off-by: Logan Gunthorpe <logang@deltatee.com> [bhelgaas: split to separate patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
d0c9606b |
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26-Sep-2018 |
Bin Meng <bmeng.cn@gmail.com> |
PCI: Add Device IDs for Intel GPU "spurious interrupt" quirk Add Device IDs to the Intel GPU "spurious interrupt" quirk table. For these devices, unplugging the VGA cable and plugging it in again causes spurious interrupts from the IGD. Linux eventually disables the interrupt, but of course that disables any other devices sharing the interrupt. The theory is that this is a VGA BIOS defect: it should have disabled the IGD interrupt but failed to do so. See f67fd55fa96f ("PCI: Add quirk for still enabled interrupts on Intel Sandy Bridge GPUs") and 7c82126a94e6 ("PCI: Add new ID for Intel GPU "spurious interrupt" quirk") for some history. [bhelgaas: See link below for discussion about how to fix this more generically instead of adding device IDs for every new Intel GPU. I hope this is the last patch to add device IDs.] Link: https://lore.kernel.org/linux-pci/1537974841-29928-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Bin Meng <bmeng.cn@gmail.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v3.4+
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#
5f0ecb27 |
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11-Sep-2018 |
Joshua Abraham <j.abraham1776@gmail.com> |
PCI: Remove set but unused variable Remove a set but unused variable in quirks.c. Fixes warning: variable ‘mmio_sys_info’ set but not used [-Wunused-but-set-variable] Signed-off-by: Joshua Abraham <j.abraham1776@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
50ca031b |
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05-Sep-2018 |
Mika Westerberg <mika.westerberg@linux.intel.com> |
Revert "PCI: Add ACS quirk for Intel 300 series" This reverts f154a718e6cc ("PCI: Add ACS quirk for Intel 300 series"). It turns out that erratum "PCH PCIe* Controller Root Port (ACSCTLR) Appear As Read Only" has been fixed in 300 series chipsets, even though the datasheet [1] claims otherwise. To make ACS work properly on 300 series root ports, revert the faulty commit. [1] https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/300-series-c240-series-chipset-pch-spec-update.pdf Fixes: f154a718e6cc ("PCI: Add ACS quirk for Intel 300 series") Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v4.18+
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#
c9d8b55f |
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21-Aug-2018 |
Ard Biesheuvel <ardb@kernel.org> |
PCI: Add support for relative addressing in quirk tables Allow the PCI quirk tables to be emitted in a way that avoids absolute references to the hook functions. This reduces the size of the entries, and, more importantly, makes them invariant under runtime relocation (e.g., for KASLR) Link: http://lkml.kernel.org/r/20180704083651.24360-6-ard.biesheuvel@linaro.org Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michael Ellerman <mpe@ellerman.id.au> Acked-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: James Morris <james.morris@microsoft.com> Cc: James Morris <jmorris@namei.org> Cc: Jessica Yu <jeyu@kernel.org> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Kees Cook <keescook@chromium.org> Cc: Nicolas Pitre <nico@linaro.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Petr Mladek <pmladek@suse.com> Cc: Russell King <linux@armlinux.org.uk> Cc: "Serge E. Hallyn" <serge@hallyn.com> Cc: Sergey Senozhatsky <sergey.senozhatsky@gmail.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Thomas Garnier <thgarnie@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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2538fb89 |
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14-Aug-2018 |
Jakub Kicinski <kuba@kernel.org> |
PCI: Limit config space size for Netronome NFP5000 Like the NFP4000 and NFP6000, the NFP5000 as an erratum where reading/ writing to PCI config space addresses above 0x600 can cause the NFP to generate PCIe completion timeouts. Limit the NFP5000's PF's config space size to 0x600 bytes as is already done for the NFP4000 and NFP6000. The NFP5000's VF is 0x6003 (PCI_DEVICE_ID_NETRONOME_NFP6000_VF), the same device ID as the NFP6000's VF. Thus, its config space is already limited by the existing use of quirk_nfp6000(). Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tony Egan <tony.egan@netronome.com>
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#
7695e73f |
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13-Aug-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add function 1 DMA alias quirk for Marvell 88SS9183 Add function 1 DMA alias quirk for Marvell 88SS9183 PCIe SSD Controller. Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 Reported-and-tested-by: Felix Blüthner <f.bluethner@mailbox.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
10dbc9fe |
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09-Aug-2018 |
Logan Gunthorpe <logang@deltatee.com> |
PCI: Add ACS Redirect disable quirk for Intel Sunrise Point Intel Sunrise Point PCH hardware has an implementation of the ACS bits that does not comply with the PCIe standard. Add a device-specific quirk, pci_quirk_disable_intel_spt_pch_acs_redir() to disable ACS Redirection on this system. Signed-off-by: Logan Gunthorpe <logang@deltatee.com> [bhelgaas: changelog, split to separate patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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#
73c47dde |
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09-Aug-2018 |
Logan Gunthorpe <logang@deltatee.com> |
PCI: Add device-specific ACS Redirect disable infrastructure Intel Sunrise Point (SPT) PCH hardware has an implementation of the ACS bits that does not comply with the PCIe standard. To deal with this we need device-specific quirks to disable ACS redirection. Add a new pci_dev_specific_disable_acs_redir() quirk and a new .disable_acs_redir() function pointer for use by non-compliant devices. No functional change intended. Signed-off-by: Logan Gunthorpe <logang@deltatee.com> [bhelgaas: split to separate patch, move pci_dev_specific_disable_acs_redir() declarations to drivers/pci/pci.h] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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#
3b269185 |
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09-Aug-2018 |
Logan Gunthorpe <logang@deltatee.com> |
PCI: Convert device-specific ACS quirks from NULL termination to ARRAY_SIZE Convert the search for device-specific ACS enable quirks from searching a NULL-terminated array to iterating through the array, which is always fixed-size anyway. No functional change intended. Signed-off-by: Logan Gunthorpe <logang@deltatee.com> [bhelgaas: changelog, split to separate patch for reviewability] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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#
51ba0945 |
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09-Aug-2018 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Delay after FLR of Intel DC P3700 NVMe Add a device-specific reset for Intel DC P3700 NVMe device which exhibits a timeout failure in drivers waiting for the ready status to update after NVMe enable if the driver interacts with the device too soon after FLR. As this has been observed in device assignment scenarios, resolve this with a device-specific reset quirk to add an additional, heuristically determined, delay after the FLR completes. Link: https://bugzilla.redhat.com/show_bug.cgi?id=1592654 Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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ffb08634 |
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09-Aug-2018 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Disable Samsung SM961/PM961 NVMe before FLR The Samsung SM961/PM961 (960 EVO) sometimes fails to return from FLR with the PCI config space reading back as -1. A reproducible instance of this behavior is resolved by clearing the enable bit in the NVMe configuration register and waiting for the ready status to clear (disabling the NVMe controller) prior to FLR. Link: https://bugzilla.redhat.com/show_bug.cgi?id=1542494 Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
b95e2cd0 |
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11-Jun-2018 |
Ray Jui <ray.jui@broadcom.com> |
PCI: iproc: Activate PAXC bridge quirk for more devices Activate PAXC bridge quirk for more PAXC based PCIe root complex with the following PCIe device ID: 0xd750, 0xd802, 0xd804 Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Oza Pawandeep <poza@codeaurora.org> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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#
d6488ac1 |
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05-Jul-2018 |
Gustavo A. R. Silva <gustavo@embeddedor.com> |
PCI: Mark fall-through switch cases before enabling -Wimplicit-fallthrough In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Warning level 2 was used: -Wimplicit-fallthrough=2 Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
aa667c64 |
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09-Jul-2018 |
James Puthukattukaran <james.puthukattukaran@oracle.com> |
PCI: Workaround IDT switch ACS Source Validation erratum Some IDT switches incorrectly flag an ACS Source Validation error on completions for config read requests even though PCIe r4.0, sec 6.12.1.1, says that completions are never affected by ACS Source Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: Item #36 - Downstream port applies ACS Source Validation to Completions Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that completions are never affected by ACS Source Validation. However, completions received by a downstream port of the PCIe switch from a device that has not yet captured a PCIe bus number are incorrectly dropped by ACS Source Validation by the switch downstream port. Workaround: Issue a CfgWr1 to the downstream device before issuing the first CfgRd1 to the device. This allows the downstream device to capture its bus number; ACS Source Validation no longer stops completions from being forwarded by the downstream port. It has been observed that Microsoft Windows implements this workaround already; however, some versions of Linux and other operating systems may not. When doing the first config read to probe for a device, if the device is behind an IDT switch with this erratum: 1. Disable ACS Source Validation if enabled 2. Wait for device to become ready to accept config accesses (by using the Config Request Retry Status mechanism) 3. Do a config write to the endpoint 4. Enable ACS Source Validation (if it was enabled to begin with) The workaround suggested by IDT is basically only step 3, but we don't know when the device is ready to accept config requests. That means we need to do config reads until we receive a non-Config Request Retry Status, which means we need to disable ACS SV temporarily. Signed-off-by: James Puthukattukaran <james.puthukattukaran@oracle.com> [bhelgaas: changelog, clean up whitespace, fold in unused variable fix from Anders Roxell <anders.roxell@linaro.org>] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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ad281ecf |
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23-May-2018 |
Doug Meyer <dmeyer@gigaio.com> |
PCI: Add DMA alias quirk for Microsemi Switchtec NTB Add a quirk for the Microsemi Switchtec parts to allow DMA access via non-transparent bridging to work when the IOMMU is turned on. This exclusively addresses the ability of a remote NT endpoint to perform DMA accesses through the locally enumerated NT endpoint. Other aspects of the Switchtec NTB functionality, such as interrupts for doorbells and messages are independent of this quirk, and will work whether the IOMMU is on or off. When a requestor on one NT endpoint accesses memory on another NT endpoint, it does this via a devfn proxy ID. Proxy IDs are statically assigned to each NT endpoint by the NTB hardware as part of the release-from-reset sequence prior to PCI enumeration. These proxy IDs cannot be modified dynamically, and are not visible to the host during enumeration. When the Switchtec NTB driver loads it will map local requestor IDs, such as the root complex and transparent bridge DMA engines, to proxy IDs by populating those requestor IDs in hardware mapping table table entries. This establishes a fixed relationship between a requestor ID and a proxy ID. When a peer on a remote NT endpoint performs an access within a particular translation window in it's NT endpoint BAR address space, that access is translated to a DMA request on the local endpoint's bus. As part of the translation process, the original requestor ID has its devfn replaced with the proxy ID, and the bus portion of the BDF is replaced with the bus of the local NT endpoint. Thus, the DMA access from a remote NT endpoint will appear on the local bus to have come from the unknown devfn which the IOMMU will reject. Interrogate NTB hardware registers for each remote NT endpoint to obtain the proxy IDs that have been assigned to it and alias them to the local (enumerated) NT endpoint's device. The IOMMU then accepts the remote proxy IDs as if they were requests coming directly from the enumerated endpoint, giving remote requestors access to memory resources which the local host has made available. Note that the aliasing of the proxy IDs cannot be performed at the driver level given the current IOMMU architecture. Superficially this is because pci_add_dma_alias() symbol is not exported. Functionally, the current IOMMU design requires the aliasing to be performed prior to the creation of IOMMU groups. If a driver were to attempt to use pci_add_dma_alias() in its probe routine it would fail since the IOMMU groups have been set up by that time. If the Switchtec hardware supported dynamic proxy ID (re-)assignment this would be an issue, but it does not. To further clarify static proxy ID assignment: While the requester ID to proxy ID mapping can be dynamically changed, the number and value of proxy IDs given to an NT EP cannot, even for dynamic reconfiguration such as hot-add. Therefore, the chip configuration must account a priori for the proxy IDs needs, considering both static and dynamic system configurations. For example, a port on the chip may not having anything plugged into it at start of day; but it must have a sufficient number of proxy IDs assigned to accommodate the supported devices which may be hot-added. Switchtec NTB functionality with the IOMMU off is unchanged by this quirk. Signed-off-by: Doug Meyer <dmeyer@gigaio.com> [bhelgaas: use hard-coded Device IDs instead of adding #defines for each] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
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82e1719c |
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02-May-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Clean up whitespace in quirks.c Clean up whitespace, capitalization, etc. in comments. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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78047350 |
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01-May-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Reorder quirks infrastructure code The infrastructure that applies PCI quirks was buried in the middle of the quirks themselves (at one time it was probably at the end of the file, but new quirks tend to be added at the end of the file). Move it all to the top of the file so it's easy to find. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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333c8c12 |
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07-May-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add Qualcomm vendor ID Add the Qualcomm vendor ID to pci_ids.h and use it in quirks. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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f154a718 |
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27-Apr-2018 |
Mika Westerberg <mika.westerberg@linux.intel.com> |
PCI: Add ACS quirk for Intel 300 series Intel 300 series chipset still has the same ACS issue as the previous generations so extend the ACS quirk to cover it as well. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org
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e8440f4b |
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25-Apr-2018 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add ACS quirk for Intel 7th & 8th Gen mobile The specification update indicates these have the same errata for implementing non-standard ACS capabilities. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org
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1b30dfd3 |
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10-Apr-2018 |
Sinan Kaya <okaya@codeaurora.org> |
PCI: Mark Broadcom HT1100 and HT2000 Root Port Extended Tags as broken Per PCIe r3.1, sec 2.2.6.2 and 7.8.4, a Requester may not use 8-bit Tags unless its Extended Tag Field Enable is set, but all Receivers/Completers must handle 8-bit Tags correctly regardless of their Extended Tag Field Enable. Some devices do not handle 8-bit Tags as Completers, so add a quirk for them. If we find such a device, we disable Extended Tags for the entire hierarchy to make peer-to-peer DMA possible. The Broadcom HT1100/HT2000/HT2100 seems to have issues with handling 8-bit tags. Mark it as broken. This fixes Xorg hangs and unresponsive keyboards with errors like this: radeon 0000:06:00.0: GPU lockup (current fence id 0x000000000000000e last fence id 0x0000000000000 [drm:r600_ring_test [radeon]] *ERROR* radeon: ring 0 test failed (scratch(0x8504)=0xCAFEDEAD) [drm:r600_resume [radeon]] *ERROR* r600 startup failed on resume Fixes: 60db3a4d8cc9 ("PCI: Enable PCIe Extended Tags if supported") Link: https://bugzilla.kernel.org/show_bug.cgi?id=196197 Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> CC: stable@vger.kernel.org # v4.11: 62ce94a7a5a5 PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken CC: stable@vger.kernel.org # v4.11
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df62ab5e |
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09-Mar-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Tidy comments Remove pointless comments that tell us the file name, remove blank line comments, follow multi-line comment conventions. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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6846b3b5 |
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14-Mar-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Report quirks that take more than 10ms With "initcall_debug", we report how long every PCI quirk took. Even without "initcall_debug", report the runtime of any quirk that takes longer than 10ms. This is to make it easier to notice quirks that slow down boot. This was motivated by a report from Paul Menzel that PCI final quirks took half a second at boot. Link: https://lkml.kernel.org/r/44cada166e42007d27b4c3e3aa0744d7@molgen.mpg.de Reported-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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d89bd919 |
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14-Mar-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Report quirk timings with pci_info() instead of pr_debug() With "initcall_debug", we report how long every PCI quirk took. Previously we used pr_debug(), which means you have to figure out how to enable debug output. Log these timings using pci_info() instead so it doesn't depend on DEBUG, CONFIG_DYNAMIC_DEBUG, etc. Also, don't log anything at all unless "initcall_debug" is specified. This matches what we do in do_one_initcall_debug(). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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99605857 |
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19-Mar-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/VPD: Move VPD quirks to vpd.c Move the VPD-related quirks from quirks.c to vpd.c, which removes the need for struct pci_vpd outside vpd.c. The goal is to encapsulate all the VPD code and structures in vpd.c. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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bb9d8126 |
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09-Mar-2018 |
Arnd Bergmann <arnd@arndb.de> |
arch: remove tile port The Tile architecture port was added by Chris Metcalf in 2010, and maintained until early 2018 when he orphaned it due to his departure from Mellanox, and nobody else stepped up to maintain it. The product line is still around in the form of the BlueField SoC, but no longer uses the Tile architecture. There are also still products for sale with Tile-GX SoCs, notably the Mikrotik CCR router family. The products all use old (linux-3.3) kernels with lots of patches and won't be upgraded by their manufacturers. There have been efforts to port both OpenWRT and Debian to these, but both projects have stalled and are very unlikely to be continued in the future. Given that we are reasonably sure that nobody is still using the port with an upstream kernel any more, it seems better to remove it now while the port is in a good shape than to let it bitrot for a few years first. Cc: Chris Metcalf <chris.d.metcalf@gmail.com> Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Link: http://www.mellanox.com/page/npu_multicore_overview Link: https://jenkins.debian.net/view/rebootstrap/job/rebootstrap_tilegx_gcc7/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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07f4f97d |
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03-Mar-2018 |
Lukas Wunner <lukas@wunner.de> |
vga_switcheroo: Use device link for HDA controller Back in 2013, runtime PM for GPUs with integrated HDA controller was introduced with commits 0d69704ae348 ("gpu/vga_switcheroo: add driver control power feature. (v3)") and 246efa4a072f ("snd/hda: add runtime suspend/resume on optimus support (v4)"). Briefly, the idea was that the HDA controller is forced on and off in unison with the GPU. The original code is mostly still in place even though it was never a 100% perfect solution: E.g. on access to the HDA controller, the GPU is powered up via vga_switcheroo_runtime_resume_hdmi_audio() but there are no provisions to keep it resumed until access to the HDA controller has ceased: The GPU autosuspends after 5 seconds, rendering the HDA controller inaccessible. Additionally, a kludge is required when hda_intel.c probes: It has to check whether the GPU is powered down (check_hdmi_disabled()) and defer probing if so. However in the meantime (in v4.10) the driver core has gained a feature called device links which promises to solve such issues in a clean way: It allows us to declare a dependency from the HDA controller (consumer) to the GPU (supplier). The PM core then automagically ensures that the GPU is runtime resumed as long as the HDA controller's ->probe hook is executed and whenever the HDA controller is accessed. By default, the HDA controller has a dependency on its parent, a PCIe Root Port. Adding a device link creates another dependency on its sibling: PCIe Root Port ^ ^ | | | | HDA ===> GPU The device link is not only used for runtime PM, it also guarantees that on system sleep, the HDA controller suspends before the GPU and resumes after the GPU, and on system shutdown the HDA controller's ->shutdown hook is executed before the one of the GPU. It is a complete solution. Using this functionality is as simple as calling device_link_add(), which results in a dmesg entry like this: pci 0000:01:00.1: Linked as a consumer to 0000:01:00.0 The code for the GPU-governed audio power management can thus be removed (except where it's still needed for legacy manual power control). The device link is added in a PCI quirk rather than in hda_intel.c. It is therefore legal for the GPU to runtime suspend to D3cold even if the HDA controller is not bound to a driver or if CONFIG_SND_HDA_INTEL is not enabled, for accesses to the HDA controller will cause the GPU to wake up regardless if they're occurring outside of hda_intel.c (think config space readout via sysfs). Contrary to the previous implementation, the HDA controller's power state is now self-governed, rather than GPU-governed, whereas the GPU's power state is no longer fully self-governed. (The HDA controller needs to runtime suspend before the GPU can.) It is thus crucial that runtime PM is always activated on the HDA controller even if CONFIG_SND_HDA_POWER_SAVE_DEFAULT is set to 0 (which is the default), lest the GPU stays awake. This is achieved by setting the auto_runtime_pm flag on every codec and the AZX_DCAPS_PM_RUNTIME flag on the HDA controller. A side effect is that power consumption might be reduced if the GPU is in use but the HDA controller is not, because the HDA controller is now allowed to go to D3hot. Before, it was forced to stay in D0 as long as the GPU was in use. (There is no reduction in power consumption on my Nvidia GK107, but there might be on other chips.) The code paths for legacy manual power control are adjusted such that runtime PM is disabled during power off, thereby preventing the PM core from resuming the HDA controller. Note that the device link is not only added on vga_switcheroo capable systems, but for *any* GPU with integrated HDA controller. The idea is that the HDA controller streams audio via connectors located on the GPU, so the GPU needs to be on for the HDA controller to do anything useful. This commit implicitly fixes an unbalanced runtime PM ref upon unbind of hda_intel.c: On ->probe, a runtime PM ref was previously released under the condition "azx_has_pm_runtime(chip) || hda->use_vga_switcheroo", but on ->remove a runtime PM ref was only acquired under the first of those conditions. Thus, binding and unbinding the driver twice on a vga_switcheroo capable system caused the runtime PM refcount to drop below zero. The issue is resolved because the AZX_DCAPS_PM_RUNTIME flag is now always set if use_vga_switcheroo is true. For more information on device links please refer to: https://www.kernel.org/doc/html/latest/driver-api/device_link.html Documentation/driver-api/device_link.rst Cc: Dave Airlie <airlied@redhat.com> Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Reviewed-by: Peter Wu <peter@lekensteyn.nl> Tested-by: Kai Heng Feng <kai.heng.feng@canonical.com> # AMD PowerXpress Tested-by: Mike Lothian <mike@fireburn.co.uk> # AMD PowerXpress Tested-by: Denis Lisov <dennis.lissov@gmail.com> # Nvidia Optimus Tested-by: Peter Wu <peter@lekensteyn.nl> # Nvidia Optimus Tested-by: Lukas Wunner <lukas@wunner.de> # MacBook Pro Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: https://patchwork.freedesktop.org/patch/msgid/51bd38360ff502a8c42b1ebf4405ee1d3f27118d.1520068884.git.lukas@wunner.de
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1903be82 |
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02-Mar-2018 |
Hans de Goede <hdegoede@redhat.com> |
PCI: Add function 1 DMA alias quirk for Highpoint RocketRAID 644L The Highpoint RocketRAID 644L uses a Marvel 88SE9235 controller, as with other Marvel controllers this needs a function 1 DMA alias quirk. Note the RocketRAID 642L uses the same Marvel 88SE9235 controller and already is listed with a function 1 DMA alias quirk. Cc: stable@vger.kernel.org BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1534106 Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Tejun Heo <tj@kernel.org>
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832e4e1f |
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27-Feb-2018 |
Thomas Vincent-Cross <me@tvc.id.au> |
PCI: Add function 1 DMA alias quirk for Marvell 88SE9220 Add Marvell 88SE9220 DMA quirk as found and tested on bug 42679. Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679 Signed-off-by: Thomas Vincent-Cross <me@tvc.id.au> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
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4ef76ad0 |
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20-Feb-2018 |
Feng Kan <fkan@apm.com> |
PCI: Add ACS quirk for Ampere root ports The Ampere Computing PCIe root port does not support ACS at this point. However, the hardware provides isolation and source validation through the SMMU. The stream ID generated by the PCIe ports contain both the bus/device/function number as well as the port ID in its 3 most significant bits. Turn on ACS but disable all the peer-to-peer features. APM is being rebranded to Ampere. The Vendor and Device IDs change, but the functionality stays the same. Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
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7dcf688d |
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15-Feb-2018 |
Casey Leedom <leedom@chelsio.com> |
PCI/cxgb4: Extend T3 PCI quirk to T4+ devices We've run into a problem where our device is attached to a Virtual Machine and the use of the new pci_set_vpd_size() API doesn't help. The VM kernel has been informed that the accesses are okay, but all of the actual VPD Capability Accesses are trapped down into the KVM Hypervisor where it goes ahead and imposes the silent denials. The right idea is to follow the kernel.org commit 1c7de2b4ff88 ("PCI: Enable access to non-standard VPD for Chelsio devices (cxgb3)") which Alexey Kardashevskiy authored to establish a PCI Quirk for our T3-based adapters. This commit extends that PCI Quirk to cover Chelsio T4 devices and later. The advantage of this approach is that the VPD Size gets set early in the Base OS/Hypervisor Boot and doesn't require that the cxgb4 driver even be available in the Base OS/Hypervisor. Thus PF4 can be exported to a Virtual Machine and everything should work. Fixes: 67e658794ca1 ("cxgb4: Set VPD size so we can read both VPD structures") Cc: <stable@vger.kernel.org> # v4.9+ Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Arjun Vynipadath <arjun@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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7506dc79 |
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17-Jan-2018 |
Frederick Lawler <fred@fredlawl.com> |
PCI: Add wrappers for dev_printk() Add PCI-specific dev_printk() wrappers and use them to simplify the code slightly. No functional change intended. Signed-off-by: Frederick Lawler <fred@fredlawl.com> [bhelgaas: squash into one patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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39c94652 |
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18-Dec-2017 |
Sinan Kaya <okaya@codeaurora.org> |
PCI: Deprecate pci_get_bus_and_slot() pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as where a PCI device is present. This restricts the device drivers to be reused for other domain numbers. Getting ready to remove pci_get_bus_and_slot() function in favor of pci_get_domain_bus_and_slot(). When we have a pci_dev, extract the domain number from it. The config access syscalls don't allow the user to supply a domain number, so they only work on devices in domain 0, so we can just hard-code that. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> [bhelgaas: squash quirk & syscall patches together] Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
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aa008206 |
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16-Jan-2018 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add function 1 DMA alias quirk for Marvell 9128 The Marvell 9128 is the original device generating bug 42679, from which many other Marvell DMA alias quirks have been sourced, but we didn't have positive confirmation of the fix on 9128 until now. Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679 Link: https://www.spinics.net/lists/kvm/msg161459.html Reported-by: Binarus <lists@binarus.de> Tested-by: Binarus <lists@binarus.de> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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deb86999 |
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28-Dec-2017 |
Dongdong Liu <liudongdong3@huawei.com> |
PCI: Disable MSI for HiSilicon Hip06/Hip07 only in Root Port mode HiSilicon Hip06/Hip07 can operate as either a Root Port or an Endpoint. It always advertises an MSI capability, but it can only generate MSIs when in Endpoint mode. The device has the same Vendor and Device IDs in both modes, so check the Class Code and disable MSI only when operating as a Root Port. [bhelgaas: changelog] Fixes: 72f2ff0deb87 ("PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports") Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Cc: stable@vger.kernel.org # v4.11+
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7c1efb68 |
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15-Dec-2017 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Mark Ceton InfiniTV4 INTx masking as broken PCI_COMMAND_INTX_DISABLE is writable on the Ceton InfiniTV4, indicating that the device supports disabling the INTx# signal, but it apparently doesn't work. Mark the device so we know we can't use PCI_COMMAND_INTX_DISABLE to disable its interrupts. Link: https://lkml.kernel.org/r/92a65068-60b2-c1a8-9e17-ac41fe3c5c93@code.jackst.com Reported-by: John Strader <strader.john@code.jackst.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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292af71e |
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08-Dec-2017 |
Sergey Senozhatsky <sergey.senozhatsky.work@gmail.com> |
PCI: Remove unneeded kallsyms include The file was converted from print_fn_descriptor_symbol() to %pF some time ago (c9bbb4abb658 "PCI: use %pF instead of print_fn_descriptor_symbol() in quirks.c"). kallsyms does not seem to be needed anymore. Signed-off-by: Sergey Senozhatsky <sergey.senozhatsky@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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b2441318 |
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01-Nov-2017 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
06dc4ee5 |
|
12-Oct-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
PCI: Disable MSI for Freescale Layerscape PCIe RC mode The Freescale PCIe controller advertises the MSI/MSI-X capability in both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X by itself; it can only transfer MSI/MSI-X from downstream devices. Add a quirk to prevent use of MSI/MSI-X in RC mode. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
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#
f2ddaf8d |
|
17-Oct-2017 |
Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com> |
PCI: Apply Cavium ThunderX ACS quirk to more Root Ports Extend the Cavium ThunderX ACS quirk to cover more device IDs and restrict it to only Root Ports. Signed-off-by: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com> [bhelgaas: changelog, stable tag] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v4.12+
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#
7f342678 |
|
17-Oct-2017 |
Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com> |
PCI: Set Cavium ACS capability quirk flags to assert RR/CR/SV/UF The Cavium ThunderX (CN8XXX) family of PCIe Root Ports does not advertise an ACS capability. However, the RTL internally implements similar protection as if ACS had Request Redirection, Completion Redirection, Source Validation, and Upstream Forwarding features enabled. Change Cavium ACS capabilities quirk flags accordingly. Fixes: b404bcfbf035 ("PCI: Add ACS quirk for all Cavium devices") Signed-off-by: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com> [bhelgaas: tidy changelog, comment, stable tag] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v4.6+: b77d537d00d0: PCI: Apply Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices
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#
82215510 |
|
08-Sep-2017 |
David Daney <david.daney@cavium.com> |
PCI: Mark Cavium CN8xxx to avoid bus reset Root ports of cn8xxx do not function after bus reset when used with some e1000e and LSI HBA devices. Add a quirk to prevent bus reset on these root ports. Signed-off-by: David Daney <david.daney@cavium.com> [jglauber@cavium.com: fixed typo and whitespaces] Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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#
6faadbbb |
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14-Sep-2017 |
Christoph Hellwig <hch@lst.de> |
dmi: Mark all struct dmi_system_id instances const ... and __initconst if applicable. Based on similar work for an older kernel in the Grsecurity patch. [JD: fix toshiba-wmi build] [JD: add htcpen] [JD: move __initconst where checkscript wants it] Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jean Delvare <jdelvare@suse.de>
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#
96291d56 |
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01-Sep-2017 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Fix typos and whitespace errors Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
f1b0e54e |
|
17-Aug-2017 |
Jon Derrick <jonathan.derrick@intel.com> |
x86/PCI: Move VMD quirk to x86 fixups VMD currently only exists for Intel x86 products, so move the VMD quirk to arch/x86. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
077fa19c |
|
14-Aug-2017 |
dingtianhong <dingtianhong@huawei.com> |
PCI: Disable Relaxed Ordering Attributes for AMD A1100 Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe Root Port where Upstream Transaction Layer Packets with the Relaxed Ordering Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering set, it would cause Data Corruption, so we need to disable Relaxed Ordering Attribute when Upstream TLPs to the Root Port. Reported-and-suggested-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Acked-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
87e09cde |
|
14-Aug-2017 |
dingtianhong <dingtianhong@huawei.com> |
PCI: Disable Relaxed Ordering for some Intel processors According to the Intel spec section 3.9.1 said: 3.9.1 Optimizing PCIe Performance for Accesses Toward Coherent Memory and Toward MMIO Regions (P2P) In order to maximize performance for PCIe devices in the processors listed in Table 3-6 below, the soft- ware should determine whether the accesses are toward coherent memory (system memory) or toward MMIO regions (P2P access to other devices). If the access is toward MMIO region, then software can command HW to set the RO bit in the TLP header, as this would allow hardware to achieve maximum throughput for these types of accesses. For accesses toward coherent memory, software can command HW to clear the RO bit in the TLP header (no RO), as this would allow hardware to achieve maximum throughput for these types of accesses. Table 3-6. Intel Processor CPU RP Device IDs for Processors Optimizing PCIe Performance Processor CPU RP Device IDs Intel Xeon processors based on 6F01H-6F0EH Broadwell microarchitecture Intel Xeon processors based on 2F01H-2F0EH Haswell microarchitecture It means some Intel processors has performance issue when use the Relaxed Ordering Attribute, so disable Relaxed Ordering for these root port. Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Acked-by: Alexander Duyck <alexander.h.duyck@intel.com> Acked-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a99b646a |
|
14-Aug-2017 |
dingtianhong <dingtianhong@huawei.com> |
PCI: Disable PCIe Relaxed Ordering if unsupported When bit4 is set in the PCIe Device Control register, it indicates whether the device is permitted to use relaxed ordering. On some platforms using relaxed ordering can have performance issues or due to erratum can cause data-corruption. In such cases devices must avoid using relaxed ordering. The patch adds a new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING to indicate that Relaxed Ordering (RO) attribute should not be used for Transaction Layer Packets (TLP) targeted towards these affected root complexes. This patch checks if there is any node in the hierarchy that indicates that using relaxed ordering is not safe. In such cases the patch turns off the relaxed ordering by clearing the capability for this device. Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Acked-by: Ashok Raj <ashok.raj@intel.com> Acked-by: Alexander Duyck <alexander.h.duyck@intel.com> Acked-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a0418aa2 |
|
10-Aug-2017 |
Feng Kan <fkan@apm.com> |
PCI: Add ACS quirk for APM X-Gene devices The APM X-Gene PCIe root port does not support ACS at this point. However, the hardware provides isolation and source validation through the SMMU. The stream ID generated by the PCIe ports contain both the bus/device/ function number as well as the port ID in its 3 most significant bits. Turn on ACS but disable all the peer-to-peer features. Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Acked-by: Tanmay Inamdar <tinamdar@apm.com>
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#
630b3aff |
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01-Aug-2017 |
Lukas Wunner <lukas@wunner.de> |
treewide: Consolidate Apple DMI checks We're about to amend ACPI bus scan with DMI checks whether we're running on a Mac to support Apple device properties in AML. The DMI checks are performed for every single device, adding overhead for everything x86 that isn't Apple, which is the majority. Rafael and Andy therefore request to perform the DMI match only once and cache the result. Outside of ACPI various other Apple DMI checks exist and it seems reasonable to use the cached value there as well. Rafael, Andy and Darren suggest performing the DMI check in arch code and making it available with a header in include/linux/platform_data/x86/. To this end, add early_platform_quirks() to arch/x86/kernel/quirks.c to perform the DMI check and invoke it from setup_arch(). Switch over all existing Apple DMI checks, thereby fixing two deficiencies: * They are now #defined to false on non-x86 arches and can thus be optimized away if they're located in cross-arch code. * Some of them only match "Apple Inc." but not "Apple Computer, Inc.", which is used by BIOSes released between January 2006 (when the first x86 Macs started shipping) and January 2007 (when the company name changed upon introduction of the iPhone). Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Suggested-by: Darren Hart <dvhart@infradead.org> Signed-off-by: Lukas Wunner <lukas@wunner.de> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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#
9b44b0b0 |
|
11-Jul-2017 |
Joerg Roedel <jroedel@suse.de> |
PCI: Mark AMD Stoney GPU ATS as broken ATS is broken on this hardware and causes IOMMU stalls and system failure. Disable ATS on these devices to make them usable again with IOMMU enabled. Note that the commit in the Fixes tag is not buggy; it just uncovers the problem in the hardware by increasing the ATS flush rate. Link: https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020836.html Link: https://bugzilla.redhat.com/show_bug.cgi?id=1409201 Fixes: b1516a14657a ("iommu/amd: Implement flush queue") Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
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#
62ce94a7 |
|
11-Jul-2017 |
Sinan Kaya <okaya@codeaurora.org> |
PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken Per PCIe r3.1, sec 2.2.6.2 and 7.8.4, a Requester may not use 8-bit Tags unless its Extended Tag Field Enable is set, but all Receivers/Completers must handle 8-bit Tags correctly regardless of their Extended Tag Field Enable. Some devices do not handle 8-bit Tags as Completers, so add a quirk for them. If we find such a device, we disable Extended Tags for the entire hierarchy to make peer-to-peer DMA possible. The Broadcom HT2100 seems to have issues with handling 8-bit tags. Mark it as broken. The pci_walk_bus() in the quirk handles devices we've enumerated in the past, and pci_configure_device() handles devices we enumerate in the future. Fixes: 60db3a4d8cc9 ("PCI: Enable PCIe Extended Tags if supported") Link: https://bugzilla.redhat.com/show_bug.cgi?id=1467674 Reported-and-tested-by: Wim ten Have <wim.ten.have@oracle.com> Signed-off-by: Sinan Kaya <okaya@codeaurora.org> [bhelgaas: changelog, tweak messages, rename bit and quirk] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
5938628c |
|
09-May-2017 |
Bjorn Helgaas <bhelgaas@google.com> |
drm/radeon: make MacBook Pro d3_delay quirk more generic The PCI Power Management Spec, r1.2, sec 5.6.1, requires a 10 millisecond delay when powering on a device, i.e., transitioning from state D3hot to D0. Apparently some devices require more time, and d1f9809ed131 ("drm/radeon: add quirk for d3 delay during switcheroo poweron for apple macbooks") added an additional delay for the Radeon device in a MacBook Pro. 4807c5a8a0c8 ("drm/radeon: add a PX quirk list") made the affected device more explicit. Add a generic PCI quirk to increase the d3_delay. This means we will use the additional delay for *all* wakeups from D3, not just those initiated by radeon_switcheroo_set_state(). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> CC: Maarten Lankhorst <maarten.lankhorst@canonical.com>
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#
2f686f1d |
|
19-May-2017 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Correct PCI_STD_RESOURCE_END usage PCI_STD_RESOURCE_END is (confusingly) the index of the last valid BAR, not the *number* of BARs. To iterate through all possible BARs, we need to include PCI_STD_RESOURCE_END. Fixes: 9fe373f9997b ("PCI: Increase IBM ipr SAS Crocodile BARs to at least system page size") Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
d40b7fd2 |
|
07-Jun-2017 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Mark Intel XXV710 NIC INTx masking as broken Just like the other XL710 and X710 variants, the XXV710 device IDs appear to have the same hardware bug, the status register doesn't report pending interrupts resulting in "irq xx: nobody cared..." errors from the spurious interrupt handler when we try to use it with device assignment. Reported-by: Stefan Assmann <sassmann@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
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#
c4e649b0 |
|
19-Apr-2017 |
Stefan Assmann <sassmann@kpanic.de> |
PCI: Disable boot interrupt quirk for ASUS M2N-LR The ASUS M2N-LR should not trigger boot interrupt quirks although it carries an Intel 6702PXH. On this board the boot interrupt quirks cause incorrect IRQ assignments and should be disabled. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=43074 Tested-by: Solomon Peachy <pizza@shaftnet.org> Signed-off-by: Stefan Assmann <sassmann@kpanic.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
48f52d1a |
|
14-Apr-2017 |
Christoph Hellwig <hch@lst.de> |
PCI: Call pcie_flr() from reset_chelsio_generic_dev() Instead of copy & pasting and old version of the code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
c8d8096a |
|
14-Apr-2017 |
Christoph Hellwig <hch@lst.de> |
PCI: Call pcie_flr() from reset_intel_82599_sfp_virtfn() The 82599 quirk contained an outdated copy of the FLR code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
45a23293 |
|
13-Apr-2017 |
Jayachandran C <c.jayachandran@gmail.com> |
PCI: Avoid generating invalid ThunderX2 DMA aliases On Cavium ThunderX2 arm64 SoCs (formerly known as Broadcom Vulcan), the PCI topology is slightly unusual. For a multi-node system, it looks like: 00:00.0 PCI bridge to [bus 01-1e] 01:0a.0 PCI-to-PCIe bridge to [bus 02-04] 02:00.0 PCIe Root Port bridge to [bus 03-04] (XLATE_ROOT) 03:00.0 PCIe Endpoint pci_for_each_dma_alias() assumes IOMMU translation is done at the root of the PCI hierarchy. It generates 03:00.0, 01:0a.0, and 00:00.0 as DMA aliases for 03:00.0 because buses 01 and 00 are non-PCIe buses that don't carry the Requester ID. Because the ThunderX2 IOMMU is at 02:00.0, the Requester IDs 01:0a.0 and 00:00.0 are never valid for the endpoint. This quirk stops alias generation at the XLATE_ROOT bridge so we won't generate 01:0a.0 or 00:00.0. The current IOMMU code only maps the last alias (this is a separate bug in itself). Prior to this quirk, we only created IOMMU mappings for the invalid Requester ID 00:00:0, which never matched any DMA transactions. With this quirk, we create IOMMU mappings for a valid Requester ID, which fixes devices with no aliases but leaves devices with aliases still broken. The last alias for the endpoint is also used by the ARM GICv3 MSI-X code. Without this quirk, the GIC Interrupt Translation Tables are setup with the invalid Requester ID, and the MSI-X generated by the device fails to be translated and routed. Link: https://bugzilla.kernel.org/show_bug.cgi?id=195447 Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Acked-by: David Daney <david.daney@cavium.com>
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#
fce5d57e |
|
11-Apr-2017 |
Jarod Wilson <jarod@redhat.com> |
PCI: Add bridge DMA alias quirk for ITE 8893 bridge The ITE 8893 bridge has the same problems as the ITE 8892, which were resulting in crippling an older PCI 1Gbps NIC down to 45Mbps throughput with IOMMU and VT-d enabled. With the patch, this old e1000 goes back up to ~900Mbps. Suggested-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
|
#
f65fd1aa |
|
03-Apr-2017 |
Sasha Neftin <sasha.neftin@intel.com> |
PCI: Avoid FLR for Intel 82579 NICs Per Intel Specification Update 335553-002 (see link below), some 82579 network adapters advertise a Function Level Reset (FLR) capability, but they can hang when an FLR is triggered. To reproduce the problem, attach the device to a VM, then detach and try to attach again. Add a quirk to prevent the use of FLR on these devices. [bhelgaas: changelog, comments] Link: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/82579lm-82579v-gigabit-network-connection-spec-update.pdf Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
b77d537d |
|
30-Mar-2017 |
Manish Jaggi <mjaggi@caviumnetworks.com> |
PCI: Apply Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices Only apply the Cavium ACS quirk to devices with ID in the range 0xa000-0xa0ff. These are the on-chip PCI devices for CN81xx/CN83xx/CN88xx. Fixes: b404bcfbf035 ("PCI: Add ACS quirk for all Cavium devices") Reported-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Manish Jaggi <mjaggi@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Acked-by: Alex Williamson <alex.williamson@redhat.com>
|
#
0d5370d1 |
|
27-Feb-2017 |
Ethan Zhao <ethan.zhao@oracle.com> |
PCI: Prevent VPD access for QLogic ISP2722 QLogic ISP2722-based 16/32Gb Fibre Channel to PCIe Adapter has the VPD access issue too, while read the common pci-sysfs access interface shown as /sys/devices/pci0000:00/0000:00:03.2/0000:0b:00.0/vpd with simple 'cat' could cause system hang and panic: Kernel panic - not syncing: An NMI occurred. Depending on your system the reason for the NMI is logged in any one of the following resources: 1. Integrated Management Log (IML) 2. OA Syslog 3. OA Forward Progress Log 4. iLO Event Log CPU: 0 PID: 15070 Comm: udevadm Not tainted 4.1.12 Hardware name: HP ProLiant DL380 Gen9/ProLiant DL380 Gen9, BIOS P89 12/27/2015 0000000000000086 000000007f0cdf51 ffff880c4fa05d58 ffffffff817193de ffffffffa00b42d8 0000000000000075 ffff880c4fa05dd8 ffffffff81714072 0000000000000008 ffff880c4fa05de8 ffff880c4fa05d88 000000007f0cdf51 Call Trace: <NMI> [<ffffffff817193de>] dump_stack+0x63/0x81 [<ffffffff81714072>] panic+0xd0/0x20e [<ffffffffa00b390d>] hpwdt_pretimeout+0xdd/0xe0 [hpwdt] [<ffffffff81021fc9>] ? sched_clock+0x9/0x10 [<ffffffff8101c101>] nmi_handle+0x91/0x170 [<ffffffff8101c10c>] ? nmi_handle+0x9c/0x170 [<ffffffff8101c5fe>] io_check_error+0x1e/0xa0 [<ffffffff8101c719>] default_do_nmi+0x99/0x140 [<ffffffff8101c8b4>] do_nmi+0xf4/0x170 [<ffffffff817232c5>] end_repeat_nmi+0x1a/0x1e [<ffffffff815d724b>] ? pci_conf1_read+0xeb/0x120 [<ffffffff815d724b>] ? pci_conf1_read+0xeb/0x120 [<ffffffff815d724b>] ? pci_conf1_read+0xeb/0x120 <<EOE>> [<ffffffff815db4b3>] raw_pci_read+0x23/0x40 [<ffffffff815db4fc>] pci_read+0x2c/0x30 [<ffffffff8136f612>] pci_user_read_config_word+0x72/0x110 [<ffffffff8136f746>] pci_vpd_pci22_wait+0x96/0x130 [<ffffffff8136ff9b>] pci_vpd_pci22_read+0xdb/0x1a0 [<ffffffff8136ea30>] pci_read_vpd+0x20/0x30 [<ffffffff8137d590>] read_vpd_attr+0x30/0x40 [<ffffffff8128e037>] sysfs_kf_bin_read+0x47/0x70 [<ffffffff8128d24e>] kernfs_fop_read+0xae/0x180 [<ffffffff8120dd97>] __vfs_read+0x37/0x100 [<ffffffff812ba7e4>] ? security_file_permission+0x84/0xa0 [<ffffffff8120e366>] ? rw_verify_area+0x56/0xe0 [<ffffffff8120e476>] vfs_read+0x86/0x140 [<ffffffff8120f3f5>] SyS_read+0x55/0xd0 [<ffffffff81720f2e>] system_call_fastpath+0x12/0x71 Shutting down cpus with NMI Kernel Offset: disabled drm_kms_helper: panic occurred, switching back to text console So blacklist the access to its VPD. Signed-off-by: Ethan Zhao <ethan.zhao@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.6+
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#
4091fb95 |
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27-Feb-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
scripts/spelling.txt: add "followings" pattern and fix typo instances Fix typos and add the following to the scripts/spelling.txt: followings||following While we are here, add a missing colon in the boilerplate in DT binding documents. The "you SoC" in allwinner,sunxi-pinctrl.txt was fixed as well. I reworded "as the followings:" to "as follows:" for drivers/usb/gadget/udc/renesas_usb3.c. Link: http://lkml.kernel.org/r/1481573103-11329-32-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
33be632b |
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16-Feb-2017 |
Sinan Kaya <okaya@codeaurora.org> |
PCI: Add ACS quirk for Qualcomm QDF2400 and QDF2432 The Qualcomm QDF2xxx root ports don't advertise an ACS capability, but they do provide ACS-like features to disable peer transactions and validate bus numbers in requests. To be specific: * Hardware supports source validation but it will report the issue as Completer Abort instead of ACS Violation. * Hardware doesn't support peer-to-peer and each root port is a root complex with unique segment numbers. * It is not possible for one root port to pass traffic to the other root port. All PCIe transactions are terminated inside the root port. Add an ACS quirk for the QDF2400 and QDF2432 products. [bhelgaas: changelog] Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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#
cd3e2eb8 |
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13-Feb-2017 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
PCI: Sort the list of devices with D3 delay quirk by ID Sort the list of Intel devices that have no PCI D3 delay by ID. Add a comment for group of devices that had not been marked yet. There is no functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
72f2ff0d |
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03-Feb-2017 |
Dongdong Liu <liudongdong3@huawei.com> |
PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports The PCIe Root Port in Hip06/Hip07 SoCs advertises an MSI capability, but it cannot generate MSIs. It can transfer MSI/MSI-X from downstream devices, but does not support MSI/MSI-X itself. Add a quirk to prevent use of MSI/MSI-X by the Root Port. [bhelgaas: changelog, sort vendor ID #define, drop device ID #define] Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
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#
ce709f86 |
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27-Jan-2017 |
Jon Mason <jon.mason@broadcom.com> |
PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSS The Broadcom Northstar2 SoC has a number of quirks for the PAXC (internal/fake) PCI bus. Specifically, the PCI config space is shared between the root port and the first PF (ie., PF0), and a number of fields are tied to zero (thus preventing them from being set). These cannot be "fixed" in device firmware, so we must fix them with a quirk. Signed-off-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
7184f5b4 |
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19-Jan-2017 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add ACS quirk for Intel Union Point Intel 200-series chipsets have the same errata as 100-series: the ACS capability doesn't follow the PCIe spec, the capability and control registers are dwords rather than words. Add PCIe root port device IDs to existing quirk. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
8b0e1953 |
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24-Dec-2016 |
Thomas Gleixner <tglx@linutronix.de> |
ktime: Cleanup ktime_set() usage ktime_set(S,N) was required for the timespec storage type and is still useful for situations where a Seconds and Nanoseconds part of a time value needs to be converted. For anything where the Seconds argument is 0, this is pointless and can be replaced with a simple assignment. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org>
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#
1c7de2b4 |
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24-Oct-2016 |
Alexey Kardashevskiy <aik@ozlabs.ru> |
PCI: Enable access to non-standard VPD for Chelsio devices (cxgb3) There is at least one Chelsio 10Gb card which uses VPD area to store some non-standard blocks (example below). However pci_vpd_size() returns the length of the first block only assuming that there can be only one VPD "End Tag". Since 4e1a635552d3 ("vfio/pci: Use kernel VPD access functions"), VFIO blocks access beyond that offset, which prevents the guest "cxgb3" driver from probing the device. The host system does not have this problem as its driver accesses the config space directly without pci_read_vpd(). Add a quirk to override the VPD size to a bigger value. The maximum size is taken from EEPROMSIZE in drivers/net/ethernet/chelsio/cxgb3/common.h. We do not read the tag as the cxgb3 driver does as the driver supports writing to EEPROM/VPD and when it writes, it only checks for 8192 bytes boundary. The quirk is registered for all devices supported by the cxgb3 driver. This adds a quirk to the PCI layer (not to the cxgb3 driver) as the cxgb3 driver itself accesses VPD directly and the problem only exists with the vfio-pci driver (when cxgb3 is not running on the host and may not be even loaded) which blocks accesses beyond the first block of VPD data. However vfio-pci itself does not have quirks mechanism so we add it to PCI. This is the controller: Ethernet controller [0200]: Chelsio Communications Inc T310 10GbE Single Port Adapter [1425:0030] This is what I parsed from its VPD: === b'\x82*\x0010 Gigabit Ethernet-SR PCI Express Adapter\x90J\x00EC\x07D76809 FN\x0746K' 0000 Large item 42 bytes; name 0x2 Identifier String b'10 Gigabit Ethernet-SR PCI Express Adapter' 002d Large item 74 bytes; name 0x10 #00 [EC] len=7: b'D76809 ' #0a [FN] len=7: b'46K7897' #14 [PN] len=7: b'46K7897' #1e [MN] len=4: b'1037' #25 [FC] len=4: b'5769' #2c [SN] len=12: b'YL102035603V' #3b [NA] len=12: b'00145E992ED1' 007a Small item 1 bytes; name 0xf End Tag 0c00 Large item 16 bytes; name 0x2 Identifier String b'S310E-SR-X ' 0c13 Large item 234 bytes; name 0x10 #00 [PN] len=16: b'TBD ' #13 [EC] len=16: b'110107730D2 ' #26 [SN] len=16: b'97YL102035603V ' #39 [NA] len=12: b'00145E992ED1' #48 [V0] len=6: b'175000' #51 [V1] len=6: b'266666' #5a [V2] len=6: b'266666' #63 [V3] len=6: b'2000 ' #6c [V4] len=2: b'1 ' #71 [V5] len=6: b'c2 ' #7a [V6] len=6: b'0 ' #83 [V7] len=2: b'1 ' #88 [V8] len=2: b'0 ' #8d [V9] len=2: b'0 ' #92 [VA] len=2: b'0 ' #97 [RV] len=80: b's\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'... 0d00 Large item 252 bytes; name 0x11 #00 [VC] len=16: b'122310_1222 dp ' #13 [VD] len=16: b'610-0001-00 H1\x00\x00' #26 [VE] len=16: b'122310_1353 fp ' #39 [VF] len=16: b'610-0001-00 H1\x00\x00' #4c [RW] len=173: b'\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'... 0dff Small item 0 bytes; name 0xf End Tag 10f3 Large item 13315 bytes; name 0x62 !!! unknown item name 98: b'\xd0\x03\x00@`\x0c\x08\x00\x00\x00\x00\x00\x00\x00\x00\x00' === Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
044bc425 |
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15-Nov-2016 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Expand "VPD access disabled" quirk message It's not very enlightening to see pci 0000:07:00.0: [Firmware Bug]: VPD access disabled in the dmesg log because there's no clue about what the firmware bug is. Expand the message to explain why we're disabling VPD. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
1600f625 |
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15-Nov-2016 |
Noa Osherovich <noaos@mellanox.com> |
PCI: Support INTx masking on ConnectX-4 with firmware x.14.1100+ Mellanox devices were marked as having INTx masking ability broken. As a result, the VFIO driver fails to start when more than one device function is passed-through to a VM if both have the same INTx pin. Prior to Connect-IB, Mellanox devices exposed to the operating system one PCI function per all ports. Starting from Connect-IB, the devices are function-per-port. When passing the second function to a VM, VFIO will fail to start. Exclude ConnectX-4, ConnectX4-Lx and Connect-IB from the list of Mellanox devices marked as having broken INTx masking: - ConnectX-4 and ConnectX4-LX firmware version is checked. If INTx masking is supported, we unmark the broken INTx masking. - Connect-IB does not support INTx currently so will not cause any problem. [bhelgaas: call pci_disable_device() always, after iounmap()] Fixes: 11e42532ada3 ("PCI: Assume all Mellanox devices have broken INTx masking") Signed-off-by: Noa Osherovich <noaos@mellanox.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
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#
d76d2fe0 |
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15-Nov-2016 |
Noa Osherovich <noaos@mellanox.com> |
PCI: Convert Mellanox broken INTx quirks to be for listed devices only Change Mellanox's broken_intx_masking() quirk from an "all Mellanox devices" to a quirk for listed devices only. [bhelgaas: remove #defines, reorder to keep other quirks together] Signed-off-by: Noa Osherovich <noaos@mellanox.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
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#
b88214ce |
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15-Nov-2016 |
Noa Osherovich <noaos@mellanox.com> |
PCI: Convert broken INTx masking quirks from HEADER to FINAL Convert all quirk_broken_intx_masking() quirks from HEADER to FINAL. The quirk sets dev->broken_intx_masking, which is only used by pci_intx_mask_supported(), which is not needed until after FINAL quirks have been run. [bhelgaas: changelog] Signed-off-by: Noa Osherovich <noaos@mellanox.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
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#
0bec9057 |
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05-Sep-2016 |
Herbert Xu <herbert@gondor.apana.org.au> |
PCI: Fix cavium quirk compile failure with PCI_ATS off The newly added quirk_cavium_sriov_rnm_link doesn't compile if PCI_ATS is off. This patch adds a check for PCI_ATS. Fixes: 21b5b8eebbae ("PCI: quirk fixup for cavium invalid sriov...") Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
443b40ba |
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06-Sep-2016 |
Jon Derrick <jonathan.derrick@intel.com> |
x86/PCI: VMD: Add quirk for AER to ignore source ID VMD root ports change all source ids to the VMD device ID. To find the sender of the AER notification, we need to scan all child devices for the AER sender, rather than relying on the source ID from the message. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
21b5b8ee |
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23-Aug-2016 |
Ananth Jasty <Ananth.Jasty@cavium.com> |
PCI: quirk fixup for cavium invalid sriov link value. Cavium cn88xx hardware presents an incorrect SR-IOV Function Dependency Link, add a fixup quirk for the affected devices. Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Ananth Jasty <Ananth.Jasty@cavium.com> Signed-off-by: Omer Khaliq <okhaliq@caviumnetworks.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
82a6a81c |
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26-Jul-2016 |
Xavier Gnata <xavier.gnata@gmail.com> |
thunderbolt: Add support for INTEL_FALCON_RIDGE_2C controller. From: Xavier Gnata <xavier.gnata@gmail.com> Add support to INTEL_FALCON_RIDGE_2C controller and corresponding quirk to support suspend/resume. Tested against 4.7 master on a MacBook Air 11" 2015. Signed-off-by: Andreas Noever <andreas.noever@gmail.com> Reviewed-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
25eb7e5c |
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26-Jul-2016 |
Andreas Noever <andreas.noever@gmail.com> |
thunderbolt: Fix resume quirk for Falcon Ridge 4C. The quirk 'quirk_apple_wait_for_thunderbolt' did not fire on Falcon Ridge 4C controllers with subdevice/subvendor set to zero. This lead to lost pci devices on system resume. Older thunderbolt controllers (pre Falcon Ridge) used the same device id for bridges and for the controller. On Apple hardware the subvendor- & subdevice-ids were set for the controller, but not for bridges. So that is what was used to differentiate between the two. Starting with Falcon Ridge bridges and controllers received different device ids. Additionally on some MacBookPro models (but not all) the subvendor/subdevice was zeroed. Starting with a42fb351c (thunderbolt: Allow loading of module on recent Apple MacBooks with thunderbolt 2 controller) the thunderbolt driver binds to all Falcon Ridge 4C controllers (irregardless of subvendor/subdevice). The corresponding quirk was not updated. This commit changes the quirk to check the device class instead of its subvendor-/subdeviceids. This works for all generations of Thunderbolt controllers. Signed-off-by: Andreas Noever <andreas.noever@gmail.com> Reviewed-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
8e2e0317 |
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09-Aug-2016 |
Maik Broemme <mbroemme@libmpq.org> |
PCI: Mark Atheros AR9580 to avoid bus reset Similar to the AR93xx and the AR94xx series, the AR95xx also have the same quirk for the Bus Reset. It will lead to instant system reset if the device is assigned via VFIO to a KVM VM. I've been able reproduce this behavior with a MikroTik R11e-2HnD. Fixes: c3e59ee4e766 ("PCI: Mark Atheros AR93xx to avoid bus reset") Signed-off-by: Maik Broemme <mbroemme@libmpq.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.14+
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#
9fad4012 |
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28-Jul-2016 |
Edward Cree <ecree@solarflare.com> |
PCI: Add ACS quirk for Solarflare SFC9220 The Solarflare SFC9220 apparently lacks an ACS capability, but does not perform peer-to-peer between functions. Add a quirk so we know about this isolation. [bhelgaas: changelog] Signed-off-by: Edward Cree <ecree@solarflare.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
db83f87b |
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18-Jul-2016 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add DMA alias quirk for Adaptec 3805 Add a DMA alias quirk for the Adaptec 3805, just like the 3405 quirk added in commit d3d2ab43ddae ("PCI: Add DMA alias quirk for Adaptec 3405"). Link: https://www.redhat.com/archives/vfio-users/2016-July/msg00046.html Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
9ac0108c |
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30-May-2016 |
Chris Blake <chrisrblake93@gmail.com> |
PCI: Mark Atheros AR9485 and QCA9882 to avoid bus reset Similar to the AR93xx series, the AR94xx and the Qualcomm QCA988x also have the same quirk for the Bus Reset. Fixes: c3e59ee4e766 ("PCI: Mark Atheros AR93xx to avoid bus reset") Signed-off-by: Chris Blake <chrisrblake93@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.14+
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#
00456b35 |
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18-May-2016 |
Aaron Sierra <asierra@xes-inc.com> |
PCI: Add function 1 DMA alias quirk for Marvell 88SE9182 Add function 1 DMA alias quirk for Marvell 88SE9182. We found this quirk reported in the same thread as other Marvell devices, but no patch resulted: https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 Signed-off-by: Steven Graham <sgraham@xes-inc.com> Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
1bf2bf22 |
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31-Mar-2016 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Work around Intel Sunrise Point PCH incorrect ACS capability Intel Sunrise Point root ports implement ACS but use dwords for the capability and control registers, putting the control register at the wrong offset. Use quirks to enable and test ACS for these devices, which match the standard functions modulo the broken control register offset. Note that lspci assumes devices implement ACS per spec, so it shows invalid ACS data for these devices. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
c1d61c9b |
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31-Mar-2016 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Reverse standard ACS vs device-specific ACS enabling The original thought was that if a device implemented ACS, then surely we want to use that... well, it turns out that devices can make an ACS capability so broken that we still need to fall back to quirks. Reverse the order of ACS enabling to give quirks first shot at it. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
8bcf4525 |
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24-Mar-2016 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Mark Intel i40e NIC INTx masking as broken All of the i40e (XL710/X710) 10/20/40GbE NICs lack support for indicating INTx is asserted via the interrupt bit in the PCI status register. The DisINTx bit in the command register is functional, causing these devices to be incorrectly detected as supporting INTx masking. Quirk them to properly indicate no INTx masking support. Device IDs copied from i40e_devids.h. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: John Ronciak <john.ronciak@intel.com> CC: Jesse Brandeburg <jesse.brandeburg@intel.com>
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#
b1a928cd |
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03-Mar-2016 |
Jacek Lawrynowicz <jacek.lawrynowicz@intel.com> |
PCI: Add DMA alias quirk for mic_x200_dma The MIC x200 NTB forwards DMA transactions upstream using multiple alien RIDs. These RIDs have to be added as aliases to the DMA device to allow buffer access when the IOMMU is enabled. Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Acked-by: David Woodhouse <David.Woodhouse@intel.com>
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#
48c83080 |
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24-Feb-2016 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Move informational printk to pci_add_dma_alias() One of the quirks that adds DMA aliases logs an informational message in dmesg. Move that to pci_add_dma_alias() so all users log the message consistently. No functional change intended (except extra message). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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#
f0af9593 |
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24-Feb-2016 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add pci_add_dma_alias() to abstract implementation Add a pci_add_dma_alias() interface to encapsulate the details of adding an alias. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
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#
19bf4d4f |
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20-Mar-2016 |
Lukas Wunner <lukas@wunner.de> |
thunderbolt: Support 1st gen Light Ridge controller Add support for the 1st gen Light Ridge controller, which is built into these systems: iMac12,1 2011 21.5" iMac12,2 2011 27" Macmini5,1 2011 i5 2.3 GHz Macmini5,2 2011 i5 2.5 GHz Macmini5,3 2011 i7 2.0 GHz MacBookPro8,1 2011 13" MacBookPro8,2 2011 15" MacBookPro8,3 2011 17" MacBookPro9,1 2012 15" MacBookPro9,2 2012 13" Light Ridge (CV82524) was the very first copper Thunderbolt controller, introduced 2010 alongside its fiber-optic cousin Light Peak (CVL2510). Consequently the chip suffers from some teething troubles: - MSI is broken for hotplug signaling on the downstream bridges: The chip just never sends an interrupt. It requests 32 MSIs for each of its six bridges and the pcieport driver only allocates one per bridge. However I've verified that even if 32 MSIs are allocated there's no interrupt on hotplug. The only option is thus to disable MSI, which is also what OS X does. Apparently all Thunderbolt chips up to revision 1 of Cactus Ridge 4C are plagued by this issue so quirk those as well. - The chip supports a maximum hop_count of 32, unlike its successors which support only 12. Fixup ring_interrupt_active() to cope with values >= 32. - Another peculiarity is that the chip supports a maximum of 13 ports whereas its successors support 12. However the additional port (#5) seems to be unusable as reading its TB_CFG_PORT config space results in TB_CFG_ERROR_INVALID_CONFIG_SPACE. Add a quirk to mark the port disabled on the root switch, assuming that's necessary on all Macs using this chip. Tested-by: Lukas Wunner <lukas@wunner.de> [MacBookPro9,1] Tested-by: William Brown <william@blackhats.net.au> [MacBookPro8,2] Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Andreas Noever <andreas.noever@gmail.com>
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#
1d111406 |
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20-Mar-2016 |
Lukas Wunner <lukas@wunner.de> |
PCI: Add Intel Thunderbolt device IDs Intel Gen 1 and 2 chips use the same ID for NHI, bridges and switch. Gen 3 chips and onward use a distinct ID for the NHI. No functional change intended. Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Andreas Noever <andreas.noever@gmail.com>
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#
7b78f48a |
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15-Mar-2016 |
Heikki Krogerus <heikki.krogerus@linux.intel.com> |
PCI: Add PCI_CLASS_SERIAL_USB_DEVICE definition PCI-SIG has defined Interface FEh for Base Class 0Ch, Sub-Class 03h as "USB Device (not host controller)". It is already being used in various USB device controller drivers for matching, so add PCI_CLASS_SERIAL_USB_DEVICE and use it. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
7c20078a |
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15-Feb-2016 |
Babu Moger <babu.moger@oracle.com> |
PCI: Prevent VPD access for buggy devices On some devices, reading or writing VPD causes a system panic. This can be easily reproduced by running "lspci -vvv" or "cat /sys/bus/devices/XX../vpd". Blacklist these devices so we don't access VPD data at all. [bhelgaas: changelog, comment, drop pci/access.c changes] Link: https://bugzilla.kernel.org/show_bug.cgi?id=110681 Tested-by: Shane Seymour <shane.seymour@hpe.com> Tested-by: Babu Moger <babu.moger@oracle.com> Signed-off-by: Babu Moger <babu.moger@oracle.com> Signed-off-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Alexander Duyck <alexander.duyck@gmail.com>
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#
b404bcfb |
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29-Jan-2016 |
Manish Jaggi <mjaggi@caviumnetworks.com> |
PCI: Add ACS quirk for all Cavium devices Cavium devices matching this quirk do not perform peer-to-peer with other functions, allowing masking out these bits as if they were unimplemented in the ACS capability. Signed-off-by: Manish Jaggi <mjaggi@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Tirumalesh Chalamarla <tchalamarla@cavium.com>
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#
8b9b963e |
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19-Jan-2016 |
Tim Sander <tim@krieglstein.org> |
PCI: Add function 1 DMA alias quirk for Lite-On/Plextor M6e/Marvell 88SS9183 Add function 1 DMA alias quirk for Lite-On/Plextor M6e/Marvell 88SS9183. Signed-off-by: Tim Sander <tim@krieglstein.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Williamson <alex.williamson@redhat.com>
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#
c2e771b0 |
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10-Dec-2015 |
Simon Horman <simon.horman@netronome.com> |
PCI: Limit config space size for Netronome NFP4000 Like the NFP6000, the NFP4000 as an erratum where reading/writing to PCI config space addresses above 0x600 can cause the NFP to generate PCIe completion timeouts. Limit the NFP4000's PF's config space size to 0x600 bytes as is already done for the NFP6000. The NFP4000's VF is 0x6004 (PCI_DEVICE_ID_NETRONOME_NFP6000_VF), the same device ID as the NFP6000's VF. Thus, its config space is already limited by the existing use of quirk_nfp6000(). Signed-off-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
9f33a2ae |
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30-Sep-2015 |
Jason S. McMullan <jason.mcmullan@netronome.com> |
PCI: Limit config space size for Netronome NFP6000 family The NFP6000 has an erratum where reading/writing to PCI config space addresses above 0x600 can cause the NFP to generate PCIe completion timeouts. Limit the NFP6000's config space size to 0x600 bytes. Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> [simon: edited changelog] Signed-off-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
aba72ddc |
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04-Nov-2015 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
pci: Decouple quirks.c from i915_reg.h i915 register defines are going to become type safe, so going forward the register defines can't be used as straight numbers. Since quirks.c needs just a few extra register defines from i915_reg.h, decouple the two by defining the required registers locally in quirks.c. This was already done for a few other igpu related registers. Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-2-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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#
c56d4450 |
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18-Oct-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
PCI: Turn off Request Attributes to avoid Chelsio T5 Completion erratum The Chelsio T5 has a PCIe compliance erratum that causes Malformed TLP or Unexpected Completion errors in some systems, which may cause device access timeouts. Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same values for the Attribute as were supplied in the header of the corresponding Request, except as explicitly allowed when IDO is used." Instead of copying the Attributes from the Request to the Completion, the T5 always generates Completions with zero Attributes. The receiver of a Completion whose Attributes don't match the Request may accept it (which itself seems non-compliant based on sec 2.3.2), or it may handle it as a Malformed TLP or an Unexpected Completion, which will probably lead to a device access timeout. Work around this by disabling "Relaxed Ordering" and "No Snoop" in the Root Port so it always generate Requests with zero Attributes. This does affect all other devices which are downstream of that Root Port, but these are performance optimizations that should not make a functional difference. Note that Configuration Space accesses are never supposed to have TLP Attributes, so we're safe waiting till after any Configuration Space accesses to do the Root Port "fixup". Based on original work by Casey Leedom <leedom@chelsio.com> [bhelgaas: changelog, comments, rename to pci_find_pcie_root_port(), rework to use pci_upstream_bridge() and check for Root Port device type, edit diagnostics to clarify intent and devices affected] Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
da2d03ea |
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15-Sep-2015 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Use function 0 VPD for identical functions, regular VPD for others 932c435caba8 ("PCI: Add dev_flags bit to access VPD through function 0") added PCI_DEV_FLAGS_VPD_REF_F0. Previously, we set the flag on every non-zero function of quirked devices. If a function turned out to be different from function 0, i.e., it had a different class, vendor ID, or device ID, the flag remained set but we didn't make VPD accessible at all. Flip this around so we only set PCI_DEV_FLAGS_VPD_REF_F0 for functions that are identical to function 0, and allow regular VPD access for any other functions. [bhelgaas: changelog, stable tag] Fixes: 932c435caba8 ("PCI: Add dev_flags bit to access VPD through function 0") Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> Acked-by: Myron Stowe <myron.stowe@redhat.com> Acked-by: Mark Rustad <mark.d.rustad@intel.com> CC: stable@vger.kernel.org
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#
10b4ad1a |
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24-Sep-2015 |
Ondrej Zary <linux@rainbow-software.org> |
PCI: Disable MSI on SiS 761 MSI is broken on SiS 761 chipset at least on PC Chips A31G board. No interrupts are delivered once MSI is enabled for a device. This causes hang on X11 start with a nVidia card installed (with nouveau driver). Disable MSI completely for this chipset. Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
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#
91f15fb3 |
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24-Aug-2015 |
Zhang Rui <rui.zhang@intel.com> |
PCI: Disable async suspend/resume for JMicron multi-function SATA/AHCI On multi-function JMicron SATA/PATA/AHCI devices, the PATA controller at function 1 doesn't work if it is powered on before the SATA controller at function 0. The result is that PATA doesn't work after resume, and we print messages like this: pata_jmicron 0000:02:00.1: Refused to change power state, currently in D3 irq 17: nobody cared (try booting with the "irqpoll" option) Async resume was introduced in v3.15 by 76569faa62c4 ("PM / sleep: Asynchronous threads for resume_noirq"). Prior to that, we powered on the functions in order, so this problem shouldn't happen. e6b7e41cdd8c ("ata: Disabling the async PM for JMicron chip 363/361") solved the problem for JMicron 361 and 363 devices. With async suspend disabled, we always power on function 0 before function 1. Barto then reported the same problem with a JMicron 368 (see comment #57 in the bugzilla). Rather than extending the blacklist piecemeal, disable async suspend for all JMicron multi-function SATA/PATA/AHCI devices. This quirk could stay in the ahci and pata_jmicron drivers, but it's likely the problem will occur even if pata_jmicron isn't loaded until after the suspend/resume. Making it a PCI quirk ensures that we'll preserve the power-on order even if the drivers aren't loaded. [bhelgaas: changelog, limit to multi-function, limit to IDE/ATA] Link: https://bugzilla.kernel.org/show_bug.cgi?id=81551 Reported-and-tested-by: Barto <mister.freeman@laposte.net> Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.15+
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#
27d868b5 |
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24-Aug-2015 |
Keith Busch <kbusch@kernel.org> |
PCI: Set MPS to match upstream bridge Firmware typically configures the PCIe fabric with a consistent Max Payload Size setting based on the devices present at boot. A hot-added device typically has the power-on default MPS setting (128 bytes), which may not match the fabric. The previous Linux default, in the absence of any "pci=pcie_bus_*" options, was PCIE_BUS_TUNE_OFF, in which we never touch MPS, even for hot-added devices. Add a new default setting, PCIE_BUS_DEFAULT, in which we make sure every device's MPS setting matches the upstream bridge. This makes it more likely that a hot-added device will work in a system with optimized MPS configuration. Note that if we hot-add a device that only supports 128-byte MPS, it still likely won't work because we don't reconfigure the rest of the fabric. Booting with "pci=pcie_bus_peer2peer" is a workaround for this because it sets MPS to 128 for everything. [bhelgaas: changelog, new default, rework for pci_configure_device() path] Tested-by: Keith Busch <keith.busch@intel.com> Tested-by: Jordan Hargrave <jharg93@gmail.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Yinghai Lu <yinghai@kernel.org>
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#
95e16587 |
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10-Aug-2015 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add ACS quirks for Intel I219-LM/V The Intel 100-series chipset now includes the integrated Ethernet as part of a multifunction package. The Ethernet function does not include native ACS support, but Intel confirms that the device is not capable of peer-to- peer within the package. We can therefore quirk it to expose the isolation. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: John Ronciak <john.ronciak@gmail.com>
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#
3388a614 |
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07-Aug-2015 |
Tadeusz Struk <tadeusz.struk@intel.com> |
PCI: Add quirk for Intel DH895xCC VF PCI config erratum The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with QuickAssist Technology is prematurely terminated in hardware. Workaround the issue by hard-coding the known expected next capability pointer and saving the PCIE cap into internal buffer. Patch generated against cryptodev-2.6 Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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#
7aa6ca4d |
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13-Jul-2015 |
Mark Rustad <mark.d.rustad@intel.com> |
PCI: Add VPD function 0 quirk for Intel Ethernet devices Set the PCI_DEV_FLAGS_VPD_REF_F0 flag on all Intel Ethernet device functions other than function 0, so that on multi-function devices, we will always read VPD from function 0 instead of from the other functions. [bhelgaas: changelog] Signed-off-by: Mark Rustad <mark.d.rustad@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alexander Duyck <alexander.h.duyck@redhat.com> CC: stable@vger.kernel.org
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#
46fd9625 |
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01-Jul-2015 |
Rami Rosen <ramirose@gmail.com> |
PCI: Remove a broken link in quirks.c Remove a broken link in drivers/pci/quirks.c. Signed-off-by: Rami Rosen <ramirose@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
fff905f3 |
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29-Jun-2015 |
Wei Yang <weiyang@linux.vnet.ibm.com> |
PCI: Move PCI_FIND_CAP_TTL to pci.h and use it in quirks Some quirks search for a HyperTransport capability and use a hard-coded TTL value of 48 to avoid an infinite loop. Move the definition of PCI_FIND_CAP_TTL to pci.h and use it instead of the hard-coded TTL values. [bhelgaas: changelog] Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
2b4aed1d |
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19-Jun-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Shift PCI_CLASS_NOT_DEFINED consistently with other classes The PCI class in dev->class is a three-byte value comprising a base class, sub-class, and interface type. PCI_CLASS_NOT_DEFINED includes the base class and sub-class, but not the interface type, so it should be shifted to make space for the interface. It happens that PCI_CLASS_NOT_DEFINED is zero, so it doesn't matter in the end, but we should still use it consistently with other class definitions. Treat PCI_CLASS_NOT_DEFINED as a base class/sub-class value that should appear in bits 8-23 of dev->class. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
eefaf338 |
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24-Jun-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Revert aeb30016fec3 ("PCI: add Intel USB specific reset method") Revert aeb30016fec3 ("PCI: add Intel USB specific reset method"). We checked for "dev->class == PCI_CLASS_SERIAL_USB", but dev->class contains the entire three-byte base class/sub-class/interface, while PCI_CLASS_SERIAL_USB is only the two-byte base class/sub-class. This error meant that we used the Intel device-specific reset on devices with class code 0x000c03 instead of those with class code 0x0c03xx. 0x000c03 is a reserved value in the 0x00 backwards compatibility base class and shouldn't match any devices, so I think reset_intel_generic_dev() always failed. I considered adding a shift, but I can't test it, so it's as likely to break something as to fix something. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Yu Zhao <yu.zhao@intel.com> CC: Mathias Nyman <mathias.nyman@intel.com>
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#
d1541dc9 |
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19-Jun-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Fix TI816X class code quirk In fixup_ti816x_class(), we assigned "class = PCI_CLASS_MULTIMEDIA_VIDEO". But PCI_CLASS_MULTIMEDIA_VIDEO is only the two-byte base class/sub-class and needs to be shifted to make space for the low-order interface byte. Shift PCI_CLASS_MULTIMEDIA_VIDEO to set the correct class code. Fixes: 63c4408074cb ("PCI: Add quirk for setting valid class for TI816X Endpoint") Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Hemant Pedanekar <hemantp@ti.com>
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#
e6323e3c |
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19-Jun-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Fix generic NCR 53c810 class code quirk In the generic quirk fixup_rev1_53c810(), added by a5312e28c195 ("[PATCH] PCI: NCR 53c810 quirk"), we assigned "class = PCI_CLASS_STORAGE_SCSI". But PCI_CLASS_STORAGE_SCSI is only the two-byte base class/sub-class and needs to be shifted to make space for the low-order interface byte. Furthermore, we had a similar quirk, pci_fixup_ncr53c810(), for arch/x86, which assigned class correctly. The arch code is linked before the PCI core, so arch quirks run before generic quirks. Therefore, on x86, the x86 arch quirk ran first, and the generic quirk did nothing because it saw that dev->class was already set. But on other arches, the generic quirk set the wrong class code. Fix the generic quirk to set the correct class code and remove the now-unnecessary x86-specific quirk. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Matthew Wilcox <matthew@wil.cx>
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#
cd76d10b |
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19-Jun-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Use PCI_CLASS_SERIAL_USB instead of bare number be6646bfbaec ("PCI: Prevent xHCI driver from claiming AMD Nolan USB3 DRD device") added a quirk to override the PCI class code of the AMD Nolan device. Use PCI_CLASS_SERIAL_USB instead of a bare number to improve greppability. Also add a log message about what we're doing. No functional change except the new message. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Huang Rui <ray.huang@amd.com> CC: Jason Chang <jason.chang@amd.com> CC: Felipe Balbi <balbi@ti.com>
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#
3657cebd |
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19-Jun-2015 |
Krzysztof =?utf-8?Q?Ha=C5=82asa?= <khalasa@piap.pl> |
PCI: Add quirk for Intersil/Techwell TW686[4589] AV capture cards Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) class code. Fix it. Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
4a118753 |
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19-Jun-2015 |
Srinidhi Kasagar <srinidhi.kasagar@intel.com> |
PCI: Remove Intel Cherrytrail D3 delays Just like Haswell, Intel Atom Cherrytrail does not need the default 10ms d3_delay imposed by the PCI specification. Expand quirk_remove_d3_delay() to apply to Cherrytrail devices, so we can ignore the 10ms delay before entering or exiting D3 suspend. [bhelgaas: changelog, comment] Signed-off-by: Srinidhi Kasagar <srinidhi.kasagar@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
247de694 |
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21-May-2015 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
PCI: Add function 1 DMA alias quirk for Marvell 9120 Marvell 9120 SATA controller has the same issue as a number of others, so use the same quirk for this one. The other quirks were added by cc346a4714a5 ("PCI: Add function 1 DMA alias quirk for Marvell devices"). Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Williamson <alex.williamson@redhat.com>
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#
dca230d1 |
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01-May-2015 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add ACS quirks for Intel 9-series PCH root ports Intel confirms that 9-series chipset root ports provide ACS-equivalent isolation when configured via the existing Intel PCH ACS quirk setup. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Don Dugger <donald.d.dugger@intel.com>
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#
96803199 |
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07-May-2015 |
Michael S. Tsirkin <mst@redhat.com> |
PCI/MSI: Drop pci_msi_off() calls from quirks The PCI core now disables MSI and MSI-X for all devices during enumeration regardless of CONFIG_PCI_MSI. Remove device-specific code to disable MSI/MSI-X. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
1f934641 |
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13-Apr-2015 |
Thomas Gleixner <tglx@linutronix.de> |
x86/irq: Remove sis apic bug workaround The SiS apic bug workaround is now obsolete as we cache the register values for performance reasons. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Cc: Grant Likely <grant.likely@linaro.org> Link: http://lkml.kernel.org/r/1428978610-28986-22-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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#
c89ac443 |
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31-Mar-2015 |
Darrick J. Wong <darrick.wong@oracle.com> |
PCI: Fix typo in Thunderbolt kernel message Fix a typo in one of the kernel messages. Signed-off-by: Darrick J. Wong <darrick.wong@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
d748804f |
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20-Mar-2015 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add ACS quirks for Intel 1G NICs Intel has verified that there is no peer-to-peer between functions for the below selection of 82580, 82576, 82575, I350, and 82571 multi-port devices. This adds the necessary quirks to consider the functions isolated from each other. 82571 quad-port devices are omitted due to likely lack of ACS/isolation in the onboard switch, rendering quirks for the downstream endpoints useless. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: John Ronciak <john.ronciak@intel.com>
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#
06cf35f9 |
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03-Feb-2015 |
Myron Stowe <myron.stowe@redhat.com> |
PCI: Handle read-only BARs on AMD CS553x devices Some AMD CS553x devices have read-only BARs because of a firmware or hardware defect. There's a workaround in quirk_cs5536_vsa(), but it no longer works after 36e8164882ca ("PCI: Restore detection of read-only BARs"). Prior to 36e8164882ca, we filled in res->start; afterwards we leave it zeroed out. The quirk only updated the size, so the driver tried to use a region starting at zero, which didn't work. Expand quirk_cs5536_vsa() to read the base addresses from the BARs and hard-code the sizes. On Nix's system BAR 2's read-only value is 0x6200. Prior to 36e8164882ca, we interpret that as a 512-byte BAR based on the lowest-order bit set. Per datasheet sec 5.6.1, that BAR (MFGPT) requires only 64 bytes; use that to avoid clearing any address bits if a platform uses only 64-byte alignment. [bhelgaas: changelog, reduce BAR 2 size to 64] Fixes: 36e8164882ca ("PCI: Restore detection of read-only BARs") Link: https://bugzilla.kernel.org/show_bug.cgi?id=85991#c4 Link: http://support.amd.com/TechDocs/31506_cs5535_databook.pdf Link: http://support.amd.com/TechDocs/33238G_cs5536_db.pdf Reported-and-tested-by: Nix <nix@esperi.org.uk> Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v.2.6.27+
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#
78e88358 |
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22-Jan-2015 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add Wellsburg (X99) to Intel PCH root port ACS quirk Intel has confirmed that the Wellsburg chipset, while not reporting ACS, does provide the proper isolation through the RCBA/BSPR registers, so the same quirk works for this set of device IDs. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Don Dugger <donald.d.dugger@intel.com>
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#
d3d2ab43 |
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13-Jan-2015 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add DMA alias quirk for Adaptec 3405 The Adaptec 3405 is actually an Intel 80333 I/O processor where the exposed device at 0e.0 is actually the address translation unit of the I/O processor and a hidden, private device at 01.0 masters the DMA for the device. Create a fixed alias between the exposed and hidden devfn so we can enable the IOMMU. Scenarios like this are potentially likely for any device incorporating this I/O processor, so this little bit of abstraction with the fixed alias table should make future additions trivial. Without this fix, booting a system with the Intel IOMMU enabled and an Adaptec 3405 at 02:0e.0 results in a flood of errors like this: dmar: DRHD: handling fault status reg 3 dmar: DMAR:[DMA Write] Request device [02:01.0] fault addr ffbff000 DMAR:[fault reason 02] Present bit in context entry is clear [bhelgaas: changelog, comment] Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Adaptec OEM Raid Solutions <aacraid@adaptec.com>
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#
6a3763d1 |
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12-Jan-2015 |
Vasundhara Volam <vasundhara.volam@emulex.com> |
PCI: Add ACS quirk for Emulex NICs As Skyhawk and BE3-R (both multi-function devices) don't advertise the PCI-ACS capability, the vfio driver places all the functions of these devices in a single IOMMU group. Attaching (via PCI-passthru) two different Skyhawk/BE3-R partitions (nPAR, Flex, etc. PFs) using vfio, to different guests doesn't work as vfio only allows functions in *different* IOMMU groups to be assigned to different guests. As peer-to-peer access between PFs in Skyhawk/BE3-R is not possible, we can treat them as "fully isolated" even though the device doesn't advertise ACS. Add a PCI quirk for Skyhawk and BE3-R chips to fix this problem. Signed-off-by: Vasundhara Volam <vasundhara.volam@emulex.com> Signed-off-by: Sathya Perla <sathya.perla@emulex.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Williamson <alex.williamson@redhat.com>
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#
d84f3174 |
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21-Nov-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Mark AMD/ATI VGA devices that don't reset on D3hot->D0 transition Some AMD/ATI GPUs report NoSoftRst- to indicate that they perform a reset when software transitions them from D3hot to D0, but there is no apparent effect on the device: the monitor remains synced and the framebuffer contents are retained. Callers of pci_reset_function() don't necessarily have a way to validate whether a reset was effective, so we don't want to rely on NoSoftRst if it's known to be inaccurate. Returning an error in such cases appears to be the better option. For users like vfio-pci, this allows the driver to escalate to the bus reset interfaces. If a device lives on the root bus, there's really no further escalation path, so we exempt PM reset as potentially better than nothing. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
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#
c3e59ee4 |
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15-Jan-2015 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Mark Atheros AR93xx to avoid bus reset Reports against the TL-WDN4800 card indicate that PCI bus reset of this Atheros device cause system lock-ups and resets. I've also been able to confirm this behavior on multiple systems. The device never returns from reset and attempts to access config space of the device after reset result in hangs. Blacklist bus reset for the device to avoid this issue. [bhelgaas: This regression appeared in v3.14. Andreas bisected it to 425c1b223dac ("PCI: Add Virtual Channel to save/restore support"), but we don't understand the mechanism by which that commit affects the reset path.] [bhelgaas: changelog, references] Link: http://lkml.kernel.org/r/20140923210318.498dacbd@dualc.maya.org Reported-by: Andreas Hartmann <andihartmann@freenet.de> Tested-by: Andreas Hartmann <andihartmann@freenet.de> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.14+
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#
be6646bf |
|
30-Oct-2014 |
Huang Rui <ray.huang@amd.com> |
PCI: Prevent xHCI driver from claiming AMD Nolan USB3 DRD device The AMD Nolan (NL) SoC contains a DesignWare USB3 Dual-Role Device that can be operated either as a USB Host or a USB Device. In the AMD NL platform, this device ([1022:7912]) has a class code of PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will claim it. But the dwc3 driver is a more specific driver for this device, and we'd prefer to use it instead of xhci. To prevent xhci from claiming the device, change the class code to 0x0c03fe, which the PCI r3.0 spec defines as "USB device (not host controller)". The dwc3 driver can then claim it based on its Vendor and Device ID. Suggested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jason Chang <jason.chang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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#
3587e625 |
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02-Oct-2014 |
Marti Raudsepp <marti@juffo.org> |
PCI: Add ACS quirk for AMD A88X southbridge devices AMD has confirmed that peer-to-peer between two southbridge functions does not occur. Add a quirk to indicate that these functions are isolated even though they don't have an ACS capability. Link: https://bugzilla.kernel.org/show_bug.cgi?id=81841 Signed-off-by: Marti Raudsepp <marti@juffo.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joel Schopp <joel.schopp@amd.com>
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#
100ebb2c |
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26-Sep-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add ACS quirk for Intel 10G NICs Intel has verified there is no peer-to-peer between functions for the below selection of 82598, 82599, and X520 10G NICs. These NICs lack an ACS capability, so we're not able to determine this isolation without the help of quirks. Generalize the Solarflare quirk and add these Intel 10G NICs. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: John Ronciak <John.ronciak@intel.com>
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#
89b51cb5 |
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17-Sep-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add ACS quirk for Solarflare SFC9120 & SFC9140 Solarflare confirms that these devices do not allow peer-to-peer between functions. Quirk them to allow IOMMU grouping to expose this isolation. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Robert Stonehouse <rstonehouse@solarflare.com>
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#
5d8f4c9f |
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17-Sep-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Remove unused pci_get_dma_source() pci_get_dma_source() is unused, so remove it. We now have dma_alias_devfn() to describe this. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
9fe373f9 |
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20-Aug-2014 |
Douglas Lehr <dllehr@us.ibm.com> |
PCI: Increase IBM ipr SAS Crocodile BARs to at least system page size The Crocodile chip occasionally comes up with 4k and 8k BAR sizes. Due to an erratum, setting the SR-IOV page size causes the physical function BARs to expand to the system page size. Since ppc64 uses 64k pages, when Linux tries to assign the smaller resource sizes to the now 64k BARs the address will be truncated and the BARs will overlap. Force Linux to allocate the resource as a full page, which avoids the overlap. [bhelgaas: print expanded resource, too] Signed-off-by: Douglas Lehr <dllehr@us.ibm.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Milton Miller <miltonm@us.ibm.com> CC: stable@vger.kernel.org
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#
11e42532 |
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05-Sep-2014 |
Gavin Shan <gwshan@linux.vnet.ibm.com> |
PCI: Assume all Mellanox devices have broken INTx masking The VFIO driver routes LSI interrupts by capturing, masking, and then delivering. When passing though Mellanox adapters from host to guest, interrupt storm are reported from host and guest. That's because the PCI command register INTx Disable bit doesn't work on Mellanox devices. # lspci | grep Mellanox 0001:05:00.0 Ethernet controller: Mellanox Technologies MT27500 Family [ConnectX-3] 0005:01:00.0 Ethernet controller: Mellanox Technologies MT26448 [ConnectX EN 10GigE, PCIe 2.0 5GT/s] (rev b0) Amir Vadai confirmed that all Mellanox devices have same problem. The patch marks broken INTx masking for all Mellanox adapters. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Amir Vadai <amirv@mellanox.com>
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#
8ab4abbe |
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05-Jul-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add bridge DMA alias quirk for Intel 82801 bridge This bridge sometimes shows up as a root complex device and sometimes as a discrete PCIe-to-PCI bridge. Testing indicates that in the latter case, we need to enable the PCIe bridge DMA alias quirk. Reported-by: Milos Kaurin <milos.kaurin@gmail.com> Tested-by: Milos Kaurin <milos.kaurin@gmail.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
1df5172c |
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03-Jun-2014 |
Andreas Noever <andreas.noever@gmail.com> |
PCI: Suspend/resume quirks for Apple thunderbolt Add two quirks to support thunderbolt suspend/resume on Apple systems. We need to perform two different actions during suspend and resume: The whole controller has to be powered down before suspend. If this is not done then the native host interface device will be gone after resume if a thunderbolt device was plugged in before suspending. The controller represents itself as multiple PCI devices/bridges. To power it down we hook into the upstream bridge of the controller and call the magic ACPI methods. Power will be restored automatically during resume (by the firmware presumably). During resume we have to wait for the native host interface to reestablish all pci tunnels. Since there is no parent-child relationship between the NHI and the bridges we have to explicitly wait for them using device_pm_wait_for_dev. We do this in the resume_noirq phase of the downstream bridges of the controller (which lead into the thunderbolt tunnels). Signed-off-by: Andreas Noever <andreas.noever@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
7d2a01b8 |
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03-Jun-2014 |
Andreas Noever <andreas.noever@gmail.com> |
PCI: Add pci_fixup_suspend_late quirk pass Add pci_fixup_suspend_late as a new pci_fixup_pass. The pass is called from suspend_noirq and poweroff_noirq. Using the same pass for suspend and hibernate is consistent with resume_early which is called by resume_noirq and restore_noirq. The new quirk pass is required for Thunderbolt support on Apple hardware. Signed-off-by: Andreas Noever <andreas.noever@gmail.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
c2e0fb96 |
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03-Jun-2014 |
Jérôme Carretero <cJ-ko@zougloub.eu> |
PCI: Add function 1 DMA alias quirk for HighPoint RocketRaid 642L This device uses function 1 as the PCIe requester ID. This vendor has similar boards based on the same Marvell 88SE9235 chipset, but this patch was only tested with the 642L. Tested on ASUS Sabertooth 990FX (AMD). Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679 Signed-off-by: Jérôme Carretero <cJ-ko@zougloub.eu> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Williamson <alex.williamson@redhat.com>
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#
227f0647 |
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18-Apr-2014 |
Ryan Desfosses <ryan@desfo.org> |
PCI: Merge multi-line quoted strings Merge quoted strings that are broken across lines into a single entity. The compiler merges them anyway, but checkpatch complains about it, and merging them makes it easier to grep for strings. No functional change. [bhelgaas: changelog, do the same for everything under drivers/pci] Signed-off-by: Ryan Desfosses <ryan@desfo.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
3c78bc61 |
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18-Apr-2014 |
Ryan Desfosses <ryan@desfo.org> |
PCI: Whitespace cleanup Fix various whitespace errors. No functional change. [bhelgaas: fix other similar problems] Signed-off-by: Ryan Desfosses <ryan@desfo.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
98ca50db |
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09-Jun-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add bridge DMA alias quirk for ITE bridge The ITE 8892 is a PCIe-to-PCI bridge but doesn't have a PCIe capability. Quirk it so we can figure out the DMA alias for devices below the bridge, so they work correctly with an IOMMU. [bhelgaas: add changelog] Link: https://bugzilla.kernel.org/show_bug.cgi?id=73551 Reported-by: Ronald <rwarsow@gmx.de> Tested-by: Ronald <rwarsow@gmx.de> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
ebdb51eb |
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22-May-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add bridge DMA alias quirk for ASMedia and Tundra bridges The quirk is intended to be extremely generic, but we only apply it to known offending devices. Link: https://bugzilla.kernel.org/show_bug.cgi?id=44881 Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
cc346a47 |
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28-May-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add function 1 DMA alias quirk for Marvell devices Several Marvell devices and a JMicron device have a similar DMA requester ID problem to Ricoh, except they use function 1 as the PCIe requester ID. Add a quirk for these to populate the DMA alias with the correct devfn. Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679 Tested-by: George Spelvin <linux@horizon.com> Tested-by: Andreas Schrägle <ajs124.ajs124@gmail.com> Tested-by: Tobias N <qemu@suppser.de> Tested-by: <daxcore@online.de> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
ec637fb2 |
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22-May-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add function 0 DMA alias quirk for Ricoh devices The existing quirk for these devices (pci_get_dma_source()) doesn't really solve the problem; re-implement it using the DMA alias iterator. We'll come back later and remove the existing quirk and dma_source interface. Note that device ID 0xe822 is typically function 0 and 0xe230 has been tested to not need the quirk and are therefore removed versus the equivalent dma_source quirk. If there exist in other configurations we can re-add them. Link: https://bugzilla.redhat.com/show_bug.cgi?id=605888 Tested-by: Pat Erley <pat-lkml@erley.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
3cb30b73 |
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01-May-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Mark RTL8110SC INTx masking as broken INTx masking does not work on this device. To see this, configure the network device UP on an active network, note that the interrupt count continues to increment for the device in /proc/interrupts. Use setpci to set the PCI_COMMAND_INTX_DISABLE bit in the PCI_COMMAND register. As expected, the interrupt count ceases to increment. However, reading the PCI_STATUS_INTERRUPT bit of the PCI_STATUS register does not indicate that interrupts are pending and clearing PCI_COMMAND_INTX_DISABLE in the PCI_COMMAND register does not allow the device to continue operation. This does not affect operation of the host r8169 driver, but it does prevent the device from being functional when assigned to a VM, such as with QEMU and VFIO. The guest driver successfully probes the device, but there is no traffic. Mark INTx masking as broken, allowing the more restrictive APIC masking to be used instead. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
7c82126a |
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07-Apr-2014 |
Thomas Jarosch <thomas.jarosch@intra2net.com> |
PCI: Add new ID for Intel GPU "spurious interrupt" quirk After a CPU upgrade while keeping the same mainboard, we faced "spurious interrupt" problems again. It turned out that the new CPU also featured a new GPU with a different PCI ID. Add this PCI ID to the quirk table. Probably all other Intel GPU PCI IDs are affected, too, but I don't want to add them without a test system. See f67fd55fa96f ("PCI: Add quirk for still enabled interrupts on Intel Sandy Bridge GPUs") for some history. [bhelgaas: add f67fd55fa96f reference, stable tag] Signed-off-by: Thomas Jarosch <thomas.jarosch@intra2net.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.4+
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#
1a30fd0d |
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31-Mar-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add Patsburg (X79) to Intel PCH root port ACS quirk Intel has updated Red Hat bz1037684 to note that X79 PCH root ports also provide isolation and the same ACS quirks apply. Some sources indicate additional device IDs for X79, but this patch includes only the ones specifically identified by Intel: https://bugzilla.redhat.com/show_bug.cgi?id=1037684#c11 Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Don Dugger <donald.d.dugger@intel.com>
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#
bd064f0a |
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26-Feb-2014 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Mark resources as IORESOURCE_UNSET if we can't assign them When assigning addresses to resources, mark them with IORESOURCE_UNSET before we start and clear IORESOURCE_UNSET if assignment is successful. That means that if we print the resource during assignment, we will show the size, not a meaningless address. Also, clear IORESOURCE_UNSET if we do assign an address, so we print the address when it is valid. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
d99321b6 |
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03-Feb-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Enable quirks for PCIe ACS on Intel PCH root ports Many of the currently available Intel PCH-based root ports do not provide PCIe ACS capabilities. Without this, we must assume that peer-to-peer traffic between multifunction root ports and between devices behind root ports is possible. This lack of isolation is exposed by grouping the devices together in the same IOMMU group. If we want to expose these devices to userspace, vfio uses IOMMU groups as the unit of ownership, thus making it very difficult to assign individual devices to separate users. The good news is that the chipset does provide ACS-like isolation capabilities, but we do need to verify and enable those capabilities if the BIOS has not done so. This patch implements the device specific enabling and testing of equivalent ACS function for these devices. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Don Dugger <donald.d.dugger@intel.com>
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#
2c744244 |
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03-Feb-2014 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add device-specific PCI ACS enable Some devices support PCI ACS-like features, but don't report it using the standard PCIe capabilities. We already provide hooks for device-specific testing of ACS, but not for device-specific enabling of ACS. This provides that setup hook. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
fc279850 |
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09-Dec-2013 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev These interfaces: pcibios_resource_to_bus(struct pci_dev *dev, *bus_region, *resource) pcibios_bus_to_resource(struct pci_dev *dev, *resource, *bus_region) took a pci_dev, but they really depend only on the pci_bus. And we want to use them in resource allocation paths where we have the bus but not a device, so this patch converts them to take the pci_bus instead of the pci_dev: pcibios_resource_to_bus(struct pci_bus *bus, *bus_region, *resource) pcibios_bus_to_resource(struct pci_bus *bus, *resource, *bus_region) In fact, with standard PCI-PCI bridges, they only depend on the host bridge, because that's the only place address translation occurs, but we aren't going that far yet. [bhelgaas: changelog] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
dad33750 |
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27-Nov-2013 |
Dave Jones <davej@redhat.com> |
remove obsolete references to powertweak This tool hasn't been maintained in over a decade, and is pretty much useless these days. Let's pretend it never happened. Also remove a long-dead email address. Signed-off-by: Dave Jones <davej@fedoraproject.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
f7625980 |
|
14-Nov-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Fix whitespace, capitalization, and spelling errors Fix whitespace, capitalization, and spelling errors. No functional change. I know "busses" is not an error, but "buses" was more common, so I used it consistently. Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus()) Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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#
b8cac70a |
|
10-Sep-2013 |
Todd E Brandt <todd.e.brandt@linux.intel.com> |
PCI: Remove Intel Haswell D3 delays The latest Intel Haswell chipsets have a hardware optimization which allows on-chip PCI devices to ignore the 10ms delay before entering or exiting D3 suspend. This patch implements the optimization as a PCI quirk, since we want tight control over which devices use it. This way we can test each device individually to be sure there are no issues before we enable the quirk. The first set of devices are from the Haswell platform, which includes every PCI device that is on the northbridge and southbridge. This patch reduces the Haswell suspend time from 93 ms to 47 ms and resume time from 160 ms to 64 ms. Signed-off-by: Todd Brandt <todd.e.brandt@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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#
4d708ab0 |
|
06-Aug-2013 |
Casey Leedom <leedom@chelsio.com> |
PCI: Use pci_wait_for_pending_transaction() instead of for loop New routine has been added to avoid duplication of code to wait for pending PCI transactions to complete. This makes use of that function. Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
2c6217e0 |
|
06-Aug-2013 |
Casey Leedom <leedom@chelsio.com> |
PCI: Chelsio quirk: Enable Bus Master during Function-Level Reset T4 can wedge if there are DMAs in flight within the chip and Bus Master has been disabled. We need to have it on till the Function Level Reset completes. T4 can also suffer a Head Of Line blocking problem if MSI-X interrupts are disabled before the FLR has completed. Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
15b100df |
|
27-Jun-2013 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Claim ACS support for AMD southbridge devices AMD confirmed that peer-to-peer between these devices is not possible. We can therefore claim that they support a subset of ACS. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Donald Dutile <ddutile@redhat.com>
|
#
728cdb75 |
|
18-Jun-2013 |
Yijing Wang <wangyijing@huawei.com> |
PCI: Use pdev->pm_cap instead of pci_find_capability(..,PCI_CAP_ID_PM) PCI PM cap register offset has been saved in pci_pm_init(), so we can use pdev->pm_cap instead of using pci_find_capability(..) here. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
|
#
fafe5c3d8 |
|
03-Jun-2013 |
Shane Huang <shane.huang@amd.com> |
ahci: Add AMD CZ SATA device ID To add AMD CZ SATA controller device ID of IDE mode. [bhelgaas: drop pci_ids.h update] Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
|
#
12b03188 |
|
06-May-2013 |
Jon Mason <jon.mason@intel.com> |
PCI: Work around Ivytown NTB BAR size issue Certain NTB devices have a hardware erratum where, regardless of pre-configured value, reading the BAR size returns 4096. To work around this issue, add a PCI quirk to read the appropriate values from an alternative register in PCI config space and move the resource endpoints to the appropriate location. Signed-off-by: Jon Mason <jon.mason@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
65195c76 |
|
11-Apr-2013 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Clean up quirk_io_region Before every call of quirk_io_region(), pci_read_config_word() is called. We can fold that call into quirk_io_region() to make code more readable. [bhelgaas: changelog, fill bus_region directly rather than copying from res] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
70588818 |
|
07-Mar-2013 |
Xiong Huang <xiong@qca.qualcomm.com> |
PCI: Add MSI INTX_DISABLE quirks for AR8161/AR8162/AR8171/AR8172/E210X The following PCIe devices with revision lower than 0x18 have this bug: AR8161(1091)/AR8162(1090)/AR8171(10A1)/AR8172(10A0)/E210X(E091). Signed-off-by: Huang,Xiong <xiong@qca.qualcomm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Wei Yang <weiyang@linux.vnet.ibm.com>
|
#
812089e0 |
|
01-Dec-2012 |
Andy Lutomirski <luto@amacapital.net> |
PCI: Reduce Ricoh 0xe822 SD card reader base clock frequency to 50MHz Otherwise it fails like this on cards like the Transcend 16GB SDHC card: mmc0: new SDHC card at address b368 mmcblk0: mmc0:b368 SDC 15.0 GiB mmcblk0: error -110 sending status command, retrying mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb0 Tested on my Lenovo x200 laptop. [bhelgaas: changelog] Signed-off-by: Andy Lutomirski <luto@amacapital.net> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Chris Ball <cjb@laptop.org> CC: Manoj Iyer <manoj.iyer@canonical.com> CC: stable@vger.kernel.org
|
#
15856ad5 |
|
21-Nov-2012 |
Bill Pemberton <wfp5p@virginia.edu> |
PCI: Remove __dev* markings CONFIG_HOTPLUG is going away as an option so __devexit_p, __devint, __devinitdata, __devinitconst, and _devexit are no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
2794bb28 |
|
29-Oct-2012 |
Ian Abbott <abbotti@mev.co.uk> |
PCI: Add PLX PCI 9050 workaround for some Meilhaus DAQ cards The Meilhaus ME-2000i and ME-2600i data acquisition cards supported by the Comedi "me_daq" driver use the PLX PCI 9050 PCI Target bridge chip affected by the bug that prevents the chip's local configuration registers being read from BAR0 or BAR1 base addresses that are an odd multiple of 128 bytes. Use the PLX PCI 9050 quirk handler for these devices to re-allocate affected regions to a 256-byte boundary. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
21c5fd97 |
|
30-Oct-2012 |
Ian Abbott <abbotti@mev.co.uk> |
PCI: Add workaround for PLX PCI 9050 BAR alignment erratum The PLX PCI 9050 PCI Target bridge controller has a bug that prevents its local configuration registers being read through BAR0 (memory) or BAR1 (i/o) if the base address lies on an odd 128-byte boundary, i.e. if bit 7 of the base address is non-zero. This bug is described in the PCI 9050 errata list, version 1.4, May 2005. It was fixed in the pin-compatible PCI 9052, which can be distinguished from the PCI 9050 by checking the revision in the PCI header, which is hard-coded for these chips. Workaround the problem by re-allocating the affected regions to a 256-byte boundary. Note that BAR0 and/or BAR1 may have been disabled (size 0) during initialization of the PCI chip when its configuration is read from a serial EEPROM. Currently, the fix-up has only been used for devices with the default vendor and device ID of the PLX PCI 9050. The PCI 9052 shares the same default device ID as the PCI 9050 but they have different PCI revision codes. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
76b57c67 |
|
22-Aug-2012 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Wait for pending transactions to complete before 82599 FLR Before initiating an FLR, we should wait for completion of any outstanding non-posted requests. See PCIe spec r3.0, sec 6.6.2. This makes reset_intel_82599_sfp_virtfn() very similar to the generic pcie_flr(). The only difference is that the 82599 doesn't report FLR support in the VF Device Capability register. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
59875ae4 |
|
24-Jul-2012 |
Jiang Liu <jiang.liu@huawei.com> |
PCI/core: Use PCI Express Capability accessors Use PCI Express Capability access functions to simplify core. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
12962267 |
|
07-Apr-2012 |
Chris Metcalf <cmetcalf@tilera.com> |
arch/tile: tilegx PCI root complex support This change implements PCIe root complex support for tilegx using the kernel support layer for accessing the TRIO hardware shim. Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> [changes in 07487f3] Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
|
#
95df8b87 |
|
13-Jul-2012 |
Myron Stowe <myron.stowe@redhat.com> |
PCI: fix undefined reference to 'pci_fixup_final_inited' My "PCI: Integrate 'pci_fixup_final' quirks into hot-plug paths" patch introduced an undefined reference to 'pci_fixup_final_inited' when CONFIG_PCI_QUIRKS is not enabled (on x86_64): drivers/built-in.o: In function `pci_bus_add_device': (.text+0x4f62): undefined reference to `pci_fixup_final_inited' This patch removes the external reference ending up with a result closer to what we ultimately want when the boot path issues described in the original patch are resolved. References: https://lkml.org/lkml/2012/7/9/542 Original, offending, patch https://lkml.org/lkml/2012/7/12/338 Randy's catch Reported-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Randy Dunlap <rdunlap@xenotime.net>
|
#
dbf0e4c7 |
|
09-Jul-2012 |
Alan Stern <stern@rowland.harvard.edu> |
PCI: EHCI: fix crash during suspend on ASUS computers Quite a few ASUS computers experience a nasty problem, related to the EHCI controllers, when going into system suspend. It was observed that the problem didn't occur if the controllers were not put into the D3 power state before starting the suspend, and commit 151b61284776be2d6f02d48c23c3625678960b97 (USB: EHCI: fix crash during suspend on ASUS computers) was created to do this. It turned out this approach messed up other computers that didn't have the problem -- it prevented USB wakeup from working. Consequently commit c2fb8a3fa25513de8fedb38509b1f15a5bbee47b (USB: add NO_D3_DURING_SLEEP flag and revert 151b61284776be2) was merged; it reverted the earlier commit and added a whitelist of known good board names. Now we know the actual cause of the problem. Thanks to AceLan Kao for tracking it down. According to him, an engineer at ASUS explained that some of their BIOSes contain a bug that was added in an attempt to work around a problem in early versions of Windows. When the computer goes into S3 suspend, the BIOS tries to verify that the EHCI controllers were first quiesced by the OS. Nothing's wrong with this, but the BIOS does it by checking that the PCI COMMAND registers contain 0 without checking the controllers' power state. If the register isn't 0, the BIOS assumes the controller needs to be quiesced and tries to do so. This involves making various MMIO accesses to the controller, which don't work very well if the controller is already in D3. The end result is a system hang or memory corruption. Since the value in the PCI COMMAND register doesn't matter once the controller has been suspended, and since the value will be restored anyway when the controller is resumed, we can work around the BIOS bug simply by setting the register to 0 during system suspend. This patch (as1590) does so and also reverts the second commit mentioned above, which is now unnecessary. In theory we could do this for every PCI device. However to avoid introducing new problems, the patch restricts itself to EHCI host controllers. Finally the affected systems can suspend with USB wakeup working properly. Reference: https://bugzilla.kernel.org/show_bug.cgi?id=37632 Reference: https://bugzilla.kernel.org/show_bug.cgi?id=42728 Based-on-patch-by: AceLan Kao <acelan.kao@canonical.com> Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Tested-by: Dâniel Fraga <fragabr@gmail.com> Tested-by: Javier Marcet <jmarcet@gmail.com> Tested-by: Andrey Rahmatullin <wrar@wrar.name> Tested-by: Oleksij Rempel <bug-track@fisher-privat.net> Tested-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Cc: stable <stable@vger.kernel.org> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
735bff10 |
|
09-Jul-2012 |
Myron Stowe <myron.stowe@redhat.com> |
PCI: call final fixups hot-added devices Final fixups are currently applied only at boot-time by pci_apply_final_quirks(), which is an fs_initcall(). Hot-added devices don't get these fixups, so they may not be completely initialized. This patch makes us run final fixups for hot-added devices in pci_bus_add_device() just before the new device becomes eligible for driver binding. This patch keeps the fs_initcall() for devices present at boot because we do resource assignment between pci_bus_add_device and the fs_initcall(), and we don't want to break any fixups that depend on that assignment. This is a design issue that may be addressed in the future -- any resource assignment should be done *before* device_add(). [bhelgaas: changelog] Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
3274c8eb |
|
09-Jul-2012 |
Myron Stowe <myron.stowe@redhat.com> |
PCI: move final fixups from __init to __devinit Final fixups are executed during device enumeration. If we support hotplug, this may be after boot, so final fixups cannot be __init. [bhelgaas: changelog] Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
2b28ae19 |
|
09-Jul-2012 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2) 9d265124d051 and 15a260d53f7c added quirks for P2P bridges that support I/O windows that start/end at 1K boundaries, not just the 4K boundaries defined by the PCI spec. For details, see the IOBL_ADR register and the EN1K bit in the CNF register in the Intel 82870P2 (P64H2). These quirks complicate the code that reads P2P bridge windows (pci_read_bridge_io() and pci_cfg_fake_ranges()) because the bridge I/O resource is updated in the HEADER quirk, in pci_read_bridge_io(), in pci_setup_bridge(), and again in the FINAL quirk. This is confusing and makes it impossible to reassign the bridge windows after FINAL quirks are run. This patch adds support for 1K windows in the generic paths, so the HEADER quirk only has to enable this support. The FINAL quirk, which used to undo damage done by pci_setup_bridge(), is no longer needed. This removes "if (!res->start) res->start = ..." from pci_read_bridge_io(); that was part of 9d265124d051 to avoid overwriting the resource filled in by the quirk. Since pci_read_bridge_io() itself now knows about granularity, the quirk no longer updates the resource and this test is no longer needed. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
25e742b2 |
|
09-Jul-2012 |
Myron Stowe <myron.stowe@redhat.com> |
PCI: never discard enable/suspend/resume_early/resume fixups The enable/suspend/resume_early/resume fixups can be called at any time, so they can't be __init or __devinit. [bhelgaas: changelog] Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
dff3aef7 |
|
09-Jul-2012 |
Myron Stowe <myron.stowe@redhat.com> |
PCI: release temporary reference in __nv_msi_ht_cap_quirk() __nv_msi_ht_cap_quirk() acquires a temporary reference via 'pci_get_bus_and_slot()' that is never released. This patch releases the temporary reference. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
2729d5b1 |
|
09-Jul-2012 |
Myron Stowe <myron.stowe@redhat.com> |
PCI: restructure 'pci_do_fixups()' This patch restructures pci_do_fixups()'s quirk invocations in the style of initcall_debug_start() and initcall_debug_report(), so we have only one call site for the quirk. [bhelgaas: changelog] Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
0bdb3b21 |
|
07-Jun-2012 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: add Ralink RT2800 broken INTx masking quirk Passes pci_intx_mask_supported test but continues to send interrupts as discovered through VFIO-based device assignment. http://www.spinics.net/lists/kvm/msg73738.html [bhelgaas: use HEADER, not FINAL, which is currently broken for hotplug] Tested-by: Andreas Hartmann <andihartmann@01019freenet.de> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
de509f9f |
|
07-Jun-2012 |
Jan Kiszka <jan.kiszka@siemens.com> |
PCI: add Chelsio T310 10GbE NIC broken INTx masking quirk According to http://thread.gmane.org/gmane.comp.emulators.kvm.devel/91388 the T310 does not properly support INTx masking as it fails to keep the PCI_STATUS_INTERRUPT bit updated once the interrupt is masked. Mark this adapter as broken so that pci_intx_mask_supported won't report it as compatible. [bhelgaas: use HEADER, not FINAL, which is currently broken for hotplug] Tested-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
fbebb9fd |
|
16-Jun-2012 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: add infrastructure for devices with broken INTx masking pci_intx_mask_supported() assumes INTx masking is supported if the PCI_COMMAND_INTX_DISABLE bit is writable. But when that bit is set, some devices don't actually mask INTx or update PCI_STATUS_INTERRUPT as we expect. This patch adds a way for quirks to identify these broken devices. [bhelgaas: split out from Chelsio quirk addition] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
c2fb8a3f |
|
13-Jun-2012 |
Alan Stern <stern@rowland.harvard.edu> |
USB: add NO_D3_DURING_SLEEP flag and revert 151b61284776be2 This patch (as1558) fixes a problem affecting several ASUS computers: The machine crashes or corrupts memory when going into suspend if the ehci-hcd driver is bound to any controllers. Users have been forced to unbind or unload ehci-hcd before putting their systems to sleep. After extensive testing, it was determined that the machines don't like going into suspend when any EHCI controllers are in the PCI D3 power state. Presumably this is a firmware bug, but there's nothing we can do about it except to avoid putting the controllers in D3 during system sleep. The patch adds a new flag to indicate whether the problem is present, and avoids changing the controller's power state if the flag is set. Runtime suspend is unaffected; this matters only for system suspend. However as a side effect, the controller will not respond to remote wakeup requests while the system is asleep. Hence USB wakeup is not functional -- but of course, this is already true in the current state of affairs. A similar patch has already been applied as commit 151b61284776be2d6f02d48c23c3625678960b97 (USB: EHCI: fix crash during suspend on ASUS computers). The patch supersedes that one and reverts it. There are two differences: The old patch added the flag at the USB level; this patch adds it at the PCI level. The old patch applied to all chipsets with the same vendor, subsystem vendor, and product IDs; this patch makes an exception for a known-good system (based on DMI information). Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Tested-by: Dâniel Fraga <fragabr@gmail.com> Tested-by: Andrey Rahmatullin <wrar@wrar.name> Tested-by: Steven Rostedt <rostedt@goodmis.org> Cc: stable <stable@vger.kernel.org> Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
ad805758 |
|
10-Jun-2012 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: add ACS validation utility In a PCI environment, transactions aren't always required to reach the root bus before being re-routed. Intermediate switches between an endpoint and the root bus can redirect DMA back downstream before things like IOMMUs have a chance to intervene. Legacy PCI is always susceptible to this as it operates on a shared bus. PCIe added a new capability to describe and control this behavior, Access Control Services, or ACS. The utility function pci_acs_enabled() allows us to test the ACS capabilities of an individual devices against a set of flags while pci_acs_path_enabled() tests a complete path from a given downstream device up to the specified upstream device. We also include the ability to add device specific tests as it's likely we'll see devices that do not implement ACS, but want to indicate support for various capabilities in this space. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
b99ea85a |
|
03-Jun-2012 |
Sebastian Andrzej Siewior <sebastian@breakpoint.cc> |
PCI: move fixup hooks from __init to __devinit The fixups are executed once the pci-device is found which is during boot process so __init seems fine as long as the platform does not support hotplug. However it is possible to remove the PCI bus at run time and have it rediscovered again via "echo 1 > /sys/bus/pci/rescan" and this will call the fixups again. Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
12ea6cad |
|
10-Jun-2012 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: add PCI DMA source ID quirk DMA transactions are tagged with the source ID of the device making the request. Occasionally hardware screws this up and uses the source ID of a different device (often the wrong function number of a multifunction device). A specific Ricoh multifunction device is a prime example of this problem and included in this patch. Given a pci_dev, this function returns the pci_dev to use as the source ID for DMA. When hardware works correctly, this returns the input device. For the components of the Ricoh multifunction device, it returns the pci_dev for function 0. This will be used by IOMMU drivers for determining the boundaries of IOMMU groups as multiple devices using the same source ID must be contained within the same group. This can also be used by existing streaming DMA paths for the same purpose. [bhelgaas: fold in pci_dev_get() for !CONFIG_PCI] Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
df558de1 |
|
27-Apr-2012 |
Xudong Hao <xudong.hao@intel.com> |
PCI: work around IvyBridge internal graphics FLR erratum For IvyBridge Mobile platform, a system hang may occur if a FLR (Function Level Reset) is asserted to internal graphics. This quirk is a workaround for the IVB FLR errata issue. We are disabling the FLR reset handshake between the PCH and CPU display, then manually powering down the panel power sequencing and resetting the PCH display. Signed-off-by: Xudong Hao <xudong.hao@intel.com> Signed-off-by: Kay, Allen M <allen.m.kay@intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
7cb6a291 |
|
30-Apr-2012 |
Huang, Xiong <xiong@qca.qualcomm.com> |
atl1c: add workaround for issue of bit INTX-disable for MSI interrupt All supported devices have one issue that msi interrupt doesn't assert if pci command register bit (PCI_COMMAND_INTX_DISABLE) is set. Add workaround in drivers/pci/quirks.c Signed-off-by: xiong <xiong@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
0b471506 |
|
27-Feb-2012 |
Matt Carlson <mcarlson@broadcom.com> |
tg3: Recode PCI MRRS adjustment as a PCI quirk This patch recodes the MRRS cap for 5719 A0 devices as a PCI quirk. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
3cf8b643 |
|
15-Feb-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: print out PCI device info along with duration Makes it a little easier to figure out which device may have caused a slow quirk. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: Arjan van de Ven <arjan@infradead.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
2069ecfb |
|
15-Feb-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Move "pci reassigndev resource alignment" out of quirks.c This isn't really a quirk; calling it directly from pci_add_device makes more sense. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
40c96236 |
|
24-Feb-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Use class for quirk for ti816x class fixup Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
4c5b28e2 |
|
24-Feb-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Use class for quirk for intel e100 interrupt fixup Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
08803efe |
|
24-Feb-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Use class for quirk for netmos class fixup Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
faa738bb |
|
24-Feb-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Use class for quirk for legacy ATA NO_D3 Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
ae9de56b |
|
24-Feb-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Use class for quirk for cardbus_legacy Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
52d21b5e |
|
24-Feb-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Use class for quirk for host bridge mmio_always_on Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
f4ca5c6a |
|
24-Feb-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Add class support in quirk handling Recently added support to allow quirks to report duration also make the boot log very crowded when initcall_debug is specified. One thing we can to do mitigate this is to not call quirks unnecessarily by adding a new quirk declaration macro that takes a class argument. The new macro takes a class value and a class shift value (since it can vary) so that quirks will be limited to certain device classes, greatly reducing the number we call on every PCI device addition. -v2: fix v1 that left over of sparated patch. -v3: according to Jesse, change cls to class, cls_shift, to class_shift. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
f67fd55f |
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07-Dec-2011 |
Thomas Jarosch <thomas.jarosch@intra2net.com> |
PCI: Add quirk for still enabled interrupts on Intel Sandy Bridge GPUs Some BIOS implementations leave the Intel GPU interrupts enabled, even though no one is handling them (f.e. i915 driver is never loaded). Additionally the interrupt destination is not set up properly and the interrupt ends up -somewhere-. These spurious interrupts are "sticky" and the kernel disables the (shared) interrupt line after 100.000+ generated interrupts. Fix it by disabling the still enabled interrupts. This resolves crashes often seen on monitor unplug. Tested on the following boards: - Intel DH61CR: Affected - Intel DH67BL: Affected - Intel S1200KP server board: Affected - Asus P8H61-M LE: Affected, but system does not crash. Probably the IRQ ends up somewhere unnoticed. According to reports on the net, the Intel DH61WW board is also affected. Many thanks to Jesse Barnes from Intel for helping with the register configuration and to Intel in general for providing public hardware documentation. Signed-off-by: Thomas Jarosch <thomas.jarosch@intra2net.com> Tested-by: Charlie Suffin <charlie.suffin@stratus.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
3209874a |
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30-Jan-2012 |
Arjan van de Ven <arjan@infradead.org> |
PCI: Annotate PCI quirks in initcall_debug style While diagnosing some boot time issues on a platform, all that I could see in the bootgraph/dmesg was that the system was spending a lot of time in applying one or more PCI quirks... which was virtually undebuggable. This patch adds printk's in "initcall_debug" style to the dmesg, which are added when the user asks for the initcall_debug (the nr one tool to use when debugging boot hangs or boot time issues) kernel command line option. v2: add #includes so quirks can build on non-x86 Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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363c75db |
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27-May-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
pci: Fix files needing export.h for EXPORT_SYMBOL/THIS_MODULE They were implicitly getting it from device.h --> module.h but we want to clean that up. So add the minimal header for these macros. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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d387a8d6 |
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14-Oct-2011 |
Jon Mason <mason@myri.com> |
PCI: Workaround for Intel MPS errata Intel 5000 and 5100 series memory controllers have a known issue if read completion coalescing is enabled and the PCI-E Maximum Payload Size is set to 256B. To work around this issue, disable read completion coalescing in the memory controller and root complexes. Unfortunately, it must always be disabled, even if no 256B MPS devices are present, due to the possibility of one being hotplugged. Links to erratas: http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf Thanks to Jesse Brandeburg and Ben Hutchings for providing insight into the problem. Tested-and-Reported-by: Avi Kivity <avi@redhat.com> Signed-off-by: Jon Mason <mason@myri.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
3e309cdf |
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05-Oct-2011 |
Josh Boyer <jwboyer@redhat.com> |
PCI quirk: mmc: Always check for lower base frequency quirk for Ricoh 1180:e823 Commit 15bed0f2f added a quirk for the e823 Ricoh card reader to lower the base frequency. However, the quirk first checks to see if the proprietary MMC controller is disabled, and returns if so. On some devices, such as the Lenovo X220, the MMC controller is already disabled by firmware it seems, but the frequency change is still needed so sdhci-pci can talk to the cards. Since the MMC controller is disabled, the frequency fixup was never being run on these machines. This moves the e823 check above the MMC controller check so that it always gets run. This fixes https://bugzilla.redhat.com/show_bug.cgi?id=722509 Signed-off-by: Josh Boyer <jwboyer@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
a94d072b |
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05-Oct-2011 |
Ben Hutchings <bhutchings@solarflare.com> |
PCI: Add quirk for known incorrect MPSS Using legacy interrupts and TLPs > 256 bytes on the SFC4000 (all revisions) may cause interrupt messages to be replayed. In some systems this results in a non-recoverable MCE. Early boards using the SFC4000 set the maximum payload size supported (MPSS) to 1024 bytes and we should override that. There are probably other devices with similar issues, so give this quirk a generic name. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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d3f13810 |
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23-Aug-2011 |
Suresh Siddha <suresh.b.siddha@intel.com> |
iommu: Rename the DMAR and INTR_REMAP config options Change the CONFIG_DMAR to CONFIG_INTEL_IOMMU to be consistent with the other IOMMU options. Rename the CONFIG_INTR_REMAP to CONFIG_IRQ_REMAP to match the irq subsystem name. And define the CONFIG_DMAR_TABLE for the common ACPI DMAR routines shared by both CONFIG_INTEL_IOMMU and CONFIG_IRQ_REMAP. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: yinghai@kernel.org Cc: youquan.song@intel.com Cc: joerg.roedel@amd.com Cc: tony.luck@intel.com Cc: dwmw2@infradead.org Link: http://lkml.kernel.org/r/20110824001456.558630224@sbsiddha-desk.sc.intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
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#
15bed0f2 |
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11-Jul-2011 |
Manoj Iyer <manoj.iyer@canonical.com> |
mmc: Added quirks for Ricoh 1180:e823 lower base clock frequency Ricoh 1180:e823 does not recognize certain types of SD/MMC cards, as reported at http://launchpad.net/bugs/773524. Lowering the SD base clock frequency from 200Mhz to 50Mhz fixes this issue. This solution was suggest by Koji Matsumuro, Ricoh Company, Ltd. This change has no negative performance effect on standard SD cards, though it's quite possible that there will be one on UHS-1 cards. Signed-off-by: Manoj Iyer <manoj.iyer@canonical.com> Tested-by: Daniel Manrique <daniel.manrique@canonical.com> Cc: Koji Matsumuro <matsumur@nts.ricoh.co.jp> Cc: <stable@kernel.org> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Ball <cjb@laptop.org>
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#
be98ca65 |
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26-May-2011 |
Manoj Iyer <manoj.iyer@canonical.com> |
mmc: Add PCI fixup quirks for Ricoh 1180:e823 reader Signed-off-by: Manoj Iyer <manoj.iyer@canonical.com> Cc: <stable@kernel.org> Signed-off-by: Chris Ball <cjb@laptop.org>
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#
9251bac9 |
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15-May-2011 |
Jean Delvare <khali@linux-fr.org> |
PCI: Don't use dmi_name_in_vendors in quirk Don't use the costly dmi_name_in_vendors() when we know the string we are looking for can only be in the DMI board name field. This is more robust and, more importantly, much faster. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
b6d95bb6 |
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15-Apr-2011 |
Jean Delvare <khali@linux-fr.org> |
PCI: Use ICH6_GPIO_EN in ich6_lpc_acpi_gpio We were just lucky that ICH4_GPIO_EN and ICH6_GPIO_EN happen to have the same value. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
5d9c0a79 |
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15-Apr-2011 |
Jean Delvare <khali@linux-fr.org> |
PCI: Fix typo in ich7 quirk comment Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
63c44080 |
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04-Apr-2011 |
Hemant Pedanekar <hemantp@ti.com> |
PCI: Add quirk for setting valid class for TI816X Endpoint TI816X (common name for DM816x/C6A816x/AM389x family) devices configured to boot as PCIe Endpoint have class code = 0. This makes kernel PCI bus code to skip allocating BARs to these devices resulting into following type of error when trying to enable them: "Device 0000:01:00.0 not available because of resource collisions" The device cannot be operated because of the above issue. This patch adds a ID specific (TI VENDOR ID and 816X DEVICE ID based) 'early' fixup quirk to replace class code with PCI_CLASS_MULTIMEDIA_VIDEO as class. Signed-off-by: Hemant Pedanekar <hemantp@ti.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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25985edc |
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30-Mar-2011 |
Lucas De Marchi <lucas.demarchi@profusion.mobi> |
Fix common misspellings Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
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#
87e3dc38 |
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28-Feb-2011 |
Jiri Slaby <jirislaby@kernel.org> |
PCI: do not create quirk I/O regions below PCIBIOS_MIN_IO for ICH Some broken BIOSes on ICH4 chipset report an ACPI region which is in conflict with legacy IDE ports when ACPI is disabled. Even though the regions overlap, IDE ports are working correctly (we cannot find out the decoding rules on chipsets). So the only problem is the reported region itself, if we don't reserve the region in the quirk everything works as expected. This patch avoids reserving any quirk regions below PCIBIOS_MIN_IO which is 0x1000. Some regions might be (and are by a fast google query) below this border, but the only difference is that they won't be reserved anymore. They should still work though the same as before. The conflicts look like (1f.0 is bridge, 1f.1 is IDE ctrl): pci 0000:00:1f.1: address space collision: [io 0x0170-0x0177] conflicts with 0000:00:1f.0 [io 0x0100-0x017f] At 0x0100 a 128 bytes long ACPI region is reported in the quirk for ICH4. ata_piix then fails to find disks because the IDE legacy ports are zeroed: ata_piix 0000:00:1f.1: device not available (can't reserve [io 0x0000-0x0007]) References: https://bugzilla.novell.com/show_bug.cgi?id=558740 Signed-off-by: Jiri Slaby <jslaby@suse.cz> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Thomas Renninger <trenn@suse.de> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
cdb97558 |
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28-Feb-2011 |
Jiri Slaby <jirislaby@kernel.org> |
PCI: add more checking to ICH region quirks Per ICH4 and ICH6 specs, ACPI and GPIO regions are valid iff ACPI_EN and GPIO_EN bits are set to 1. Add checks for these bits into the quirks prior to the region creation. While at it, name the constants by macros. Signed-off-by: Jiri Slaby <jslaby@suse.cz> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Thomas Renninger <trenn@suse.de> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
b99af4b0 |
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14-Feb-2011 |
Brandeburg, Jesse <jesse.brandeburg@intel.com> |
PCI: remove quirk for pre-production systems Revert commit 7eb93b175d4de9438a4b0af3a94a112cb5266944 Author: Yu Zhao <yu.zhao@intel.com> Date: Fri Apr 3 15:18:11 2009 +0800 PCI: SR-IOV quirk for Intel 82576 NIC If BIOS doesn't allocate resources for the SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the old Flash Memory Space. Please refer to Intel 82576 Gigabit Ethernet Controller Datasheet section 7.9.2.14.2 for details. http://download.intel.com/design/network/datashts/82576_Datasheet.pdf Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> This quirk was added before SR-IOV was in production and now all machines that originally had this issue alreayd have bios updates to correct the issue. The quirk itself is no longer needed and in fact causes bugs if run. Remove it. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> CC: Yu Zhao <yu.zhao@intel.com> CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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49c2fa08 |
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08-Dec-2010 |
Neil Horman <nhorman@tuxdriver.com> |
PCI: Update MCP55 quirk to not affect non HyperTransport variants I wrote this quirk awhile ago to properly setup MCP55 chips on hypertransport busses so that interrupts reached whatever cpu happend to boot the kdump kernel. while that works well, it was recently shown to me that a a non-hypertransport variant of the MCP55 exists, and on those system the register that this quirk manipulates causes hangs if you write to it. Since the quirk was only meant to handle errors found on MCP55 chips that have a HT interface, this patch adds a filter to make sure the chip is an HT capable before making the needed register adjustment. This lets the broken MCP55s work with kdump while not breaking the non-HT variants. Resolves https://bugzilla.kernel.org/show_bug.cgi?id=23952 Tested successfully by the reporter and myself. Cc: stable@kernel.org Reported-by: Mathieu Bérard <mathieu@mberard.eu> Acked-by: Vivek Goyal <vgoyal@redhat.com> Signed-off-by: Neil Horman <nhorman@tuxdriver.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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254e4200 |
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06-Dec-2010 |
Suresh Siddha <suresh.b.siddha@intel.com> |
x86, vt-d: Quirk for masking vtd spec errors to platform error handling logic On platforms with Intel 7500 chipset, there were some reports of system hang/NMI's during kexec/kdump in the presence of interrupt-remapping enabled. During kdump, there is a window where the devices might be still using old kernel's interrupt information, while the kdump kernel is coming up. This can cause vt-d faults as the interrupt configuration from the old kernel map to null IRTE entries in the new kernel etc. (with out interrupt-remapping enabled, we still have the same issue but in this case we will see benign spurious interrupt hit the new kernel). Based on platform config settings, these platforms seem to generate NMI/SMI when a vt-d fault happens and there were reports that the resulting SMI causes the system to hang. Fix it by masking vt-d spec defined errors to platform error reporting logic. VT-d spec related errors are already handled by the VT-d OS code, so need to report the same error through other channels. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> LKML-Reference: <1291667190.2675.8.camel@sbsiddha-MOBL3.sc.intel.com> Cc: stable@kernel.org [v2.6.32+] Reported-by: Max Asbock <masbock@linux.vnet.ibm.com> Reported-and-tested-by: Takao Indoh <indou.takao@jp.fujitsu.com> Acked-by: Chris Wright <chrisw@sous-sol.org> Acked-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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f02cbbe6 |
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01-Nov-2010 |
Chris Metcalf <cmetcalf@tilera.com> |
pci root complex: support for tile architecture This change enables PCI root complex support for TILEPro. Unlike TILE-Gx, TILEPro has no support for memory-mapped I/O, so the PCI support consists of hypervisor upcalls for PIO, DMA, etc. However, the performance is fine for the devices we have tested with so far (1Gb Ethernet, SATA, etc.). The <asm/io.h> header was tweaked to be a little bit more aggressive about disabling attempts to map/unmap IO port space. The hacky <asm/pci-bridge.h> header was rolled into the <asm/pci.h> header and the result was simplified. Both of the latter two headers were preliminary versions not meant for release before now - oh well. There is one quirk for our TILEmpower platform, which accidentally negotiates up to 5GT and needs to be kicked down to 2.5GT. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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631dd1a8 |
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18-Oct-2010 |
Justin P. Mattock <justinmattock@gmail.com> |
Update broken web addresses in the kernel. The patch below updates broken web addresses in the kernel Signed-off-by: Justin P. Mattock <justinmattock@gmail.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Finn Thain <fthain@telegraphics.com.au> Cc: Randy Dunlap <rdunlap@xenotime.net> Cc: Matt Turner <mattst88@gmail.com> Cc: Dimitry Torokhov <dmitry.torokhov@gmail.com> Cc: Mike Frysinger <vapier.adi@gmail.com> Acked-by: Ben Pfaff <blp@cs.stanford.edu> Acked-by: Hans J. Koch <hjk@linutronix.de> Reviewed-by: Finn Thain <fthain@telegraphics.com.au> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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66db60ea |
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21-Sep-2010 |
Neil Horman <nhorman@tuxdriver.com> |
PCI: add quirk for non-symmetric-mode irq routing to versions 0 and 4 of the MCP55 northbridge A long time ago I worked on a RHEL5 bug in which kdump hung during boot on a set of systems. The systems hung because they never received timer interrupts during calibrate_delay. These systems also all had Opteron processors on a hypertransport bus, bridged to a pci bus via an Nvidia MCP55 northbridge chip. After much wrangling I managed to learn from Nvidia that they have an undocumented register in some versions of that chip which control how legacy interrupts are send to the cpu complex when the ioapic isn't active. Nvidia defaults this register to only send legacy interrupts to the BSP, so if kdump happens to boot on an AP, we never get timer interrupts and boom. I had initially used this quirk as a workaround, with my intent being to move apic initalization to an earlier point in the boot process, so the setting of the register would be irrelevant. Given the work involved in doing that however, the fragile nature of the apic initalization code, and the fact that, over the 2 years since we found this bug, the MCP55 is the only chip which seems to have this issue, I've figure at this point its likely safer to just carry the quirk around. By setting the referenced bits in this hidden register, interrupts will be broadcast to all cpus when the ioapic isn't active on the above described systems. Acked-by: Simon Horman <horms@verge.net.au> Acked-by: Vivek Goyal <vgoyal@redhat.com> Signed-off-by: Neil Horman <nhorman@tuxdriver.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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4731fdcf |
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24-Sep-2010 |
Len Brown <len.brown@intel.com> |
intel_idle: PCI quirk to prevent Lenovo Ideapad s10-3 boot hang When the Lenovo Ideapad S10-3 is booted with HT enabled, it hits a boot hang in the intel_idle driver. This occurs when entering ATM-C4 for the first time, unless BM_STS is first cleared. acpi_idle doesn't see this because it first checks and clears BM_STS, but it would hit the same hang if that check were disabled. http://bugs.meego.com/show_bug.cgi?id=7093 https://bugs.launchpad.net/ubuntu/+source/linux/+bug/634702 Signed-off-by: Len Brown <len.brown@intel.com>
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5b6ae5ba |
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30-Jul-2010 |
Tejun Heo <tj@kernel.org> |
libata: more PCI IDs for jmicron controllers Add support for JMB364 and 369. Patch-originally-from: Aries Lee <arieslee@jmicron.com> Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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3d2a5318 |
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23-Jul-2010 |
Rafael J. Wysocki <rjw@rjwysocki.net> |
PCI: Do not run NVidia quirks related to MSI with MSI disabled There is no reason to run NVidia-specific quirks related to HT MSI mappings with MSI disabled via pci=nomsi, so make __nv_msi_ht_cap_quirk() return immediately in that case. This allows at least one machine to boot 100% of the time with pci=nomsi (it still doesn't boot reliably without that). Addresses https://bugzilla.kernel.org/show_bug.cgi?id=16443 . Cc: stable@kernel.org Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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4e344b1c |
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03-Jul-2010 |
Kulikov Vasiliy <segooon@gmail.com> |
PCI: use for_each_pci_dev() Use for_each_pci_dev() to simplify the code. Signed-off-by: Kulikov Vasiliy <segooon@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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253d2e54 |
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16-Jul-2010 |
Jacob Pan <jacob.jun.pan@linux.intel.com> |
PCI: disable mmio during bar sizing It is a known issue that mmio decoding shall be disabled while doing PCI bar sizing. Host bridge and other devices (PCI PIC) shall be excluded for certain platforms. This patch mainly comes from Mathew Willcox's patch in http://kerneltrap.org/mailarchive/linux-kernel/2007/9/13/258969. A new flag bit "mmio_alway_on" is added to pci_dev with the intention that devices with their mmio decoding cannot be disabled during BAR sizing shall have this bit set, preferrablly in their quirks. Without this patch, Intel Moorestown platform graphics unit will be corrupted during bar sizing activities. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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549e1561 |
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23-May-2010 |
Tejun Heo <tj@kernel.org> |
PCI: disable MSI on VIA K8M800 MSI delivery from on-board ahci controller doesn't work on K8M800. At this point, it's unclear whether the culprit is with the ahci controller or the host bridge. Given the track record and considering the rather minimal impact of MSI, disabling it seems reasonable. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Rainer Hurtado Navarro <publio.escipion.el.africano@gmail.com> Cc: stable@kernel.org Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
aff61369 |
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25-May-2010 |
Clemens Ladisch <clemens@ladisch.de> |
PCI quirk: AMD 780: work around wrong vendor ID on APC bridge In all AMD 780 family northbridges, the vendor ID of the internal graphics PCI/PCI bridge reads not as AMD but as that of the mainboard vendor, because the hardware actually returns the value of the subsystem vendor ID (erratum 18). We currently have additional quirk entries for Asus and Acer, but it is likely that we will encounter more systems with other vendor IDs. Since we do not know in advance all possible vendor IDs, a better way to find the device is to declare the quirk on the host bridge, whose ID is always correct, and use that device as a stepping stone to find the PCI/ PCI bridge, if present. Reviewed-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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4daedcfe |
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03-Jun-2010 |
Tejun Heo <tj@kernel.org> |
ahci: add pci quirk for JMB362 JMB362 is a new variant of jmicron controller which is similar to JMB360 but has two SATA ports instead of one. As there is no PATA port, single function AHCI mode can be used as in JMB360. Add pci quirk for JMB362. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Aries Lee <arieslee@jmicron.com> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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3322340a |
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28-Mar-2010 |
Felix Radensky <felix@embedded-sol.com> |
PCI: Allow manual resource allocation for PCI hotplug bridges At the moment only PCI-E briges can be flagged as hotplug, thus allowing manual resource preallocation via pci=hpmemsize=nnM and pci=hpiosize=nnM kernel parameters. Some PCI hotplug bridges, e.g. PLX 6254 can also benefit from this functionalily, as kernel fails to properly allocate their resources when hotplug device is added and PCI bus is rescanned. This patch adds header quirk for PLX 6254 that marks this bridge as hotplug. Other PCI bridges with similar problems can use it as well. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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9313ff45 |
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18-May-2010 |
Alex Deucher <alexdeucher@gmail.com> |
PCI quirks: disable msi on AMD rs4xx internal gfx bridges Doesn't work reliably for internal gfx. Fixes kernel bug https://bugzilla.kernel.org/show_bug.cgi?id=15626. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: Stable <stable@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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e4146bb9 |
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15-May-2010 |
Ben Hutchings <ben@decadent.org.uk> |
PCI: Disable MSI for MCP55 on P5N32-E SLI As reported in <http://bugs.debian.org/552299>, MSI appears to be broken for this on-board device. We already have a quirk for the P5N32-SLI Premium; extend it to cover both variants of the board. Reported-by: Romain DEGEZ <romain.degez@smartjog.com> Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Cc: stable@kernel.org Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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5193d7a7 |
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02-Apr-2010 |
Clemens Ladisch <clemens@ladisch.de> |
PCI quirk: RS780/RS880: disable MSI behind the PCI bridge The missing initialization of the nb_cntl.strap_msi_enable does not seem to be the only problem that prevents MSI, so that quirk is not sufficient to enable MSI on all machines. To be safe, disable MSI unconditionally for the internal graphics and HDMI audio on these chipsets. [rjw: Added the PCI_VENDOR_ID_AI quirk.] Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
f967a443 |
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22-Mar-2010 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
PCI: don't say we claimed a resource if we failed pci_claim_resource() can fail, so pay attention and only claim success when it actually succeeded. If pci_claim_resource() fails, it prints a useful diagnostic. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
134b3450 |
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24-Mar-2010 |
Matthew Wilcox <willy@infradead.org> |
PCI quirk: Disable MSI on VIA K8T890 systems Bugzilla 15287 indicates that there's a problem with Message Signalled Interrupts on VIA K8T890 systems. Add a quirk to disable MSI on these systems. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Tested-by: Jan Kreuzer <kontrollator@gmx.de> Tested-by: lh <jarryson@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
a5ee4eb7 |
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22-Mar-2010 |
Clemens Ladisch <clemens@ladisch.de> |
PCI quirk: RS780/RS880: work around missing MSI initialization AMD says in section 2.5.4 (GFX MSI Enable) of #43291 (AMD 780G Family Register Programming Requirements): The SBIOS must enable internal graphics MSI capability in GCCFG by setting the following: NBCFG.NB_CNTL.STRAP_MSI_ENABLE='1' Quite a few BIOS writers misinterpret this sentence and think that enabling MSI is an optional feature. However, clearing that bit just prevents delivery of MSI messages but does not remove the MSI PCI capabilities registers, and so leaves these devices unusable for any driver that attempts to use MSI. Setting that bit is not possible after the BIOS has locked down the configuration registers, so we have to manually disable MSI for the affected devices. This fixes the codec communication errors in the HDA driver when accessing the HDMI audio device, and allows us to get rid of the overcautious quirk in radeon_irq_kms.c. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Tested-by: Alex Deucher <alexdeucher@gamil.com> Cc: <stable@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
ca846392 |
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19-Mar-2010 |
Tim Yamin <plasm@roo.me.uk> |
PCI quirk: only apply CX700 PCI bus parking quirk if external VT6212L is present Apply the CX700 quirk only when an external VT6212L is present (which is the case for the errant hardware the quirk was written for), don't touch the settings otherwise -- Hauppage PVR-500 tuners need PCI Bus Parking in order to work and when that's turned on everything seems to behave fine. I guess the underlying problem is a combination of an external VT6212L and the CX700 rather than the CX700's PCI being broken completely for all cases... Reported-by: Jeroen Roos <jeroen@roosnl.com> Signed-off-by: Tim Yamin <plasm@roo.me.uk> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
03cd8f7e |
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05-Mar-2010 |
Maxim Levitsky <maximlevitsky@gmail.com> |
ricoh_mmc: port from driver to pci quirk This patch solves nasty problem original driver has. Original goal of the ricoh_mmc was to disable this device because then, mmc cards can be read using standard SDHCI controller, thus avoiding writing of yet another driver. However, the act of disablement, makes other pci functions that belong to this controller (xD and memstick) shift up one level, thus pci core has now wrong idea about these devices. To fix this issue, this patch moves the driver into the pci quirk section, thus it is executes before the pci is enumerated, and therefore solving that issue, also same sequence of commands is performed on resume for same reasons. Also regardless of the above, this way is cleaner. You still need to set CONFIG_MMC_RICOH_MMC to enable this quirk Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com> Acked-by: Philip Langdale <philipl@overt.org> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Cc: <linux-mmc@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
93177a74 |
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02-Jan-2010 |
Rafael J. Wysocki <rjw@rjwysocki.net> |
PCI: Clean up build for CONFIG_PCI_QUIRKS unset Currently, drivers/pci/quirks.c is built unconditionally, but if CONFIG_PCI_QUIRKS is unset, the only things actually built in this file are definitions of global variables and empty functions (due to the #ifdef CONFIG_PCI_QUIRKS embracing all of the code inside the file). This is not particularly nice and if someone overlooks the #ifdef CONFIG_PCI_QUIRKS, build errors are introduced. To clean that up, move the definitions of the global variables in quirks.c that are always built to pci.c, move the definitions of the empty functions (compiled when CONFIG_PCI_QUIRKS is unset) to headers (additionally make these functions static inline) and modify drivers/pci/Makefile so that quirks.c is only built if CONFIG_PCI_QUIRKS is set. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
7a0deb6b |
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19-Feb-2010 |
Alexander Duyck <alexander.h.duyck@intel.com> |
pci: add support for 82576NS serdes to existing SR-IOV quirk This patch adds support for the 82576NS Serdes adapter to the existing pci quirk for 82576 parts. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
73d2eaac |
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04-Feb-2010 |
Andres Salomon <dilinger@collabora.co.uk> |
CS5536: apply pci quirk for BIOS SMBUS bug The new cs5535-* drivers use PCI header config info rather than MSRs to determine the memory region to use for things like GPIOs and MFGPTs. As anticipated, we've run into a buggy BIOS: [ 0.081818] pci 0000:00:14.0: reg 10: [io 0x6000-0x7fff] [ 0.081906] pci 0000:00:14.0: reg 14: [io 0x6100-0x61ff] [ 0.082015] pci 0000:00:14.0: reg 18: [io 0x6200-0x63ff] [ 0.082917] pci 0000:00:14.2: reg 20: [io 0xe000-0xe00f] [ 0.083551] pci 0000:00:15.0: reg 10: [mem 0xa0010000-0xa0010fff] [ 0.084436] pci 0000:00:15.1: reg 10: [mem 0xa0011000-0xa0011fff] [ 0.088816] PCI: pci_cache_line_size set to 32 bytes [ 0.088938] pci 0000:00:14.0: address space collision: [io 0x6100-0x61ff] already in use [ 0.089052] pci 0000:00:14.0: can't reserve [io 0x6100-0x61ff] This is a Soekris board, and its BIOS sets the size of the PCI ISA bridge device's BAR0 to 8k. In reality, it should be 8 bytes (BAR0 is used for SMBus stuff). This quirk checks for an incorrect size, and resets it accordingly. Signed-off-by: Andres Salomon <dilinger@collabora.co.uk> Tested-by: Leigh Porter <leigh@leighporter.org> Tested-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
df9d1e8a |
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31-Dec-2009 |
Linus Torvalds <torvalds@linux-foundation.org> |
pci: avoid compiler warning in quirks.c Introduced by commit 5b889bf23 ("PCI: Fix build if quirks are not enabled"), which made the pci_dev_reset_methods[] array static and 'const', but didn't then change the code to match, and use a const pointer when moving it to quirks.c. Trivially fixed by just adding the required 'const' to the iterator variable. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
5b889bf2 |
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31-Dec-2009 |
Rafael J. Wysocki <rjw@rjwysocki.net> |
PCI: Fix build if quirks are not enabled After commit b9c3b266411d27f1a6466c19d146d08db576bfea ("PCI: support device-specific reset methods") the kernel build is broken if CONFIG_PCI_QUIRKS is unset. Fix this by moving pci_dev_specific_reset() to drivers/pci/quirks.c and providing an empty replacement for !CONFIG_PCI_QUIRKS builds. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Reported-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
c763e7b5 |
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06-Dec-2009 |
Dexuan Cui <dexuan.cui@intel.com> |
PCI: add Intel 82599 Virtual Function specific reset method Handle device specific timeout and use FLR. Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
aeb30016 |
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06-Dec-2009 |
Dexuan Cui <dexuan.cui@intel.com> |
PCI: add Intel USB specific reset method Handle device specific reset requirements (i.e. vendor reg for reset along with appropriate timeout). Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
b9c3b266 |
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06-Dec-2009 |
Dexuan Cui <dexuan.cui@intel.com> |
PCI: support device-specific reset methods Add a new type of quirk for resetting devices at pci_dev_reset time. This is necessary to handle device with nonstandard reset procedures, especially useful for guest drivers. Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
2820f333 |
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15-Dec-2009 |
Csaba Henk <csaba@gluster.com> |
PCI: Handle case when no pci device can provide cache line size hint Prior to this patch, if pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, ...) returns 0 for all dev, pci_cache_line_size ends up set to zero (instead of pci_dfl_cache_line_size). This patch ensures the pci_cache_line_size = pci_dfl_cache_line_size setting in the above scenario. This happens in case of a kvm-88 guest (where, consequently, the rtl8139 NIC failed to initialize). Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Csaba Henk <csaba@gluster.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
c7dabef8 |
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27-Oct-2009 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
vsprintf: use %pR, %pr instead of %pRt, %pRf Jesse accidentally applied v1 [1] of the patchset instead of v2 [2]. This is the diff between v1 and v2. The changes in this patch are: - tidied vsprintf stack buffer to shrink and compute size more accurately - use %pR for decoding and %pr for "raw" (with type and flags) instead of adding %pRt and %pRf [1] http://lkml.org/lkml/2009/10/6/491 [2] http://lkml.org/lkml/2009/10/13/441 Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
4fd8bdc5 |
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27-Oct-2009 |
Stefan Assmann <sassmann@redhat.com> |
PCI: avoid boot interrupt quirk for AMD 813x B1 devices AMD 813x rev. B1 (like rev. B2) devices generate no interrupts if quirk_disable_amd_813x_boot_interrupt is executed, add an exception. http://bugzilla.kernel.org/show_bug.cgi?id=14159 Patch also adds missing cases for DECLARE_PCI_FIXUP_RESUME and DECLARE_PCI_FIXUP_FINAL calls to quirk_disable_amd_813x_boot_interrupt. Signed-off-by: Stefan Assmann <sassmann@redhat.com> Tested-by: Gabriele Giorgetti <g.giorgetti@teamsystem.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
ac1aa47b |
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26-Oct-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
PCI: determine CLS more intelligently Till now, CLS has been determined either by arch code or as L1_CACHE_BYTES. Only x86 and ia64 set CLS explicitly and x86 doesn't always get it right. On most configurations, the chance is that firmware configures the correct value during boot. This patch makes pci_init() determine CLS by looking at what firmware has configured. It scans all devices and if all non-zero values agree, the value is used. If none is configured or there is a disagreement, pci_dfl_cache_line_size is used. arch can set the dfl value (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or override the actual one. ia64, x86 and sparc64 updated to set the default cls instead of the actual one. While at it, declare pci_cache_line_size and pci_dfl_cache_line_size in pci.h and drop private declarations from arch code. Signed-off-by: Tejun Heo <tj@kernel.org> Acked-by: David Miller <davem@davemloft.net> Acked-by: Greg KH <gregkh@suse.de> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
5deab536 |
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12-Oct-2009 |
Shane Huang <shane.huang@amd.com> |
ahci / atiixp / pci quirks: rename AMD SB900 into Hudson-2 This patch renames the code name SB900 into Hudson-2 Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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#
cf6f3bf7 |
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11-Oct-2009 |
David Woodhouse <David.Woodhouse@intel.com> |
Run pci_apply_final_quirks() sooner. Having this as a device_initcall() means that some real device drivers can actually initialise _before_ the quirks are run, which is wrong. We want it to run _before_ device_initcall(), but _after_ fs_initcall(), since some arch-specific PCI initialisation like pcibios_assign_resources() is done at fs_initcall(). We could use rootfs_initcall() but I actually want to use that for the IOMMU initialisation, which has to come after the quirks, but still before the real devices. So use fs_initcall_sync() instead -- since this is entirely synchronous, it doesn't hurt that it'll escape the synchronisation. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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#
00010268 |
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11-Oct-2009 |
David Woodhouse <David.Woodhouse@intel.com> |
Mark pci_apply_final_quirks() __init rather than __devinit It doesn't get invoked on hotplug; it can be thrown away after init. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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#
8d86fb2c |
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11-Oct-2009 |
David Woodhouse <David.Woodhouse@intel.com> |
Rename pci_init() to pci_apply_final_quirks(), move it to quirks.c This function may have done more in the past, but all it does now is apply the PCI_FIXUP_FINAL quirks. So name it sensibly and put it where it belongs. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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#
1f56f4a2 |
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06-Oct-2009 |
Gabe Black <gabe.black@ni.com> |
PCI quirk: TI XIO200a erroneously reports support for fast b2b transfers This quirk will disable fast back to back transfer on the secondary bus segment of the TI Bridge. Signed-off-by: Gabe Black <gabe.black@ni.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
fdcdaf6c |
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14-Sep-2009 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
PCI: use dev_printk in quirk messages Convert quirk printks to dev_printk(). Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> CC: Olaf Dabrunz <od@suse.de> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
e2dd90b1 |
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28-Jul-2009 |
Shane Huang <shane.huang@amd.com> |
ahci: Add AMD SB900 SATA/IDE controller device IDs Add AMD SB900 SATA/IDE controller device IDs. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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#
0ba379ec |
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06-Sep-2009 |
Eric W. Biederman <ebiederm@xmission.com> |
PCI: Simplify hotplug mch quirk. There is a very old quirk for the intel E7502 E7320 and E7525 memory controller hubs that disables usage of msi interrupts on pcie hotplug bridges of those devices, and disables changing the affinity of irqs. Today all we have to do to disable msi on a specific device is to set dev->no_msi, which is much more straightforward than the previous logic. The re-running of this fixup after pci hotplug happens below these devices is totally bogus. All of the state we change is pure software state and we don't change the hardware at all. Which means hotplug on the lower devices doesn't have a chance to change this state. So we can safely remove the special case from the pciehp driver and the pcie portdriver. I suspect the special case was someone's expermental debug code that slipped in. Certainly it isn't mentioned in commit 6fb8880a61510295aece04a542767161f624dffe aka BKrev: 41966101LJ_ogfOU0m2aE6teZfQnuQ where the code first appears. Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
6f1186be |
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13-Aug-2009 |
Alexander Duyck <alexander.h.duyck@intel.com> |
PCI quirk: update 82576 device ids in SR-IOV quirks list This patch adds the most recent additions to the list of 82576 device IDs to the list of devices needing the SR-IOV quirk. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
6dab62ee |
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21-Jul-2009 |
Tejun Heo <tj@kernel.org> |
PCI: apply nv_msi_ht_cap_quirk on resume too http://bugzilla.kernel.org/show_bug.cgi?id=12542 reports that with the quirk not applied on resume, msi stops working after resuming and mcp78s ahci fails due to IRQ mis-delivery. Apply it on resume too. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Cc: Tj <linux@tjworld.net> Reported-by: Nicolas Derive <kalon33@ubuntu.com> Cc: Greg KH <greg@kroah.com> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
6b5096e4 |
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28-Jul-2009 |
Jean Delvare <khali@linux-fr.org> |
PCI: Unhide the SMBus on the Compaq Evo D510 USDT One more form factor for Compaq Evo D510, which needs the same quirk as the other form factors. Apparently there's no hardware monitoring chip on that one, but SPD EEPROMs, so it's still worth unhiding the SMBus. Signed-off-by: Jean Delvare <khali@linux-fr.org> Tested-by: Nuzhna Pomoshch <nuzhna_pomoshch@yahoo.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
7a661c6f |
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24-Jun-2009 |
Alan Cox <alan@linux.intel.com> |
PCI: More PATA quirks for not entering D3 The ALi loses some state if it goes into D3. Unfortunately even with the chipset documents I can't figure out how to restore some bits of it. The VIA one saves/restores apparently fine but the ACPI _GTM methods break on some platforms if we do this and this causes cable misdetections. These are both effectively regressions as historically nothing matched the devices and then decided not to bind to them. Nowdays something is binding to all sorts of devices and a result they get dumped into D3. Signed-off-by: Alan Cox <alan@linux.intel.com> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
74c57428 |
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12-May-2009 |
Michal Miroslaw <mirq-linux@rere.qmqm.pl> |
PCI quirk: HP hides SMBus controller in Compaq nx9500 laptops I found no references to SMBus in ACPI DSDT disassembly on my laptop so this should be safe. Signed-off-by: Michal Miroslaw <mirq-linux@rere.qmqm.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
26c56dc0 |
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12-May-2009 |
Michal Miroslaw <mirq-linux@rere.qmqm.pl> |
PCI quirk: unhide 'Overflow' device on i828{6,7}5P/PE chipsets Some BIOSes hide 'overflow' device (dev #6) for i82875P/PE chipsets. The same happens for i82865P/PE. Add a quirk to enable this device. This allows i82875 EDAC driver to bind to chipset's dev #6 and not dev #0 as the latter is used by AGP driver. On my laptop (i82865P based) ACPI code is disabling this device again in \_SB.PCI0._CRS method (called at least at PNP init time). This can be easily worked around by patching DSDT. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Michal Miroslaw <mirq-linux@rere.qmqm.pl> Acked-by: Doug Thompson <norsk5@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
4096ed0f |
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11-May-2009 |
Mats Erik Andersson <mats.andersson@gisladisker.se> |
PCI: expose SMBus on Asus notebook A6L Addition of one unknown subsystem identifier to the quirks handler for chipset i82855GM_HB on notebook Asus A6L. This exposes the otherwise hidden SMBus controller within the south bridge ICH4-M. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
dcb4ea2e |
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06-May-2009 |
Alexander Duyck <alexander.h.duyck@intel.com> |
pci: update 82576 sr-iov quirk with latest device IDs The current quirk doesn't include all 82576 device IDs. This update resolves that. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
162dedd3 |
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03-Apr-2009 |
Thomas Renninger <trenn@suse.de> |
PCI quirk: disable MSI on VIA VT3364 chipsets Without this patch, Broadcom BCM5906 Ethernet controllers set up via MSI cause the machine to hang. Tejun agreed that the best is to blacklist the whole chipset and after adding it, seeing the other VIA quirks disabling MSI, this very much looks like the right way. Cc: <stable@kernel.org> Signed-off-by: Thomas Renninger <trenn@suse.de> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
0cdbe30f |
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05-Apr-2009 |
Yuji Shimada <shimada-yxb@necst.nec.co.jp> |
PCI: don't corrupt enable_cnt when doing manual resource alignment This patch fixes breakage of of enable_cnt in quirk_resource_alignment. Currently, quirk_resource_alignment calls pci_disable_device. pci_disable_device decrements enable_cnt, so that enable_cnt becomes -1. The patch disables memory decoding, writing command register directly. So enable_cnt is not broken. Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
7eb93b17 |
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03-Apr-2009 |
Yu Zhao <yu.zhao@intel.com> |
PCI: SR-IOV quirk for Intel 82576 NIC If BIOS doesn't allocate resources for the SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the old Flash Memory Space. Please refer to Intel 82576 Gigabit Ethernet Controller Datasheet section 7.9.2.14.2 for details. http://download.intel.com/design/network/datashts/82576_Datasheet.pdf Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
eeafda70 |
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29-Mar-2009 |
Yinghai Lu <yinghai@kernel.org> |
PCI: fix HT MSI mapping fix Impact: fix bug This patch reworks the nv_msi_ht_cap_quirk() and will only try to avoid to enable ht_msi on device following that root dev, and don't touch that root dev, but only do that trick with end_device on the chain. Reported-by: Prakash Punnoor <prakash@punnoor.de> Tested-by: Prakash Punnoor <prakash@punnoor.de> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
de745306 |
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20-Mar-2009 |
Yinghai Lu <yinghai@kernel.org> |
PCI: don't enable too much HT MSI mapping Impact: fix bug Prakash reported that his c51-mcp51 system ondie sound card doesn't work MSI but if he hack out the HT-MSI on mcp51, the MSI will work well with sound card. This patch reworks nv_msi_ht_cap_quirk() and will only avoid enabling ht_msi on devices following that root device. Reported-by: Prakash Punnoor <prakash@punnoor.de> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
8293b0f6 |
|
02-Mar-2009 |
David O'Shea <dcoshea@hotmail.com> |
PCI: Compaq Evo D510 SMBus quirk using USB instead of VGA On the Compaq Evo D510 SFF/CMT, a PCI quirk activated the SMBus device based on detection of the on-board VGA controller, but the on-board VGA is disabled if an AGP card is inserted, so look for one of the USB controllers instead. Signed-off-by: David O'Shea <dcoshea@hotmail.com> Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
32a9a682 |
|
16-Mar-2009 |
Yuji Shimada <shimada-yxb@necst.nec.co.jp> |
PCI: allow assignment of memory resources with a specified alignment This patch allows memory resources to be assigned with a specified alignment at boot-time or run-time. The patch is useful when we use PCI pass-through, because page-aligned memory resources are required to securely share PCI resources with guest drivers. If you want to assign the resource at boot time, please set "pci=resource_alignment=" boot parameter. This is format of "pci=resource_alignment=" boot parameter: [<order of align>@][<domain>:]<bus>:<slot>.<func>[; ...] Specifies alignment and device to reassign aligned memory resources. If <order of align> is not specified, PAGE_SIZE is used as alignment. PCI-PCI bridge can be specified, if resource windows need to be expanded. This is example: pci=resource_alignment=20@07:00.0;18@0f:00.0;00:1d.7 If you want to assign the resource at run-time, please set "/sys/bus/pci/resource_alignment" file, and hot-remove the device and hot-add the device. For this purpose, fakephp or PCI hotplug interfaces can be used. The format of "/sys/bus/pci/resource_alignment" file is the same with boot parameter. You can use "," instead of ";". For example: # cd /sys/bus/pci # echo -n 20@12:00.0 > resource_alignment # echo 1 > devices/0000:12:00.0/remove # echo 1 > rescan Reviewed-by: Alex Chiang <achiang@hp.com> Reviewed-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
4c9c1686 |
|
08-Dec-2008 |
Jiri Slaby <jirislaby@kernel.org> |
PCI quirk: don't mark one netmos as class other Let it stay as serial, since it doesn't have subdevice in the form of 0x00PS. Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
6a958d5b |
|
06-Mar-2009 |
Prakash Punnoor <prakash@punnoor.de> |
pci: Fix typo in message while disabling HT MSI mapping "Enabling" should read "Disabling" Signed-off-by: Prakash Punnoor <prakash@punnoor.de> Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
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#
7726c330 |
|
05-Mar-2009 |
Prakash Punnoor <prakash@punnoor.de> |
pci: don't disable too many HT MSI mapping Prakash's system needs MSI disabled on some bridges, but not all. This seems to be the minimal fix for 2.6.29, but should be replaced during 2.6.30. Signed-off-by: Prakash Punnoor <prakash@punnoor.de> Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
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#
649426ef |
|
05-Mar-2009 |
Alexander Duyck <alexander.h.duyck@intel.com> |
PCI: Add PCI quirk to disable L0s ASPM state for 82575 and 82598 This patch is intended to disable L0s ASPM link state for 82598 (ixgbe) parts due to the fact that it is possible to corrupt TX data when coming back out of L0s on some systems. The workaround had been added for 82575 (igb) previously, but did not use the ASPM api. This quirk uses the ASPM api to prevent the ASPM subsystem from re-enabling the L0s state. Instead of adding the fix in igb to the ixgbe driver as well it was decided to move it into a pci quirk. It is necessary to move the fix out of the driver and into a pci quirk in order to prevent the issue from occuring prior to driver load to handle the possibility of the device being passed to a VM via direct assignment. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
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#
bbe19443 |
|
26-Feb-2009 |
Stefan Assmann <sassmann@novell.com> |
PCI: AMD 813x B2 devices do not need boot interrupt quirk Turns out that the new AMD 813x devices do not need the quirk_disable_amd_813x_boot_interrupt quirk to be run on them. If it is, no interrupts are seen on the PCI-X adapter. From: Stefan Assmann <sassmann@novell.com> Reported-by: Jamie Wellnitz <Jamie.Wellnitz@emulex.com> Tested-by: Jamie Wellnitz <Jamie.Wellnitz@emulex.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>
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#
1dec6b05 |
|
23-Feb-2009 |
Yinghai Lu <yinghai@kernel.org> |
PCI: don't enable too many HT MSI mappings Prakash reported that his c51-mcp51 ondie sound card doesn't work with MSI. But if he hacks out the HT-MSI quirk, MSI works fine. So this patch reworks the nv_msi_ht_cap_quirk(). It will now only enable ht_msi on own its root device, avoiding enabling it on devices following that root dev. Reported-by: Prakash Punnoor <prakash@punnoor.de> Tested-by: Prakash Punnoor <prakash@punnoor.de> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>
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#
e0ae4f55 |
|
17-Feb-2009 |
Yinghai Lu <yinghai@kernel.org> |
PCI quirk: enable MSI on 8132 David reported that LSI SAS doesn't work with MSI. It turns out that his BIOS doesn't enable it, but the HT MSI 8132 does support HT MSI. Add quirk to enable it Cc: stable@kernel.org Reported-by: David Lang <david@lang.hm> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
999da9fd |
|
01-Dec-2008 |
Adam Jackson <ajax@redhat.com> |
PCI quirks: piix3: warn softer about enabling passive release All the other quirks are dev_info() not dev_err(), this one isn't special. This makes 'quiet' boot in qemu really quiet. Signed-off-by: Adam Jackson <ajax@redhat.com> Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Cc: Jeff Garzik <jeff@garzik.org> Cc: Tejun Heo <htejun@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
894886e5 |
|
06-Dec-2008 |
Linus Torvalds <torvalds@linux-foundation.org> |
PCI: extend on the ICH motherboard IO decode quirk list This adds more LPC controller IO range decode quirks for the Intel ICH family of chipsets. They differ a bit between the older ICH6 chipset and the more modern layout of the ICH7-ICH10 chipsets. This patch just prints out the IO decode information found by the quirks, but eventually we may want to add them to the resource tree, in order to know to avoid allocating things over them. That's especially true if it turns out that any firmware ends up putting the magic motherboard resources in an address range that we use for dynamic allocations (ie above PCIBIOS_MIN_IO, which is 0x1000 on x86). Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Greg KH <greg@kroah.com> Cc: Frans Pop <elendil@planet.nl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
bfb0f330 |
|
27-Oct-2008 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
PCI: fixup whitespace in quirks.c Had a space before tab in do_fixups, prototype wasn't wrapped properly either. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
75e07fc3 |
|
20-Nov-2008 |
Andreas Petlund <andreas@petlund.no> |
pci: Added quirk to disable msi for MCP55 NIC on Asus P5N32-SLI Premium Signed-off-by: Andreas Petlund <andreas@petlund.no> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
bffadffd |
|
28-Oct-2008 |
Yu Zhao <yu.zhao@intel.com> |
PCI: fix VPD limit quirk for Broadcom 5708S VPD quirks need to be called after the VPD capability is initialized. Since VPD initialization now runs after pci_fixup_header (due to the capabilities consolidation), VPD quirks should be done at pci_fixup_final stage correspondingly. Tested-by: Eric Dumazet <dada1@cosmosbay.com> Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
3b15e581 |
|
23-Oct-2008 |
Fenghua Yu <fenghua.yu@intel.com> |
x86/PCI: build failure at x86/kernel/pci-dma.c with !CONFIG_PCI On Thu, Oct 23, 2008 at 04:09:52PM -0700, Alexander Beregalov wrote: > arch/x86/kernel/built-in.o: In function `iommu_setup': > pci-dma.c:(.init.text+0x36ad): undefined reference to `forbid_dac' > pci-dma.c:(.init.text+0x36cc): undefined reference to `forbid_dac' > pci-dma.c:(.init.text+0x3711): undefined reference to `forbid_dac This patch partially reverts a patch to add IOMMU support to ia64. The forbid_dac variable was incorrectly moved to quirks.c, which isn't built when PCI is disabled. Tested-by: "Alexander Beregalov" <a.beregalov@gmail.com> Acked-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
1543c90c |
|
18-Oct-2008 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
PCI: remove #ifdef DEBUG around dev_dbg call No longer needed since we don't use the function symbol stuff anymore. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
c9bbb4ab |
|
24-Sep-2008 |
Yinghai Lu <yhlu.kernel@gmail.com> |
PCI: use %pF instead of print_fn_descriptor_symbol() in quirks.c Use %pF instead of print_fn_descriptor_symbol() in quirks.c to get the name of the hook we're calling. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
3d137310 |
|
19-Aug-2008 |
Thomas Petazzoni <thomas.petazzoni@enix.org> |
PCI: allow quirks to be compiled out This patch adds the CONFIG_PCI_QUIRKS option which allows to remove all the PCI quirks, which are not necessarily used on embedded systems when PCI is working properly. As this is a size-reduction option, it depends on CONFIG_EMBEDDED. It allows to save almost 12 kilobytes of kernel code: text data bss dec hex filename 1287806 123596 212992 1624394 18c94a vmlinux.old 1275854 123596 212992 1612442 189a9a vmlinux -11952 0 0 -11952 -2EB0 +/- This patch has originally been written by Zwane Mwaikambo <zwane@arm.linux.org.uk> and is part of the Linux Tiny project. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
5b6985ce |
|
16-Oct-2008 |
Fenghua Yu <fenghua.yu@intel.com> |
intel-iommu: IA64 support The current Intel IOMMU code assumes that both host page size and Intel IOMMU page size are 4KiB. The first patch supports variable page size. This provides support for IA64 which has multiple page sizes. This patch also adds some other code hooks for IA64 platform including DMAR_OPERATION_TIMEOUT definition. [dwmw2: some cleanup] Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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#
2e532d68 |
|
16-Oct-2008 |
Linus Torvalds <torvalds@linux-foundation.org> |
{pci,pnp} quirks.c: don't use deprecated print_fn_descriptor_symbol() I dunno how this missed Bjorn and his quest to use %pF in commit c80cfb0406c01bb5da91bfe30f5cb1fd96831138 ("vsprintf: use new vsprintf symbolic function pointer format"), but it did. So use %pF in the two remaining places that still tried to print out function pointers by hand. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
35405f25 |
|
07-Aug-2008 |
Dean Hildebrand <seattleplus@gmail.com> |
PCI: Limit VPD length for Broadcom 5708S BCM5706S wont work correctly unless VPD length truncated to 128 Signed-off-by: Dean Hildebrand <dhildeb@us.ibm.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
9d82d8ea |
|
31-Jul-2008 |
Eric Dumazet <dada1@cosmosbay.com> |
PCI: add Broadcom 5708S to VPD length quirk BCM5708S wont work correctly unless VPD length truncated to 128 Signed-off-by: Eric Dumazet <dada1@cosmosbay.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
979b1791 |
|
24-Jul-2008 |
Alan Cox <alan@lxorguk.ukuu.org.uk> |
PCI: add D3 power state avoidance quirk Libata has some hacks to deal with certain controllers going silly in D3 state. The right way to handle this is to keep a PCI device flag for such devices. That can then be generalised for no ATA devices with power problems. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
41b9eb26 |
|
15-Jul-2008 |
Stefan Assmann <sassmann@suse.de> |
x86, pci: introduce config option for pci reroute quirks (was: [PATCH 0/3] Boot IRQ quirks for Broadcom and AMD/ATI) This is against linux-2.6-tip, branch pci-ioapic-boot-irq-quirks. From: Stefan Assmann <sassmann@suse.de> Subject: Introduce config option for pci reroute quirks The config option X86_REROUTE_FOR_BROKEN_BOOT_IRQS is introduced to enable (or disable) the redirection of the interrupt handler to the boot interrupt line by default. Depending on the existence of interrupt masking / threaded interrupt handling in the kernel (vanilla, rt, ...) and the maturity of the rerouting patch, users can enable or disable the redirection by default. This means that the reroute quirk can be applied to any kernel without changing it. Interrupt sharing could be increased if this option is enabled. However this option is vital for threaded interrupt handling, as done by the RT kernel. It should simplify the consolidation with the RT kernel. The option can be overridden by either pci=ioapicreroute or pci=noioapicreroute. Signed-off-by: Stefan Assmann <sassmann@suse.de> Signed-off-by: Olaf Dabrunz <od@suse.de> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Jon Masters <jonathan@jonmasters.org> Cc: Ihno Krumreich <ihno@suse.de> Cc: Sven Dietrich <sdietrich@suse.de> Cc: Daniel Gollub <dgollub@suse.de> Cc: Felix Foerster <ffoerster@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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#
88d1dce3 |
|
08-Jul-2008 |
Olaf Dabrunz <od@suse.de> |
PCI quirks: call boot IRQ quirks at end of device init and during resume It is not necessary to call boot IRQ quirks before the BARs of the bridges are probed. The normal case is to use DECLARE_PCI_FIXUP_FINAL, so we use this instead now. After a resume, we need to call the quirks again. Signed-off-by: Olaf Dabrunz <od@suse.de> Signed-off-by: Stefan Assmann <sassmann@suse.de> Cc: Jon Masters <jonathan@jonmasters.org> Cc: Olaf Dabrunz <od@suse.de> Cc: Stefan Assmann <sassmann@suse.de> Cc: Ihno Krumreich <ihno@suse.de> Cc: Sven Dietrich <sdietrich@suse.de> Cc: Daniel Gollub <dgollub@suse.de> Cc: Felix Foerster <ffoerster@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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#
542622da |
|
08-Jul-2008 |
Olaf Dabrunz <od@suse.de> |
PCI quirks: disable AMD/ATI legacy boot interrupt generation Add quirks for several AMD/ATI chipsets to prevent generation of legacy boot interrupts. Integrates a separate older quirk to make IO-APIC mode work on AMD 8131 rev. A0 and B0, which was due to an AMD erratum. Signed-off-by: Olaf Dabrunz <od@suse.de> Signed-off-by: Stefan Assmann <sassmann@suse.de> Cc: Jon Masters <jonathan@jonmasters.org> Cc: Olaf Dabrunz <od@suse.de> Cc: Stefan Assmann <sassmann@suse.de> Cc: Ihno Krumreich <ihno@suse.de> Cc: Sven Dietrich <sdietrich@suse.de> Cc: Daniel Gollub <dgollub@suse.de> Cc: Felix Foerster <ffoerster@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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#
77251188 |
|
08-Jul-2008 |
Olaf Dabrunz <od@suse.de> |
PCI quirks: add quirk to disable boot interrupt generation on broadcom HT1000 Signed-off-by: Olaf Dabrunz <od@suse.de> Signed-off-by: Stefan Assmann <sassmann@suse.de> Cc: Jon Masters <jonathan@jonmasters.org> Cc: Olaf Dabrunz <od@suse.de> Cc: Stefan Assmann <sassmann@suse.de> Cc: Ihno Krumreich <ihno@suse.de> Cc: Sven Dietrich <sdietrich@suse.de> Cc: Daniel Gollub <dgollub@suse.de> Cc: Felix Foerster <ffoerster@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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#
b0356cd0 |
|
20-Jun-2008 |
Bernhard Walle <bwalle@suse.de> |
pci, acpi: reroute PCI interrupt to legacy boot interrupt equivalent, warning fix This patch just fixes the compiler warning: drivers/pci/quirks.c: In function ‘quirk_reroute_to_boot_interrupts_intel’: drivers/pci/quirks.c:1375: warning: unused variable ‘i’ Signed-off-by: Bernhard Walle <bwalle@suse.de> Cc: sassmann@suse.de Signed-off-by: Ingo Molnar <mingo@elte.hu>
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#
e1d3a908 |
|
11-Jun-2008 |
Stefan Assmann <sassmann@suse.de> |
pci, acpi: reroute PCI interrupt to legacy boot interrupt equivalent Some chipsets (e.g. intel 6700PXH) generate a legacy INTx when the IRQ entry in the chipset's IO-APIC is masked (as, e.g. the RT kernel does during interrupt handling). On chipsets where this INTx generation cannot be disabled, we reroute the valid interrupts to their legacy equivalent to get rid of spurious interrupts that might otherwise bring down (vital) interrupt lines through spurious interrupt detection in note_interrupt(). This patch benefited from discussions with Alexander Graf, Torsten Duwe, Ihno Krumreich, Daniel Gollub, Hannes Reinecke. The conclusions we drew and the patch itself are the authors' responsibility alone. Signed-off-by: Stefan Assmann <sassmann@suse.de> Signed-off-by: Olaf Dabrunz <od@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
|
#
426b3b8d |
|
11-Jun-2008 |
Stefan Assmann <sassmann@suse.de> |
pci: add quirk to disable boot interrupt generation on intel 6300ESB Add a quirk to disable legacy boot interrupt generation on intel devices that support disabling it. This patch benefited from discussions with Alexander Graf, Torsten Duwe, Ihno Krumreich, Daniel Gollub, Hannes Reinecke. The conclusions we drew and the patch itself are the authors' responsibility alone. Signed-off-by: Stefan Assmann <sassmann@suse.de> Signed-off-by: Olaf Dabrunz <od@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
|
#
66d715c9 |
|
04-Jul-2008 |
Tejun Heo <tj@kernel.org> |
pci: VT3336 can't do MSI either It seems VT3336 can't do msi either as with its bro 3351. Disable it. Reported in the following SUSE bug. https://bugzilla.novell.com/show_bug.cgi?id=300001 Signed-off-by: Tejun Heo <tj@kernel.org> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
#
99cb233d |
|
02-Jul-2008 |
Benjamin Li <benli@broadcom.com> |
PCI: Limit VPD read/write lengths for Broadcom 5706, 5708, 5709 rev. For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the VPD end tag will hang the device. This problem was initially observed when a vpd entry was created in sysfs ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry will dump 32k of data. Reading a full 32k will cause an access beyond the VPD end tag causing the device to hang. Once the device is hung, the bnx2 driver will not be able to reset the device. We believe that it is legal to read beyond the end tag and therefore the solution is to limit the read/write length. A majority of this patch is from Matthew Wilcox who gave code for reworking the PCI vpd size information. A PCI quirk added for the Broadcom NIC's to limit the read/write's. Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
27e46859 |
|
08-Jun-2008 |
Krzysztof Helt <krzysztof.h1@wp.pl> |
PCI: unhide the SMBus on the Compaq Deskpro EN This patch unhides the SMBus on Compaq Deskpro EN SFF P667 with the Intel 815E chipset. Unhiding it reveals a THMC51 hardware monitoring chip. Jean Delvare has checked that this machine has no ACPI magic touching the SMBus nor the hardware monitoring chip, so this should be safe. The patch was tested on Fedora Core 9 with 2.6.25.4 kernel. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Tested-by: Rafał Haładuda <rh1985@wp.pl> CC: Jean Delvare <khali@linux-fr.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
10260d9a |
|
04-Jun-2008 |
Jean Delvare <khali@linux-fr.org> |
PCI: Unhide the SMBus on the Compaq Evo D510 One more machine with a hidden Intel SMBus. Unhiding it reveals a SMSC EMC6D100 hardware monitoring chip. I have checked that this machine has no ACPI magic touching the SMBus nor the hardware monitoring chip, so this should be safe. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
e1a2a51e |
|
15-May-2008 |
Rafael J. Wysocki <rjw@rjwysocki.net> |
Suspend/Resume bug in PCI layer wrt quirks Some quirks should be called with interrupt disabled, we can't directly call them in .resume_early. Also the patch introduces pci_fixup_resume_early and pci_fixup_suspend, which matches current device core callbacks (.suspend/.resume_early). TBD: Somebody knows why we need quirk resume should double check if a quirk should be called in resume or resume_early. I changed some per my understanding, but can't make sure I fixed all. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
a442ac51 |
|
15-May-2008 |
Linus Torvalds <torvalds@linux-foundation.org> |
Clean up 'print_fn_descriptor_symbol()' types Everybody wants to pass it a function pointer, and in fact, that is what you _must_ pass it for it to make sense (since it knows that ia64 and ppc64 use descriptors for function pointers and fetches the actual address from there). So don't make the argument be a 'unsigned long' and force everybody to add a cast. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
#
439a7733 |
|
11-May-2008 |
Björn Krombholz <fox.box@gmail.com> |
PCI: enable nv_msi_ht_cap_quirk for ALi bridges This applies the NVidia MSI enabled flag for HT capable devices quirk to ALi bridges as well. As described in more detail in http://bugzilla.kernel.org/show_bug.cgi?id=10667 this is required for my board which is using an nForce 3 250Gb chipset with an ALi M1695 northbridge. It fixes a regression introduced in 2.6.24 that made the internal NIC of the board unusable (MSI initialisation of the NIC but disabled MSI on the northbridge devices. Signed-off-by: Björn Krombholz <fox.box@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
bc043274 |
|
30-Mar-2008 |
Tim Yamin <tim.yamin@zonbu.com> |
PCI: Update VIA CX700 quirk This follows up 53a9bf4267b8b1f958dbeb7c8c1ef21c82229b71. Some newer CX700 BIOSes from our vendor have PCI Bus Parking disabled but PCI Master read caching enabled. This creates problems such as system freezing when both the network controller and the USB controller are active and one of them is pretty busy (e.g. heavy network traffic). This patch separates the checks and both the bus parking and the read caching are disabled independently if either is enabled by the BIOS. Signed-off-by: Tim Yamin <tim.yamin@zonbu.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
0255f543 |
|
04-Mar-2008 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
PCI: simplify quirk debug output print_fn_descriptor_symbol() prints the address if we don't have a symbol, so no need to print both. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
a99acc83 |
|
28-Mar-2008 |
Jean Delvare <khali@linux-fr.org> |
pci: revert SMBus unhide on HP Compaq nx6110 This reverts commit 3c0a654e390d00fef9d8faed758f5e1e8078adb5 and fixes kernel bug #10245: http://bugzilla.kernel.org/show_bug.cgi?id=10245 The HP Compaq nc6120 has the same PCI sub-device ID as the nx6110, and the SMBus is used by ACPI for thermal management on the nc6120, so Linux should not attach a native driver to it. This means that this quirk is unsafe and has to be removed. I also added a comment to help developers realize that adding new IDs to this SMBus unhiding quirk table should be done only with great care, and in particular only after checking that ACPI is not making use of the SMBus. Signed-off-by: Jean Delvare <khali@linux-fr.org> Cc: Tomasz Koprowski <tomek@koprowski.org> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
415b6d0e |
|
29-Feb-2008 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
PCI: consolidate duplicated MSI enable functions Two recent patches added basically the same code to turn on HT MSI mapping: http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=6bae1d96c6d7dde078994f6cb98235fd46f8736b http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=9dc625e72309e1c919ea3e7f51d0ffca96123787 There's no need to have both, so this patch removes one copy. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
d6505a52 |
|
29-Feb-2008 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
PCI: use dev_printk in quirk messages Convert quirk printks to dev_printk(). Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
9dc625e7 |
|
05-Feb-2008 |
Peer Chen <pchen@nvidia.com> |
PCI: quirks: set 'En' bit of MSI Mapping for devices onHT-based nvidia platform According to HT spec, to get message interrupt from devices mapped to HT interrupt message, the 'En' bit of MSI Mapping capability need to be set. The patch do this setting in quirks code for the devices on HT-based nvidia platform. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Andy Currid <acurrid@nvidia.com> Signed-off-by: Peer Chen <pchen@nvidia.com> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
05a7d22b |
|
01-Feb-2008 |
Crane Cai <crane.cai@amd.com> |
PCI: AMD SATA IDE mode quirk PCI: modify SATA IDE mode quirk When initialize and resume, SB600/700/800 need to set SATA mode correctly. Signed-off-by: Crane Cai <crane.cai@amd.com> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
4600c9d7 |
|
24-Jan-2008 |
Shane Huang <shane.huang@amd.com> |
PCI: modify SB700 SATA MSI quirk SB700 SATA MSI bug will be fixed in SB700 revision A21 at hardware level, but the SB700 revision older than A21 will also be found in the market. This patch modify the original quirk commit bc38b411fe696fad32b261f492cb4afbf1835256 instead of withdrawing it. The patch also removes quirk to 0x4395 because 0x4395 is SB800 device ID. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
f0fda801 |
|
17-Dec-2007 |
bjorn.helgaas@hp.com <bjorn.helgaas@hp.com> |
PCI: use dev_printk in quirk messages Convert quirk printks to dev_printk(). I made the MSI disable messages a little more consistent: - always use "disabled", not "deactivated" - specify "device MSI disabled" or "subordinate MSI disabled" when disabling MSI for only a specific device or subordinate bus Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
9f23ed3b |
|
17-Dec-2007 |
bjorn.helgaas@hp.com <bjorn.helgaas@hp.com> |
PCI: print quirk name in debug messages Instead of printing this: PCI: Calling quirk c023b250 for 0000:00:00.0 we can print this: pci 0000:00:00.0: calling quirk 0xc023b270: quirk_cardbus_legacy+0x0/0x30() The address is superfluous because sprint_symbol() includes the address if the symbol lookup fails, but this is the same style used in do_initcalls() and pnp_fixup_device(). Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
e64aeccb |
|
17-Dec-2007 |
Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
PCI: fix for quirk_e100_interrupt() Check that the e100 is in the D0 power state. If it's not, it won't respond to MMIO accesses and we end up with master-abort machine checks on some platforms. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
6bae1d96 |
|
13-Dec-2007 |
Sebastien Dugue <sebastien.dugue@bull.net> |
PCI: quirk: enable MSI Mapping on HT1000 Add a quirk to enable the MSI mapping capability on HyperTransport bridges. Wire Broadcom's HT1000 to use the quirk. Signed-off-by: Sebastien Dugue <sebastien.dugue@bull.net> Acked-by: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Andy Currid <acurrid@nvidia.com> Cc: Peer Chen <pchen@nvidia.com> Cc: Prakash Punnoor <prakash@punnoor.de> Cc: Andrew Morton <akpm@linux-foundation.org> Acked-by: Michael Chan <mchan@broadcom.com> Cc: Greg KH <greg@kroah.com> Cc: Andy Currid <acurrid@nvidia.com> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
677cc644 |
|
21-Nov-2007 |
Jean Delvare <khali@linux-fr.org> |
PCI: Unhide the SMBus on the HP xw4100 Unhide the SMBus on the HP xw4100. This gives access to a hardware monitoring chip (ADT7463) and to the memory module SPD EEPROMs. I checked that ACPI wasn't accessing the SMBus, so it should be safe. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
652c538e |
|
21-Nov-2007 |
Andrew Morton <akpm@linux-foundation.org> |
PCI: drivers/pci/quirks.c: coding-style cleanup Remove lots of space-before-) instances. Perhaps these were a workaround for problems in some long-dead cpp version. Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
53a9bf42 |
|
01-Nov-2007 |
Tim Yamin <tim.yamin@zonbu.com> |
PCI: VIA CX700 quirk to disable PCI Bus Parking PCI Bus Parking and PCI Master read caching on the VIA CX700 is buggy and can lead to problems such as USB2.0 packet loss if a VT6212L controller is on the PCI bus. It's disabled by default, but some BIOSes turn these features on and this patch reverts the configuration to the safe defaults. Signed-off-by: Tim Yamin <tim.yamin@zonbu.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
2b1afa87 |
|
29-Oct-2007 |
Auke Kok <auke-jan.h.kok@intel.com> |
PCI: quirk_vialatency: Omit reading pci revision ID Don't read the revision ID unnecessary since the PCI subsystem fills this field in already. Updated to fix a thinko bug in a previously sent patch. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
d1ec7298 |
|
10-Jan-2008 |
Zhao Yakui <yakui.zhao@intel.com> |
ACPI: apply quirk_ich6_lpc_acpi to more ICH8 and ICH9 It is important that these resources be reserved to avoid conflicts with well known ACPI registers. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
|
#
5257dca0 |
|
25-Oct-2007 |
David Miller <davem@davemloft.net> |
PCI: Remove 3 incorrect MSI quirks. Now that we have dealt with the real issue, in that some ATI SATA and USB controllers needed the INTX_DISABLE quirk, we can remove these AMD chipset global MSI disabling quirks. This reverts three changesets: 4be8f906435a6af241821ab5b94b2b12cb7d57d8 (PCI: disable MSI on RS690) aea6a433f50cd89b9cbd10850fd0b32f961f9883 (PCI: disable MSI on RD580) f122392f679ebed39db08074f935d770504623eb (PCI: disable MSI on RX790) This is based upon testing and feedback from Shane Huang <Shane.Huang@amd.com>. Cc: Shane Huang <Shane.Huang@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
bc38b411 |
|
25-Oct-2007 |
David Miller <davem@davemloft.net> |
PCI: Add MSI INTX_DISABLE quirks for ATI SB700/800 SATA and IXP SB400 USB Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
ba698ad4 |
|
25-Oct-2007 |
David Miller <davem@davemloft.net> |
PCI: Add quirk for devices which disable MSI when INTX_DISABLE is set. A reasonably common problem with some devices is that they will disable MSI generation when the INTX_DISABLE bit is set in the PCI_COMMAND register. Quirk this explicitly, guarding the pci_intx() calls in msi.c with this quirk indication. The first entries for this quirk are for 5714 and 5780 Tigon3 chips, and thus we can remove the workaround code from the tg3.c driver. Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Michael Chan <mchan@broadcom.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
1d84b542 |
|
25-Oct-2007 |
David Miller <davem@davemloft.net> |
PCI: Add MSI quirk for ServerWorks HT1000 PCIX bridge. This is the fix for the following problem: https://bugzilla.redhat.com/show_bug.cgi?id=227657 The bnx2 device 5706 complains about MSI not working behind a ServerWorks HT1000 PCIX bridge. An earlier commit to fix the problem: e3008dedff4bdc96a5f67224cd3d8d12237082a0: "PCI: disable MSI by default on systems with Serverworks HT1000 chips" was not entirely correct, and has been reverted. MSI does not work on the PCIX bus because the BIOS did not set the HT_MSI_FLAGS_ENABLE bit in the HyperTransport MSI capability on the bridge. We use the existing quirk_msi_ht_cap() to detect the problem and disable MSI in all buses behind it. Signed-off-by: Michael Chan <mchan@broadcom.com> Cc: Anantha Subramanyam <ananth@broadcom.com> Cc: Naren Sankar <nsankar@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
2cc31879 |
|
25-Oct-2007 |
David Miller <davem@davemloft.net> |
PCI: Revert "PCI: disable MSI by default on systems with Serverworks HT1000 chips" This reverts commit e3008dedff4bdc96a5f67224cd3d8d12237082a0. The real bug was an INTX issue in the tg3 ethernet chip, and cured by commit c129d962a66c76964954a98b38586ada82cf9381 Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
3a9e3a51 |
|
23-Oct-2007 |
Tejun Heo <htejun@gmail.com> |
jmicron: update quirk for JMB361/3/5/6 Set bits 0, 4, 5 and 7 of PCI configuration register 0x40 in the quirk. This has the following effects and is recommended by the vendor. * Force enable of IDE channels (used to be left alone as BIOS configured) * Change initial phase behavior of PIO cycle such that the host pulls down the bus instead of tristating it. Vendor recommends this setting. The above settings are better for the current generation of controllers and needed for the upcoming next generation. Tested on JMB363. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Ethan Hsiao <ethanhsiao@jmicron.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
|
#
346ca04d |
|
10-Sep-2007 |
Johannes Goecke <goecke@upb.de> |
PCI: re-enable onboard sound on "MSI K8T Neo2-FIR" On the "MSI K8T Neo2-FIR" board the BIOS disables the onboard soundcard, if a second PCI soundcard is present. This patch sets the korrect register bit to enable the onboard sound. Removed old code in /drivers/pci/quirks.c that only checks for the PCI-ID and fires on any Board with VIA 8237. New code in /arch/i386/pci/fixup.c checks the DMI-tables and only runs on the specific board. Signed-off-by: Johannes Goecke <goecke@upb.de> Acked-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
651472fb |
|
27-Aug-2007 |
Auke Kok <auke-jan.h.kok@intel.com> |
PCI: quirk_vt82c586_acpi: Omit reading PCI revision ID Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
aa288d4d |
|
27-Aug-2007 |
Auke Kok <auke-jan.h.kok@intel.com> |
PCI: quirk amd_8131_mmrbc: Omit reading pci revision ID Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Cc: Peter Oruba <peter.oruba@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
1bef7dc0 |
|
28-Sep-2007 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
Fix bogus PCI quirk for e100 Linas reported me that some machines were crashing at boot in quirk_e100_interrupt. It appears that this quirk is doing an ioremap directly on a PCI BAR value, which isn't legal and will cause all sorts of bad things to happen on architectures where PCI BARs don't directly match processor bus addresses. This fixes it by using the proper PCI resources instead which is possible since the quirk has been moved by a previous commit to happen late enough for that. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Linas Vepstas <linas@austin.ibm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
d7698edc |
|
23-Aug-2007 |
gw.kernel@tnode.com <gw.kernel@tnode.com> |
PCI: unhide SMBus on Compaq Deskpro EP 401963-001 motherboard PCI quirk to unhide SMBus on Compaq Deskpro EP 401963-001 (PCA# 010174) motherboard. Signed-off-by: Greg White <gw.kernel@tnode.com> Acked-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
18166c1a |
|
18-Aug-2007 |
Jean Delvare <khali@linux-fr.org> |
PCI: Run k8t_sound_hostbridge quirk only when needed The k8t_sound_hostbridge PCI quick fires on my motherboard (Jetway K8M8MS) while it shouldn't: the on-board sound chip is not disabled and is working just fine. Looking at the code, I see that we are running the quirk for two distinct register values (0x88 and 0xc8) and then clear bit 6 (0x40). However value 0x88 already has bit 6 cleared so this is a no-op. This is what happens on my board. Thus I believe that the quirk should only be run for register value 0xc8. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
f122392f |
|
20-Aug-2007 |
Tejun Heo <htejun@gmail.com> |
PCI: disable MSI on RX790 RX790 can't do MSI like its predecessors. Disable MSI on RX790. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
aea6a433 |
|
17-Aug-2007 |
Tejun Heo <htejun@gmail.com> |
PCI: disable MSI on RD580 RD580 can't do MSI like its predecessors. Disable MSI on RD580. Signed-off-by: Tejun Heo <teheo@suse.de> CC: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
4be8f906 |
|
15-Aug-2007 |
Tejun Heo <htejun@gmail.com> |
PCI: disable MSI on RS690 RS690 can't do MSI like its predecessors. Disable MSI on RS690. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Henry Su <henry.su@amd.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
4e68fc97 |
|
03-Jul-2007 |
Marian Balakowicz <m8@semihalf.com> |
PCI: quirk_e100_interrupt() called too early quirk_e100_interrupts() is called after PCI controller is initialized and before PCI bus enumeration is performed. On some powerpc platforms which modify PCI controller configuration and set different MEM and IO windows than those set by firmware quirk_e100_interrupt() is causing kernel panic as it tries to read from device BAR0 offets which at this time points to a invalid PCI window (set by firmware). This patch delays the quirk_100_interrupt() to pci_fixup_final phase, which happens after bus enumeration and before PCI enable and device driver initialization. Signed-off-by: Marian Balakowicz <m8@semihalf.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
b7b095c1 |
|
09-Jul-2007 |
Andrew Morton <akpm@linux-foundation.org> |
PCI: pci-x-pci-express-read-control-interfaces cleanups - remove unneeded local - 80-col fix Cc: Peter Oruba <peter.oruba@amd.com> Cc: Roland Dreier <rolandd@cisco.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
44c10138 |
|
08-Jun-2007 |
Auke Kok <auke-jan.h.kok@intel.com> |
PCI: Change all drivers to use pci_device->revision Instead of all drivers reading pci config space to get the revision ID, they can now use the pci_device->revision member. This exposes some issues where drivers where reading a word or a dword for the revision number, and adding useless error-handling around the read. Some drivers even just read it for no purpose of all. In devices where the revision ID is being copied over and used in what appears to be the equivalent of hotpath, I have left the copy code and the cached copy as not to influence the driver's performance. Compile tested with make all{yes,mod}config on x86_64 and i386. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Acked-by: Dave Jones <davej@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
d556ad4b |
|
15-May-2007 |
Peter Oruba <peter.oruba@amd.com> |
PCI: add PCI-X/PCI-Express read control interfaces This patch introduces an interface to read and write PCI-X / PCI-Express maximum read byte count values from PCI config space. There is a second function that returns the maximum _designed_ read byte count, which marks the maximum value for a device, since some drivers try to set MMRBC to the highest allowed value and rely on such a function. Based on patch set by Stephen Hemminger <shemminger@linux-foundation.org> Cc: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Peter Oruba <peter.oruba@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
184b812f |
|
26-May-2007 |
Jay Cliburn <jacliburn@bellsouth.net> |
PCI: quirk disable MSI on via vt3351 The Via VT3351 APIC does not play well with MSI and unleashes a flood of APIC errors when MSI is used to deliver interrupts. The problem was recently exposed when the atl1 network device driver, which enables MSI by default, stimulated APIC errors on an Asus M2V mainboard, which employs the Via VT3351. See http://bugzilla.kernel.org/show_bug.cgi?id=8472 for additional details on this bug. Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
e3008ded |
|
10-May-2007 |
Andy Gospodarek <andy@greyhouse.net> |
PCI: disable MSI by default on systems with Serverworks HT1000 chips I've been seeing lots of messages like these: eth0: No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information. On several systems that use the following Severworks HT1000 (also sometimes labeled as a Broadcom chipset as well) bridge chips. It doesn't appear MSI works well (if at all) on these systems. Signed-off-by: Andy Gospodarek <andy@greyhouse.net> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
ebdf7d39 |
|
31-May-2007 |
Tejun Heo <htejun@gmail.com> |
pci-quirks: fix MSI disabling on RS400-200 and RS480 Commit c0affe9db42bf85f4a606b3262c35ec59a5d3788 doesn't work because the host controller is being quirked not a PCI bridge. This patch reverts the commit, rename quirk_svw_msi() to quirk_disable_all_msi() and use it instead. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Matias Alejandro Torres <torresmat@gmail.com> Cc: Greg K-H <greg@kroah.com> Cc: Jeff Garzik <jeff@garzik.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
#
82377718 |
|
10-May-2007 |
Henry Su <henry.su@amd.com> |
Add the combined mode for ATI SB700 Besides those modes in ATI SB600 SATA controller, ATI SB700 supports one more mode:the combined mode. The combined mode is a Legacy IDE mode used for compatibility with some old OS without AHCI driver, but now it is not necessary for Linux since the kernel has supported AHCI. Signed-off-by: Luugi Marsan <luugi.marsan@amd.com> Cc: Jeff Garzik <jeff@garzik.org> Cc: Tejun Heo <htejun@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
|
#
c0affe9d |
|
15-Apr-2007 |
Tejun Heo <htejun@gmail.com> |
pci-quirks: disable MSI on RS400-200 and RS480 MSI doesn't work on RS400-200 and RS480 requiring pci=nomsi kernel boot parameter for ahci to work. This patch disables MSI on those chips. http://thread.gmane.org/gmane.linux.ide/17820 http://thread.gmane.org/gmane.linux.ide/17516 https://bugzilla.novell.com/show_bug.cgi?id=263893 Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
8cdfb29c |
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09-Mar-2007 |
Jeff Garzik <jeff@garzik.org> |
libata/IDE: remove combined mode quirk Both old-IDE and libata should be able handle all controllers and devices found using normal resource reservation methods. This eliminates the awful, low-performing split-driver configuration where old-IDE drove the PATA portion of a PCI device, in PIO-only mode, and libata drove the SATA portion of the /same/ PCI device, in DMA mode. Typically vendors would ship SATA hard drive / PATA optical configuration, which would lend itself to slow (PIO-only) CD-ROM performance. For Intel users running in combined mode, it is now wholly dependent on your driver choice (potentially link order, if you compile both drivers in) whether old-IDE or libata will drive your hardware. In either case, you will get full performance from both SATA and PATA ports now, without having to pass a kernel command line parameter. Signed-off-by: Jeff Garzik <jeff@garzik.org>
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#
9208ee82 |
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24-Mar-2007 |
Jean Delvare <khali@linux-fr.org> |
PCI: Stop unhiding the SMBus on Toshiba laptops It was found that the Toshiba laptops with hidden Intel SMBus have SMM code handling the thermal management which accesses the SMBus. Thus it is not safe to unhide it and let Linux access it. We have to leave the SMBus hidden. SMM is a pain, really. This fixes bugs #6315 and #6395, for good this time. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
f5f2b131 |
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05-Mar-2007 |
Eric W. Biederman <ebiederm@xmission.com> |
[PATCH] msi: sanely support hardware level msi disabling In some cases when we are not using msi we need a way to ensure that the hardware does not have an msi capability enabled. Currently the code has been calling disable_msi_mode to try and achieve that. However disable_msi_mode has several other side effects and is only available when msi support is compiled in so it isn't really appropriate. Instead this patch implements pci_msi_off which disables all msi and msix capabilities unconditionally with no additional side effects. pci_disable_device was redundantly clearing the bus master enable flag and clearing the msi enable bit. A device that is not allowed to perform bus mastering operations cannot generate intx or msi interrupt messages as those are essentially a special case of dma, and require bus mastering. So the call in pci_disable_device to disable msi capabilities was redundant. quirk_pcie_pxh also called disable_msi_mode and is updated to use pci_msi_off. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Cc: Michael Ellerman <michael@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
e34bb370 |
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26-Feb-2007 |
Tejun Heo <htejun@gmail.com> |
ahci/pata_jmicron: match class not function number Make jmiron_ata quirk update pdev->class after programming the device and update ahci and pata_jmicron such that they match class code instead of checking function number manually. For ahci, it matches for vendor and class. For pata_jmicron, it matches vendor, device and class as IDE class isn't as well defined as AHCI class. This makes jmicron device matching more conventional and script friendly. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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#
5ee2ae7f |
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26-Feb-2007 |
Tejun Heo <htejun@gmail.com> |
jmicron ATA: reimplement jmicron ATA quirk Reimplement jmicron ATA quirk. * renamed to quirk_jmicron_ata() * quirk is invoked only for the affected controllers * programming is stricter. e.g. conf5 bit24 is cleared if unnecessary. * code factored for readability * JMB360 and JMB368 are programmed into proper mode Verified on JMB360, 363 and 368. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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#
c9f89475 |
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09-Jan-2007 |
Conke Hu <conke.hu@amd.com> |
Add pci class code for SATA & AHCI, and replace some magic numbers. Signed-off-by: Conke Hu <conke.hu@amd.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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#
88187dfa |
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25-Jan-2007 |
Michael Ellerman <michael@ellerman.id.au> |
MSI: Replace pci_msi_quirk with calls to pci_no_msi() I don't see any reason why we need pci_msi_quirk, quirk code can just call pci_no_msi() instead. Remove the check of pci_msi_quirk in msi_init(). This is safe as all calls to msi_init() are protected by calls to pci_msi_supported(), which checks pci_msi_enable, which is disabled by pci_no_msi(). The pci_disable_msi routines didn't check pci_msi_quirk, only pci_msi_enable, but as far as I can see that was a bug not a feature. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
1863100a |
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14-Jan-2007 |
Adrian Bunk <bunk@stusta.de> |
PCI: remove quirk_sis_96x_compatible() Since 2.6.0-test10, all quirk_sis_96x_compatible() had any effect on was a printk(). This patch therefore removes it. Signed-off-by: Adrian Bunk <bunk@stusta.de> Acked-by: Mark M. Hoffman <mhoffman@lightlink.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
2f2d39d2 |
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05-Jan-2007 |
Jean Delvare <khali@linux-fr.org> |
PCI: Speed up the Intel SMBus unhiding quirk Speed up the Intel SMBus PCI quirk by avoiding tests which can only fail. This also makes the compiled code significantly smaller when using gcc 3.2/3.4. gcc 4.x appears to optimize the code by itself so this change doesn't make a difference there. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
15a260d5 |
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21-Dec-2006 |
Daniel Yeisley <dan.yeisley@unisys.com> |
PCI Quirk: 1k I/O space IOBL_ADR fix on P64H2 There's an existing quirk for the kernel to use 1k IO space granularity on the Intel P64H2. It turns out however that pci_setup_bridge() in drivers/pci/setup-bus.c reads in the IO base and limit address register masks it off to the nearest 4k, and writes it back. This causes the kernel to be on 1k boundaries and the hardware to be 4k aligned. The patch below fixes the problem. Signed-off-by: Dan Yeisley <dan.yeisley@unisys.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
c30ca1db |
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18-Dec-2006 |
Adrian Bunk <bunk@stusta.de> |
PCI: quirks.c: cleanup This patch contains the following cleanups: - move all EXPORT_SYMBOL's directly below the code they are exporting - move all DECLARE_PCI_FIXUP_*'s directly below the functions they are calling Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
33dced2e |
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07-Feb-2007 |
Sergei Shtylyov <sshtylyov@ru.mvista.com> |
ide: add Toshiba TC86C001 IDE driver (take 2) This is the driver for the Toshiba TC86C001 GOKU-S PCI IDE controller, completely reworked from the original brain-damaged Toshiba's 2.4 version. This single channel UltraDMA/66 controller is very simple in programming, yet Toshiba managed to plant many interesting bugs in it. The particularly nasty "limitation 5" (as they call the errata) caused me to abuse the IDE core in a possibly most interesting way so far. However, this is still better than the #ifdef mess in drivers/ide/ide-io.c that the original version included (well, it had much more mess)... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Acked-by: Alan Cox <alan@redhat.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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#
77280989 |
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01-Feb-2007 |
Tejun Heo <htejun@gmail.com> |
ahci/pata_jmicron: fix JMicron quirk For all JMicrons except for 361 and 368, AHCI mode enable bits in the Control(1) should be set. This used to be done in both ahci and pata_jmicron but while moving programming to PCI quirk, it was removed from ahci part while still left in pata_jmicron. The implemented JMicron PCI quirk was incorrect in that it didn't program AHCI mode enable bits. If pata_jmicron is loaded first and programs those bits, the ahci ports work; otherwise, ahci device detection fails miserably. This patch makes JMicron PCI quirk clear SATA IDE mode bits and set AHCI mode bits and remove the respective part from pata_jmicron. Tested on JMB361, 363 and 368. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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#
cb7468ef |
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01-Feb-2007 |
Jean Delvare <jdelvare@suse.de> |
[PATCH] via quirk update Add special handling for the VT82C686. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Nick Piggin <nickpiggin@yahoo.com.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
c06bb5d4 |
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30-Jan-2007 |
Jean Delvare <jdelvare@suse.de> |
[PATCH] Fix VIA quirks Fix VIA quirks that were recently broken by Alan Cox in the upstream kernel (commit 1597cacbe39802d86656d1f2e6329895bd2ef531). My understanding is that pci_find_present() doesn't work yet at the time the quirks are run. So I used a two-step quirk as is done for some other quirks already. First we detect the VIA south bridges and set the right low and high device limits, then we are ready to actually run the quirks on the affected devices. Signed-off-by: Jean Delvare <jdelvare@suse.de> Acked-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Acked-by: Nick Piggin <nickpiggin@yahoo.com.au> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
2e45785c |
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05-Jan-2007 |
Jean Delvare <khali@linux-fr.org> |
PCI: Unhide the SMBus on the Asus P4P800-X Unhide the SMBus on the Asus P4P800-X (and probably some other models of the family.) This gives access to the memory module SPD EEPROMs. Thanks to Winbond for supporting the lm-sensors project with the donation of this motherboard. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
9d24a81e |
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10-Jan-2007 |
Vivek Goyal <vgoyal@in.ibm.com> |
[PATCH] x86-64: pci quirks MODPOST warning fix o MODPOST generates warnings for i386 if kernel is compiled with CONFIG_RELOCATABLE=y WARNING: vmlinux - Section mismatch: reference to .init.data: from .text between 'asus_hides_smbus_lpc_ich6' (at offset 0xc0217d58) and 'quirk_cardbus_legacy' WARNING: vmlinux - Section mismatch: reference to .init.data: from .text between 'asus_hides_smbus_lpc' (at offset 0xc0217fd9) and 'pci_match_id' o Two quirk functions which are non __init, are accessing data which is of type __init. Signed-off-by: Vivek Goyal <vgoyal@in.ibm.com> Signed-off-by: Andi Kleen <ak@suse.de>
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#
2f5c33b3 |
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08-Jan-2007 |
Mark M. Hoffman <mhoffman@lightlink.com> |
[PATCH] i2c/pci: fix sis96x smbus quirk once and for all The sis96x SMBus PCI device depends on two different quirks to run in a specific order. Apart from being fragile, this was found to actually break on (at least) recent FC4, FC5, and FC6 kernels. This patch fixes the quirks so that they work without relying on the compiler and/or linker to put them in any specific order. http://lists.lm-sensors.org/pipermail/lm-sensors/2006-April/015962.html https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=189719 I tested this patch. Signed-off-by: Mark M. Hoffman <mhoffman@lightlink.com> Cc: Andrew Morton <akpm@osdl.org> Cc: Adrian Bunk <bunk@stusta.de> Cc: Greg K-H <greg@kroah.com> Cc: Jean Delvare <khali@linux-fr.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
ab17443a |
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19-Dec-2006 |
Conke Hu <conke.hu@gmail.com> |
PCI: ATI sb600 sata quirk Acked-by: Jeff Garzik <jeff@garzik.org> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
9ac0ce85 |
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04-Dec-2006 |
Jesper Juhl <jesper.juhl@gmail.com> |
PCI: Be a bit defensive in quirk_nvidia_ck804() so we don't risk dereferencing a NULL pdev. pci_get_slot() may return NULL if nothing was found. quirk_nvidia_ck804() does not check the value returned from pci_get_slot(), so it may end up causing a NULL pointer deref. Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com> Acked-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
1597cacb |
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04-Dec-2006 |
Alan Cox <alan@lxorguk.ukuu.org.uk> |
PCI: Fix multiple problems with VIA hardware This patch is designed to fix: - Disk eating corruptor on KT7 after resume from RAM - VIA IRQ handling - VIA fixups for bus lockups after resume from RAM The core of this is to add a table of resume fixups run at resume time. We need to do this for a variety of boards and features, but particularly we need to do this to get various critical VIA fixups done on resume. The second part of the problem is to handle VIA IRQ number rules which are a bit odd and need special handling for PIC interrupts. Various patches broke various boxes and while this one may not be perfect (hopefully it is) it ensures the workaround is applied to the right devices only. From: Jean Delvare <khali@linux-fr.org> Now that PCI quirks are replayed on software resume, we can safely re-enable the Asus SMBus unhiding quirk even when software suspend support is enabled. [akpm@osdl.org: fix const warning] Signed-off-by: Alan Cox <alan@redhat.com> Cc: Jean Delvare <khali@linux-fr.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
7a380507 |
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22-Nov-2006 |
Michael Ellerman <michael@ellerman.id.au> |
PCI: Use pci_find_ht_capability() in drivers/pci/quirks.c Use pci_find_ht_capability() in drivers/pci/quirks.c. I'm pretty sure the logic is unchanged here, but someone please eye-ball it for me. I've changed the message to be a little shorter, it's now: PCI: Found (enabled|disabled) HT MSI mapping on xxxx:xx:xx.x Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
0c875c28 |
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03-Dec-2006 |
David Rientjes <rientjes@cs.washington.edu> |
PCI quirks: remove redundant check Removes redundant check for dev->subordinate; if it is NULL, the function returns before the patch-affected code region. Signed-off-by: David Rientjes <rientjes@cs.washington.edu> Acked-by: Brice Goglin <brice@myri.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
368c73d4 |
|
03-Oct-2006 |
Alan Cox <alan@lxorguk.ukuu.org.uk> |
PCI: quirks: fix the festering mess that claims to handle IDE quirks The number of permutations of crap we do is amazing and almost all of it has the wrong effect in 2.6. At the heart of this is the PCI SFF magic which says that compatibility mode PCI IDE controllers use ISA IRQ routing and hard coded addresses not the BAR values. The old quirks variously clears them, sets them, adjusts them and then IDE ignores the result. In order to drive all this garbage out and to do it portably we need to handle the SFF rules directly and properly. Because we know the device BAR 0-3 are not used in compatibility mode we load them with the values that are implied (and indeed which many controllers actually thoughtfully put there in this mode anyway). This removes special cases in the IDE layer and libata which now knows that bar 0/1/2/3 always contain the correct address. It means our resource allocation map is accurate from boot, not "mostly accurate" after ide is loaded, and it shoots lots of code. There is also lots more code and magic constant knowledge to shoot once this is in and settled. Been in my test tree for a while both with drivers/ide and with libata. Wants some -mm shakedown in case I've missed something dumb or there are corner cases lurking. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
d8f79751 |
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14-Nov-2006 |
Andrew Morton <akpm@osdl.org> |
[PATCH] revert "PCI: quirk for IBM Dock II cardbus controllers" Fix http://bugzilla.kernel.org/show_bug.cgi?id=7264 We need to target this quirk a little more tightly, using the T20 DMI string. Cc: Pavel Kysilka <goldenfish@bsys.cz> Acked-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: Dominik Brodowski <linux@dominikbrodowski.net> Cc: Daniel Ritz <daniel.ritz@gmx.ch> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
3560cc5e |
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20-Oct-2006 |
Karsten Wiese <annabellesgarden@yahoo.de> |
PCI: Remove quirk_via_abnormal_poweroff My K8T800 mobo resumes fine from suspend to ram with and without patch applied against 2.6.18. quirk_via_abnormal_poweroff makes some boards not boot 2.6.18, so IMO patch should go to head, 2.6.18.2 and everywhere "ACPI: ACPICA 20060623" has been applied. Remove quirk_via_abnormal_poweroff Obsoleted by "ACPI: ACPICA 20060623": <snip> Implemented support for "ignored" bits in the ACPI registers. According to the ACPI specification, these bits should be preserved when writing the registers via a read/modify/write cycle. There are 3 bits preserved in this manner: PM1_CONTROL[0] (SCI_EN), PM1_CONTROL[9], and PM1_STATUS[11]. http://bugzilla.kernel.org/show_bug.cgi?id=3691 </snip> Signed-off-by: Karsten Wiese <fzu@wemgehoertderstaat.de> Cc: Bob Moore <robert.moore@intel.com> Cc: "Brown, Len" <len.brown@intel.com> Acked-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
6b5c76b8 |
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23-Oct-2006 |
Eiichiro Oiwa <eiichiro.oiwa.nm@hitachi.com> |
PCI: fix pci_fixup_video as it blows up on sparc64 This reverts much of the original pci_fixup_video change and makes it work for all arches that need it. fixed, and tested on x86, x86_64 and IA64 dig. Signed-off-by: Eiichiro Oiwa <eiichiro.oiwa.nm@hitachi.com> Acked-by: David Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
0c0e4668 |
|
23-Oct-2006 |
Linus Torvalds <torvalds@g5.osdl.org> |
Revert unintentional and bogus change to drivers/pci/quirks.c In commit 4e8a5201506423e0241202de1349422af4260296 ("[PKT_SCHED] netem: Orphan SKB when adding to queue.") Davem mistakenly also included a temporary diff in his tree that disabled the pci_fixup_video VGA quirk, which broke sparc64. This reverts that part of the commit. Sayeth Davem: "Greg KH has a patch coming to you soon which will move that VGA code back into x86/x86_64/IA64 specific areas and will fix the sparc64 problem properly." Special thanks to Claudio Martins <ctpm@ist.utl.pt> for noticing the error in the first place. Cc: Claudio Martins <ctpm@ist.utl.pt> Cc: David Miller <davem@davemloft.net> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
4e8a5201 |
|
22-Oct-2006 |
David S. Miller <davem@sunset.davemloft.net> |
[PKT_SCHED] netem: Orphan SKB when adding to queue. The networking emulator can queue SKBs for a very long time, so if you're using netem on the sender side for large bandwidth/delay product testing, the SKB socket send queue sizes become artificially larger. Correct this by calling skb_orphan() in netem_enqueue(). Signed-off-by: David S. Miller <davem@davemloft.net>
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#
11f242f0 |
|
10-Oct-2006 |
Alan Cox <alan@lxorguk.ukuu.org.uk> |
PCI: quirks: switch quirks code offender to use pci_get API Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
b5e4efe7 |
|
27-Sep-2006 |
eiichiro.oiwa.nm@hitachi.com <eiichiro.oiwa.nm@hitachi.com> |
PCI: Turn pci_fixup_video into generic for embedded VGA pci_fixup_video turns into generic code because there are many platforms need this fixup for embedded VGA as well as x86. The Video BIOS integrates into System BIOS on a machine has embedded VGA although embedded VGA generally don't have PCI ROM. As a result, embedded VGA need the way that the sysfs rom points to the Video BIOS of System RAM (0xC0000). PCI-to-PCI Bridge Architecture specification describes the condition whether or not PCI ROM forwards VGA compatible memory address. fixup_video suits this specification. Although the Video ROM generally implements in x86 code regardless of platform, some application such as X Window System can run this code by dosemu86. Therefore, pci_fixup_video should turn into generic code. Signed-off-by: Eiichiro Oiwa <eiichiro.oiwa.nm@hitachi.com> Acked-by: Alan Cox <alan@redhat.com> Acked-by: Jesse Barnes <jesse.barnes@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
bacedce3 |
|
25-Sep-2006 |
Daniel Ritz <daniel.ritz-ml@swissonline.ch> |
PCI: add ICH7/8 ACPI/GPIO io resource quirks Signed-off-by: Daniel Ritz <daniel.ritz@gmx.ch> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
09d6029f |
|
25-Sep-2006 |
Daniel Drake <dsd@gentoo.org> |
PCI: VIA IRQ quirk behaviour change The most recent VIA IRQ quirk changes have broken various VIA devices for some users. We are not able to add these devices to the blacklist as they are also available in PCI-card form, and running the quirk on these devices brings us back to square one (running the VIA quirk on non-VIA boards where the quirk is not needed). This patch, based on suggestions from Sergey Vlasov, implements a scheme similar to but more restrictive than the scheme we had in 2.6.16 and earlier. It runs the quirk on all VIA hardware, but *only* if a VIA southbridge was detected on the system. To further reduce the amount of quirked devices, this patch includes a change suggested by Linus at http://lkml.org/lkml/2005/9/27/113 This ensures that devices bound to non-legacy IO-APIC interrupt lines are not quirked. We have made one change to Linus' suggestion: we do a comparison of ">15" rather than ">=15", as 15 is still in the legacy interrupt range. There is still a downside to this patch: if the user inserts a VIA PCI card into a VIA-based motherboard, in some circumstances the quirk will also run on the VIA PCI card. This corner case is hard to avoid. Signed-off-by: Daniel Drake <dsd@gentoo.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
236561e5 |
|
01-Oct-2006 |
Alan Cox <alan@lxorguk.ukuu.org.uk> |
[PATCH] PCI quirks update This fixes two things Firstly someone mistakenly used "errata" for the singular. This causes Dave Woodhouse to emit diagnostics whenever the string is read, and so should be fixed. Secondly the AMD AGP tunnel has an erratum which causes hangs if you try and do direct PCI to AGP transfers in some cases. We have a flag for PCI/PCI failures but we need a different flag for this really as in this case we don't want to stop PCI/PCI transfers using things like IOAT and the new RAID offload work. I'll post some updates to make proper use of the PCIAGP flag in the media/video drivers to Mauro. Signed-off-by: Alan Cox <alan@redhat.com> Cc: David Woodhouse <dwmw2@infradead.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
6397c75c |
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30-Aug-2006 |
Brice Goglin <brice@myri.com> |
MSI: Blacklist PCI-E chipsets depending on Hypertransport MSI capability Introduce msi_ht_cap_enabled() to check the MSI capability in the Hypertransport configuration space. It is used in a generic quirk quirk_msi_ht_cap() to check whether MSI is enabled on hypertransport chipset, and a nVidia specific quirk quirk_nvidia_ck804_msi_ht_cap() where two 2 HT MSI mappings have to be checked. Both quirks set the PCI_BUS_FLAGS_NO_MSI bus flag when MSI is disabled. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
3f79e107 |
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30-Aug-2006 |
Brice Goglin <brice@myri.com> |
MSI: Cleanup existing MSI quirks Move MSI quirks in CONFIG_PCI_MSI, document why the serverworks quirk does not simply set PCI_BUS_FLAGS_NO_MSI, and create a generic quirk for other chipsets where setting PCI_BUS_FLAGS_NO_MSI is fine. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
1ae4f9ba |
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28-Aug-2006 |
Mark Hindley <mark@hindley.org.uk> |
USB: Add VIA quirk fixup for VT8235 usb2 Patch to add VIA PCI quirk for Enhanced/Extended USB on VT8235 southbridge. It is needed in order to use EHCI/USB 2.0 with ACPI. Without it IRQs are not routed correctly, you get an "Unlink after no-IRQ?" error and the device is unusable. I belive this could also be a fix for Bugzilla Bug 5835. Signed-off-by: Mark Hindley <mark@hindley.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
65ae4ddd |
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22-Aug-2006 |
Daniel Ritz <daniel.ritz-ml@swissonline.ch> |
[PATCH] PCI: fix ICH6 quirks - add the ICH6(R) LPC to the ICH6 ACPI quirks. currently only the ICH6-M is handled. [ PCI_DEVICE_ID_INTEL_ICH6_1 is the ICH6-M LPC, ICH6_0 is the ICH6(R) ] - remove the wrong quirk calling asus_hides_smbus_lpc() for ICH6. the register modified in asus_hides_smbus_lpc() has a different meaning in ICH6. Signed-off-by: Daniel Ritz <daniel.ritz@gmx.ch> Acked-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
77967052 |
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18-Aug-2006 |
Tejun Heo <htejun@gmail.com> |
[PATCH] libata: s/CONFIG_SCSI_SATA/CONFIG_[S]ATA/g in pci/quirks.c drivers/pci/quirks.c was not updated when libata config constants were renamed braking several libata quirks. Fix it. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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#
321311af |
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31-Jul-2006 |
Jean Delvare <khali@linux-fr.org> |
PCI: Unhide the SMBus on Asus PU-DLS Unhide the SMBus controller on the Asus PU-DLS board. This fixes bug #6763. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
16a74744 |
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05-Apr-2006 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
PCI: quirk to disable e100 interrupt if RESET failed to Without this quirk, e100 can be pulling on a shared interrupt line when another device (eg. USB) loads, causing the interrupt to scream and get disabled. http://bugzilla.kernel.org/show_bug.cgi?id=5918 Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Len Brown <len.brown@intel.com>
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#
ffadcc2f |
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12-Jul-2006 |
Kristen Carlson Accardi <kristen.c.accardi@intel.com> |
[PATCH] PCI: PCIE power management quirk When changing power states from D0->DX and then from DX->D0, some Intel PCIE chipsets will cause a device reset to occur. This will cause problems for any D State other than D3, since any state information that the driver will expect to be present coming from a D1 or D2 state will have been cleared. This patch addes a flag to the pci_dev structure to indicate that devices should not use states D1 or D2, and will set that flag for the affected chipsets. This patch also modifies pci_set_power_state() so that when a device driver tries to set the power state on a device that is downstream from an affected chipset, or on one of the affected devices it only allows state changes to or from D0 & D3. In addition, this patch allows the delay time between D3->D0 to be changed via a quirk. These chipsets also need additional time to change states beyond the normal 10ms. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
709cf5ea |
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30-Jun-2006 |
Matthew Garrett <mjg59@srcf.ucam.org> |
[PATCH] PCI: Clear abnormal poweroff flag on VIA southbridges, fix resume Some VIA southbridges contain a flag in the ACPI register space that indicates whether an abnormal poweroff has occured, presumably with the intention that it can be cleared on clean shutdown. Some BIOSes check this flag at resume time, and will re-POST the system rather than jump back to the OS if it's set. Clearing it at boot time appears to be sufficient. I'm not sure if drivers/pci/quirks.c is the right place to do it, but I'm not sure where would be cleaner. [akpm@osdl.org: cleanups, build fix] Signed-off-by: Matthew Garrett <mjg59@srcf.ucam.org> Cc: Greg KH <greg@kroah.com> Cc: "Brown, Len" <len.brown@intel.com> Cc: "Yu, Luming" <luming.yu@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
15e0c694 |
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12-Jul-2006 |
Alan Cox <alan@lxorguk.ukuu.org.uk> |
[PATCH] ide: fix Jmicron support Prior to 2.6.18rc1 you could install with devices on a JMicron chipset using the "all-generic-ide" option. As of this kernel the AHCI driver grabs the controller and rams it into AHCI mode losing the PATA ports and making CD drives and the like vanish. The all-generic-ide option fails because the AHCI driver grabbed the PCI device and reconfigured it. To fix this three things are needed. #1 We must put the chip into dual function mode #2 The AHCI driver must grab only function 0 (already in your rc1 tree) #3 Something must grab the PATA ports The attached patch is the minimal risk edition of this. It puts the chip into dual function mode so that AHCI will grab the SATA ports without losing the PATA ports. To keep the risk as low as possible the third patch adds the PCI identifiers for the PATA port and the FN check to the ide-generic driver. There is a more featured jmicron driver on its way but that adds risk and the ide-generic support is sufficient to install and run a system. The actual chip setup done by the quirk is the precise setup recommended by the vendor. (The JMB368 appears only in the ide-generic entry as it has no AHCI so does not need the quirk) Signed-off-by: Alan Cox <alan@redhat.com> Acked-by: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
c6764664 |
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12-Jul-2006 |
Linus Torvalds <torvalds@g5.osdl.org> |
Add PIIX4 APCI quirk for the 440MX chipset too This is confirmed to fix a hang due to PCI resource conflicts with setting up the Cardbus bridge on old laptops with the 440MX chipsets. Original report by Alessio Sangalli, lspci debugging help by Pekka Enberg, and trial patch suggested by Daniel Ritz: "From the docs available i would _guess_ this thing is really similar to the 82443BX/82371AB combination. at least the SMBus base address register is hidden at the very same place (32bit at 0x90 in function 3 of the "south" brigde)" The dang thing is largely undocumented, but the patch was corroborated by Asit Mallick: "I am trying to find the register information. 440MX is an integration of 440BX north-bridge without AGP and PIIX4E (82371EB). PIIX4 quirk should cover the ACPI and SMBus related I/O registers." and verified to fix the problem by Alessio. Cc: Daniel Ritz <daniel.ritz-ml@swissonline.ch> Cc: Asit Mallick <asit.k.mallick@intel.com> Cc: Pekka Enberg <penberg@cs.helsinki.fi> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Dmitry Torokhov <dtor_core@ameritech.net> Tested-by: Alessio Sangalli <alesan@manoweb.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
6ab3d562 |
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30-Jun-2006 |
Jörn Engel <joern@wohnheim.fh-wedel.de> |
Remove obsolete #include <linux/config.h> Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
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#
cf34a8e0 |
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13-Jun-2006 |
Brice Goglin <brice@myri.com> |
[PATCH] PCI: nVidia quirk to make AER PCI-E extended capability visible The nVidia CK804 PCI-E chipset supports the AER extended capability but sometimes fails to link it (with some BIOS or after a warm reboot). It makes the AER cap invisible to pci_find_ext_capability(). The patch adds a quirk to set the missing bit that controls the linking of the capability. By the way, it removes the corresponding code in the myri10ge driver. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Loic Prylli <loic@myri.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
bd91fde9 |
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05-Jun-2006 |
Chris Wedgwood <cw@f00f.org> |
[PATCH] PCI: MSI-K8T-Neo2-Fir: run only where needed Be more selective when running the MSI-K8T-Neo2Fir soundcard PCI quirk so as not to run this on hardware where it's probably not needed. Signed-off-by: Chris Wedgwood <cw@f00f.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
bd8481e1 |
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08-May-2006 |
Doug Thompson <norsk5@yahoo.com> |
[PATCH] PCI Bus Parity Status-broken hardware attribute, EDAC foundation Currently, the EDAC (error detection and correction) modules that are in the kernel contain some features that need to be moved. After some good feedback on the PCI Parity detection code and interface (http://www.ussg.iu.edu/hypermail/linux/kernel/0603.1/0897.html) this patch ADDs an new attribute to the pci_dev structure: Namely the 'broken_parity_status' bit. When set this indicates that the respective hardware generates false positives of Parity errors. The EDAC "blacklist" solution was inferior and will be removed in a future patch. Also in this patch is a PCI quirk.c entry for an Infiniband PCI-X card which generates false positive parity errors. I am requesting comments on this AND on the possibility of a exposing this 'broken_parity_status' bit to userland via the PCI device sysfs directory for devices. This access would allow for enabling of this feature on new devices and for old devices that have their drivers updated. (SLES 9 SP3 did this on an ATI motherboard video device). There is a need to update such a PCI attribute between kernel releases. This patch just adds a storage place for the attribute and a quirk entry for a known bad PCI device. PCI Parity reaper/harvestor operations are in EDAC itself and will be refactored to use this PCI attribute instead of its own mechanisms (which are currently disabled) in the future. Signed-off-by: Doug Thompson <norsk5@xmission.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
ce007ea5 |
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15-May-2006 |
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> |
[PATCH] smbus unhiding kills thermal management Do not enable the SMBus device on Asus boards if suspend is used. We do not reenable the device on resume, leading to all sorts of undesirable effects, the worst being a total fan failure after resume on Samsung P35 laptop. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Pavel Machek <pavel@suse.cz> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
a7b862f6 |
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15-May-2006 |
Chris Wedgwood <cw@f00f.org> |
[PATCH] VIA quirk fixup, additional PCI IDs An earlier commit (75cf7456dd87335f574dcd53c4ae616a2ad71a11) changed an overly-zealous PCI quirk to only poke those VIA devices that need it. However, some PCI devices were not included in what I hope is now the full list. Consequently we're failing to run the quirk on all machines which need it, causing IRQ routing failures. This should I hope correct this. Thanks to Masoud Sharbiani <masouds@masoud.ir> for pointing this out and testing the fix. Signed-off-by: Chris Wedgwood <cw@f00f.org> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
75cf7456 |
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19-Apr-2006 |
Chris Wedgwood <cw@f00f.org> |
[PATCH] PCI quirk: VIA IRQ fixup should only run for VIA southbridges Alan Cox pointed out that the VIA 'IRQ fixup' was erroneously running on my system which has no VIA southbridge (but I do have a VIA IEEE 1394 device). This should address that. I also changed "Via IRQ" to "VIA IRQ" (initially I read Via as a capitalized via (by way/means of). Signed-off-by: Chris Wedgwood <cw@f00f.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
7daa0c4f |
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20-Apr-2006 |
Johannes Goecke <goecke@upb.de> |
[PATCH] MSI-K8T-Neo2-Fir OnboardSound and additional Soundcard On the MSI-K8T-NEO2 FIR ( Athlon-64, Socket 939 with VIA-K8T800- Chipset and onboard Sound,... ) the BIOS lets you choose "DISABLED" or "AUTO" for the On-Board Sound Device. If you add another PCI-Sound-Card the BIOS disables the on-board device. So far I have a Quirk, that does set the correspondent BIT in the PCI-registers to enable the soundcard. But how to ensure that the code is executed ONLY on excactly this kind of boards (not any other with similar Chipset)? Cc: Jaroslav Kysela <perex@suse.cz> Acked-by: Takashi Iwai <tiwai@suse.de> Cc: Lee Revell <rlrevell@joe-job.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
2d1e1c75 |
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01-Apr-2006 |
Jean Delvare <khali@linux-fr.org> |
[PATCH] PCI: Add PCI quirk for SMBus on the Asus A6VA notebook The Asus A6VA notebook was reported to need a PCI quirk to unhide the SMBus. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
5da594b1 |
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20-Mar-2006 |
John W. Linville <linville@tuxdriver.com> |
[PATCH] pci_ids.h: correct naming of 1022:7450 (AMD 8131 Bridge) The naming of the constant defined for PCI ID 1022:7450 does not seem to match the information at http://pciids.sourceforge.net/: http://pci-ids.ucw.cz/iii/?i=1022 There 1022:7450 is listed as "AMD-8131 PCI-X Bridge" while 1022:7451 is listed as "AMD-8131 PCI-X IOAPIC". Yet, the current definition for 0x7450 is PCI_DEVICE_ID_AMD_8131_APIC. It seems to me like that name should map to 0x7451, while a name like PCI_DEVICE_ID_AMD_8131_BRIDGE should map to 0x7450. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
6e325a62 |
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14-Feb-2006 |
Michael S. Tsirkin <mst@mellanox.co.il> |
[PATCH] PCI: make MSI quirk inheritable from the pci bus It turns out AMD 8131 quirk only affects MSI for devices behind the 8131 bridge. Handle this by adding a flags field in pci_bus, inherited from parent to child. Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
e5548e96 |
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28-Feb-2006 |
Bauke Jan Douma <bjdouma@xs4all.nl> |
[PATCH] PCI: quirk for asus a8v and a8v delux motherboards On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller and MC97 modem controller are deactivated when a second PCI soundcard is present. This patch enables them. Signed-off-by: Bauke Jan Douma <bjdouma@xs4all.nl> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
3c0a654e |
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19-Feb-2006 |
tomek@koprowski.org <tomek@koprowski.org> |
[PATCH] PCI: SMBus unhide on HP Compaq nx6110 I attach a trivial patch for 2.6.15.4 that unhides SMBus controller on an HP Compaq nx6110 notebook. Signed-off-by: Tomasz Koprowski <tomek@koprowski.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
c408a379 |
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17-Jan-2006 |
Kristen Accardi <kristen.c.accardi@intel.com> |
[PATCH] PCI: quirk for IBM Dock II cardbus controllers The IBM Dock II cardbus bridges require some extra configuration before Yenta is loaded in order to setup the Interrupts to be routed properly. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
012b265f |
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17-Jan-2006 |
Jason Gaston <jason.d.gaston@intel.com> |
[PATCH] Intel ICH8 SATA: add PCI device IDs Signed-off-by: �Jason Gaston <Jason.d.gaston@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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#
9d265124 |
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05-Dec-2005 |
Daniel Yeisley <dan.yeisley@unisys.com> |
[PATCH] PCI Quirk: 1K I/O space granularity on Intel P64H2 I've implemented a quirk to take advantage of the 1KB I/O space granularity option on the Intel P64H2 PCI Bridge. I had to change probe.c because it sets the resource start and end to be aligned on 4k boundaries (after the quirk sets them to 1k boundaries). I've tested this patch on a Unisys ES7000-600 both with and without the 1KB option enabled. I also tested this on a 2 processor Dell box that doesn't have a P64H2 to make sure there were no negative affects there. Signed-off-by: Dan Yeisley <dan.yeisley@unisys.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
2bd0fa3b |
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13-Dec-2005 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
[PATCH] add boot option to control Intel SATA/PATA combined mode Combined mode sucks. Especially when both libata and the legacy IDE drivers try to drive ports on the same device, since that makes DMA rather difficult. This patch addresses the problem by allowing the user to control which driver binds to the ports in a combined mode configuration. In many cases, they'll probably want the libata driver to control both ports since it can use DMA for talking with ATAPI devices (when libata.atapi_enabled=1 of course). It also allows the user to get old school behavior by letting the legacy IDE driver bind to both ports. But neither is forced, the patch doesn't change current behavior unless one of combined_mode=ide or combined_mode=libata is passed on the boot line. Either of those options may require you to access your devices via different device nodes (/dev/hd* in the ide case and /dev/sd* in the libata case), though of course if you have udev installed nicely you may not notice anything. :) Let me know if the documentation is too cryptic, I'd be happy to expand on it if necessary. I think most users will want to boot with 'combined_mode=libata' and add 'options libata atapi_enabled=1' to their modules.conf to get good DVD playing and disk behavior (haven't tested CD or DVD writing though). I'd much rather things behave sanely by default (i.e. DMA for devices on both ports), but apparently that's difficult given the various chip bugs and hardware configs out there (not to mention that people's drives may suddenly change from /dev/hdc to /dev/sdb), so this boot option may be the correct long term fix. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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#
a5312e28 |
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31-Oct-2005 |
Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
[PATCH] PCI: NCR 53c810 quirk Move the PPC fixup for old NCR 810 controllers to generic quirks - it's needed for Alpha, x86 and other architectures that use setup-bus.c. Thanks to Jay Estabrook for pointing out the issue. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
02f313b2 |
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29-Oct-2005 |
Meelis Roos <mroos@linux.ee> |
[PATCH] PCI: Fix VIA 686 PCI quirk names The quirk names for VIA 686 are mistyped in 2.6.14 (686 vs 868). S3 868 influence? :) Here is a patch to correct them. Signed-off-by: Meelis Roos <mroos@linux.ee> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
08db2a70 |
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30-Oct-2005 |
Linus Torvalds <torvalds@g5.osdl.org> |
Fix PIIX4 SMB region size Petr Vandrovec correctly points out that the SMB region of the PIIX4 is just 16 bytes, not 32. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
7586269c |
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23-Sep-2005 |
David Brownell <david-b@pacbell.net> |
[PATCH] USB: move handoff code This moves the PCI quirk handling for USB host controllers from the PCI directory to the USB directory. Follow-on patches will need to: (a) merge these copies with the originals in the HCD reset methods. they don't wholly agree, despite doing the very same thing; and (b) eventually change it so "usb-handoff" is the default, to help get more robust USB/BIOS/input/... interactions. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> drivers/Makefile | 2 drivers/pci/quirks.c | 253 --------------------------------------- drivers/usb/Makefile | 1 drivers/usb/host/Makefile | 5 drivers/usb/host/pci-quirks.c | 272 ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 280 insertions(+), 253 deletions(-)
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#
e3b1bd57 |
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21-Sep-2005 |
Jean Delvare <khali@linux-fr.org> |
[PATCH] PCI: Add quirk for SMBus on HP D530 One more SMBus unhiding quirk, this time for the HP D530. Requested and successfully tested by Ben Cranston. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
acc06632 |
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29-Sep-2005 |
Rudolf Marek <R.Marek@sh.cvut.cz> |
[PATCH] unhide ICH6 SMBus - take 2 This patch unhides hidden SMBus on ICH6 chipset installed in Asus M6V notebook. I would like to thank Michal Mleczko for testing and help. Signed-Off-By: Rudolf Marek <r.marek@sh.cvut.cz> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> drivers/pci/quirks.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
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#
2cea752f |
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27-Sep-2005 |
Rudolf Marek <R.Marek@sh.cvut.cz> |
[PATCH] PCI: ICH6 ACPI and GPIO quirk This patch just adds ACPI and GPIO regions to its LPC bridge, similar way as ICH4 did. I would like to thank Michal Mleczko for testing. Signed-off-by: Rudolf Marek <r.marek@sh.cvut.cz> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> drivers/pci/quirks.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
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#
6693e74a |
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25-Oct-2005 |
Linus Torvalds <torvalds@g5.osdl.org> |
PCI: be more verbose about resource quirks When reserving an PCI quirk, note that in the kernel bootup messages. Also, parse the strange PIIX4 device resources - they should get their own PCI resource quirks, but for now just print out what it finds to verify that the code does the right thing. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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#
cc675230 |
|
17-Oct-2005 |
Jeff Garzik <jgarzik@pobox.com> |
[PATCH] Fix and clean up quirk_intel_ide_combined() configuration This change makes quirk_intel_ide_combined() dependent on the precise conditions under which it is needed: * IDE is built in * IDE SATA option is not set * ata_piix or ahci drivers are enabled This fixes an issue where some modular configurations would not cause the quirk to be enabled. Signed-off-by: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: Linus torvalds <torvalds@osdl.org>
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#
c87f883e |
|
06-Sep-2005 |
Rumen Ivanov Zarev <rzarev@its.caltech.edu> |
[PATCH] PCI: Unhide SMBus on Compaq Evo N620c Trivial patch against 2.6.13 to unhide SMBus on Compaq Evo N620c laptop using Intel 82855PM chipset. Signed-off-by: Rumen Zarev <rzarev@caltech.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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#
085ae41f |
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08-Aug-2005 |
David S. Miller <davem@davemloft.net> |
[PATCH] Make sparc64 use setup-res.c There were three changes necessary in order to allow sparc64 to use setup-res.c: 1) Sparc64 roots the PCI I/O and MEM address space using parent resources contained in the PCI controller structure. I'm actually surprised no other platforms do this, especially ones like Alpha and PPC{,64}. These resources get linked into the iomem/ioport tree when PCI controllers are probed. So the hierarchy looks like this: iomem --| PCI controller 1 MEM space --| device 1 device 2 etc. PCI controller 2 MEM space --| ... ioport --| PCI controller 1 IO space --| ... PCI controller 2 IO space --| ... You get the idea. The drivers/pci/setup-res.c code allocates using plain iomem_space and ioport_space as the root, so that wouldn't work with the above setup. So I added a pcibios_select_root() that is used to handle this. It uses the PCI controller struct's io_space and mem_space on sparc64, and io{port,mem}_resource on every other platform to keep current behavior. 2) quirk_io_region() is buggy. It takes in raw BUS view addresses and tries to use them as a PCI resource. pci_claim_resource() expects the resource to be fully formed when it gets called. The sparc64 implementation would do the translation but that's absolutely wrong, because if the same resource gets released then re-claimed we'll adjust things twice. So I fixed up quirk_io_region() to do the proper pcibios_bus_to_resource() conversion before passing it on to pci_claim_resource(). 3) I was mistakedly __init'ing the function methods the PCI controller drivers provide on sparc64 to implement some parts of these routines. This was, of course, easy to fix. So we end up with the following, and that nasty SPARC64 makefile ifdef in drivers/pci/Makefile is finally zapped. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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a1740913 |
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03-Sep-2005 |
Karsten Wiese <annabellesgarden@yahoo.de> |
[PATCH] via vt8237 apic bypass deassertion quirk The VIA VT8237's IOAPIC sends 'APIC De-Assert Messages' by default, causing another CPU interrupt when the IRQ pin is de-asserted. This feature is switched off by the patch to get rid of doubled ioapic level interrupt rates. Signed-off-by: Karsten Wiese <annabellesgarden@yahoo.de> Tested-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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4602b88d |
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16-Aug-2005 |
Kristen Accardi <kristen.c.accardi@intel.com> |
[PATCH] PCI: 6700/6702PXH quirk On the 6700/6702 PXH part, a MSI may get corrupted if an ACPI hotplug driver and SHPC driver in MSI mode are used together. This patch will prevent MSI from being enabled for the SHPC as part of an early pci quirk, as well as on any pci device which sets the no_msi bit. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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6d85f29b |
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07-Aug-2005 |
Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
[PATCH] VIA VT8235 PCI quirk Like many other southbridges from different manufacturers, VIA VT8235 chip has two non-standard BARs for power management and SMBus registers (see the datasheet at http://www.via.com.tw). This new quirk routine fixes boot problem with 2.6.13-rc2/rc6 kernels on Targa Visionary 811 Athlon64 laptop, as reported by Mikael Pettersson <mikpe@csd.uu.se>. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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e96e2f14 |
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29-Jul-2005 |
Daniele Gaffuri <d.gaffuri@reply.it> |
[PATCH] PCI: Hidden SMBus bridge on Toshiba Tecra M2 Patch against 2.6.12 to unhide SMBus on Toshiba Centrino laptops using Intel 82855PM chipset. Tested on Toshiba Tecra M2. Signed-off-by: Daniele Gaffuri <d.gaffuri@reply.it> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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a00db371 |
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29-Jun-2005 |
Jean Delvare <khali@linux-fr.org> |
[PATCH] PCI: Add PCI quirk for SMBus on the Asus P4B-LX One more Asus motherboard requiring the SMBus quirk (P4B-LX). Original patch from Salah Coronya. Signed-off-by: Salah Coronya <salahx@yahoo.com> Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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1e062767 |
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06-May-2005 |
Narendra Sankar <nsankar@broadcom.com> |
[PATCH] PCI: MSI functionality broken on Serverworks GC chipset MSI functionality is broken on the GC_LE x86 chipset that Serverworks developed and that is being used in various platforms today. Broadcom is going to push out to the kernel MSI enabled Gigabit drivers (in the very near future), and we would like to make sure that MSI does not get enabled on any platforms using the GC_LE chipset (device id 0x17). Following the AMD 8131 example, I am including a patch to disable MSI functionality when a GCNB_LE is detected. Please let me know if there are any issues with this. This is a permanent fix for this chipset, as the hardware will not be updated. Signed-off-by: Narendra Sankar <nsankar@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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93cffffa |
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07-Jun-2005 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
[PATCH] PCI: do VIA IRQ fixup always, not just in PIC mode At least some VIA chipsets require the fixup even in IO-APIC mode. This was found and debugged with the patient assistance of Stian Jordet <liste@jordet.nu> on an Asus CUV266-DLS motherboard. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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9920e914 |
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26-May-2005 |
Alexander Nyberg <alexn@telia.com> |
[PATCH] Fixup VIA IRQ quirk quirk_via_irqpic can't be __devinit for swsuspend Signed-off-by: Alexander Nyberg <alexn@telia.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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25be5e6c |
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27-May-2005 |
Len Brown <lenb@toshiba.hsd1.ma.comcast.net> |
[PATCH] VIA IRQ quirk Delete quirk_via_bridge(), restore quirk_via_irqpic() -- but now improved to be invoked upon device ENABLE, and now only for VIA devices -- not all devices behind VIA bridges. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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3aa8c4fe |
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21-Apr-2005 |
Rudolf Marek <R.Marek@sh.cvut.cz> |
[PATCH] PCI: Rapid Hance quirk This patch just adds Intel's Hance Rapid south bridge IDs to ICH4 region quirk. Patch was successfuly tested by Chunhao Huang from Winbond. Signed-Off-By: Rudolf Marek <r.marek@sh.cvut.cz> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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bc56b9e0 |
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07-Apr-2005 |
Greg Kroah-Hartman <gregkh@suse.de> |
[PATCH] PCI: Clean up a lot of sparse "Should it be static?" warnings. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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c368ca4e |
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16-Apr-2005 |
Jason Gaston <jason.d.gaston@intel.com> |
[PATCH] ata_piix: IDE mode SATA patch for Intel ESB2 This patch adds the Intel ESB2 DID's to the ata_piix.c and quirks.c file for IDE mode SATA support. Signed-off-by: Jason Gaston <Jason.d.gaston@intel.com> Cc: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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1da177e4 |
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16-Apr-2005 |
Linus Torvalds <torvalds@ppc970.osdl.org> |
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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