/linux-master/drivers/pwm/ |
H A D | pwm-dwc-core.c | 70 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); 78 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm)); 79 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm)); 88 dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm)); 93 __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled); 112 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); 129 ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); 130 ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); 131 ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
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H A D | core.c | 588 pwm->hwpwm = i;
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H A D | pwm-img.c | 133 val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm)); 135 PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm); 140 img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val); 159 val |= BIT(pwm->hwpwm); 164 PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm)); 175 val &= ~BIT(pwm->hwpwm);
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H A D | sysfs.c | 263 dev_set_name(&export->child, "pwm%u", pwm->hwpwm); 272 pwm_prop[0] = kasprintf(GFP_KERNEL, "EXPORT=pwm%u", pwm->hwpwm); 297 pwm_prop[0] = kasprintf(GFP_KERNEL, "UNEXPORT=pwm%u", pwm->hwpwm); 316 unsigned int hwpwm; local 319 ret = kstrtouint(buf, 0, &hwpwm); 323 if (hwpwm >= chip->npwm) 326 pwm = pwm_request_from_chip(chip, hwpwm, "sysfs"); 343 unsigned int hwpwm; local 346 ret = kstrtouint(buf, 0, &hwpwm); 350 if (hwpwm > [all...] |
H A D | pwm-vt8500.c | 108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); 109 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_SCALAR_UPDATE); 111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); 112 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_PERIOD_UPDATE); 114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); 115 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_DUTY_UPDATE); 117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); 119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); 120 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_CTRL_UPDATE); 138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); [all...] |
H A D | pwm-twl-led.c | 96 base = pwm->hwpwm * 2 + TWL4030_PWMA_REG; 120 val |= TWL4030_LED_TOGGLE(pwm->hwpwm, TWL4030_LED_PINS); 145 val &= ~TWL4030_LED_TOGGLE(pwm->hwpwm, TWL4030_LED_PINS);
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H A D | pwm-twl.c | 82 base = pwm->hwpwm * 3; 106 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); 112 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); 136 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); 142 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); 158 if (pwm->hwpwm == 1) { 196 if (pwm->hwpwm == 1) 228 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); 229 val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); 251 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMX [all...] |
H A D | pwm-visconti.c | 52 writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm)); 98 writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm)); 99 writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm)); 100 writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm)); 111 period = readl(priv->base + PIPGM_PCSR(pwm->hwpwm)); 112 duty = readl(priv->base + PIPGM_PDUT(pwm->hwpwm)); 113 pwmc0 = readl(priv->base + PIPGM_PWMC(pwm->hwpwm));
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H A D | pwm-tiehrpwm.c | 255 if (i == pwm->hwpwm) 265 pc->period_cycles[pwm->hwpwm] = period_cycles; 292 if (pwm->hwpwm == 1) 313 pc->polarity[pwm->hwpwm] = polarity; 328 if (pwm->hwpwm) { 343 configure_polarity(pc, pwm->hwpwm); 362 if (pwm->hwpwm) { 400 pc->period_cycles[pwm->hwpwm] = 0;
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H A D | pwm-tegra.c | 200 pwm_writel(pc, pwm->hwpwm, val); 221 val = pwm_readl(pc, pwm->hwpwm); 223 pwm_writel(pc, pwm->hwpwm, val); 233 val = pwm_readl(pc, pwm->hwpwm); 235 pwm_writel(pc, pwm->hwpwm, val);
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H A D | pwm-sunplus.c | 68 mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); 72 mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); 100 writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm)); 104 mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); 106 mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); 109 mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); 110 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; 112 mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); 118 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; 120 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); [all...] |
H A D | pwm-stm32.c | 107 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; 108 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; 109 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; 201 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 202 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? 207 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? 208 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? 255 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 301 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); 442 stm32_pwm_disable(priv, pwm->hwpwm); [all...] |
H A D | pwm-sun4i.c | 129 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && 138 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && 142 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; 147 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) 152 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == 153 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) 158 val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm)); 266 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); 273 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); 276 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) ! [all...] |
H A D | pwm-stmpe.c | 47 pwm->hwpwm); 51 value = ret | BIT(pwm->hwpwm); 56 pwm->hwpwm); 73 pwm->hwpwm); 77 value = ret & ~BIT(pwm->hwpwm); 82 pwm->hwpwm); 117 pin = pwm->hwpwm; 128 pwm->hwpwm); 134 switch (pwm->hwpwm) { 153 pwm->hwpwm, duty_n [all...] |
H A D | pwm-sti.c | 191 ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) || 192 ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) || 229 ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value); 235 set_bit(pwm->hwpwm, &pc->configured); 274 pwm->hwpwm, ret); 309 clear_bit(pwm->hwpwm, &pc->configured); 317 struct sti_cpt_ddata *ddata = &cdata->ddata[pwm->hwpwm]; 323 if (pwm->hwpwm > [all...] |
H A D | pwm-sifive.c | 115 duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); 193 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
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H A D | pwm-sprd.c | 75 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 87 pwm->hwpwm); 91 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); 105 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); 110 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); 126 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); 157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); 158 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); 167 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; [all...] |
H A D | pwm-spear.c | 126 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, 128 spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc); 129 spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv); 145 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); 147 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); 157 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); 159 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val);
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H A D | pwm-samsung.c | 123 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 233 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { 236 pwm->hwpwm); 240 memset(&our_chip->channel[pwm->hwpwm], 0, sizeof(our_chip->channel[pwm->hwpwm])); 248 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 264 our_chip->disabled_mask &= ~BIT(pwm->hwpwm); 274 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 288 if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U) 291 our_chip->disabled_mask |= BIT(pwm->hwpwm); [all...] |
H A D | pwm-rz-mtu3.c | 132 rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) argument 138 if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) 146 u32 hwpwm) 152 priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm); 157 if (priv->map->base_pwm_number == hwpwm) 172 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 201 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 224 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 229 if (priv->map->base_pwm_number == pwm->hwpwm) 250 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 145 rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) argument [all...] |
H A D | pwm-renesas-tpu.c | 217 if (pwm->hwpwm >= TPU_CHANNEL_MAX) 220 tpd = &tpu->tpd[pwm->hwpwm]; 223 tpd->channel = pwm->hwpwm; 237 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 246 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 355 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 365 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 388 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
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H A D | pwm-pxa.c | 75 offset = pwm->hwpwm ? 0x10 : 0;
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H A D | pwm-pca9685.c | 386 pca9685_pwm_set_duty(chip, pwm->hwpwm, 0); 392 if (!pca9685_prescaler_can_change(pca, pwm->hwpwm)) { 416 pca9685_pwm_set_duty(chip, pwm->hwpwm, duty); 430 set_bit(pwm->hwpwm, pca->pwms_enabled); 432 clear_bit(pwm->hwpwm, pca->pwms_enabled); 458 if (pwm->hwpwm >= PCA9685_MAXCHAN) { 469 duty = pca9685_pwm_get_duty(chip, pwm->hwpwm); 479 if (pca9685_pwm_test_and_set_inuse(pca, pwm->hwpwm)) 482 if (pwm->hwpwm < PCA9685_MAXCHAN) { 485 set_bit(pwm->hwpwm, pc [all...] |
/linux-master/include/linux/ |
H A D | pwm.h | 71 * @hwpwm: per-chip relative index of the PWM device 80 unsigned int hwpwm; member in struct:pwm_device
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/linux-master/drivers/staging/greybus/ |
H A D | pwm.c | 179 return gb_pwm_activate_operation(chip, pwm->hwpwm); 187 gb_pwm_deactivate_operation(chip, pwm->hwpwm); 201 gb_pwm_disable_operation(chip, pwm->hwpwm); 204 err = gb_pwm_set_polarity_operation(chip, pwm->hwpwm, state->polarity); 211 gb_pwm_disable_operation(chip, pwm->hwpwm); 227 err = gb_pwm_config_operation(chip, pwm->hwpwm, duty_cycle, period); 233 return gb_pwm_enable_operation(chip, pwm->hwpwm);
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