1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2007 Ben Dooks 4 * Copyright (c) 2008 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> 6 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> 7 * Copyright (c) 2017 Samsung Electronics Co., Ltd. 8 * 9 * PWM driver for Samsung SoCs 10 */ 11 12#include <linux/bitops.h> 13#include <linux/clk.h> 14#include <linux/export.h> 15#include <linux/err.h> 16#include <linux/io.h> 17#include <linux/kernel.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/platform_device.h> 21#include <linux/pwm.h> 22#include <linux/slab.h> 23#include <linux/spinlock.h> 24#include <linux/time.h> 25 26/* For struct samsung_timer_variant and samsung_pwm_lock. */ 27#include <clocksource/samsung_pwm.h> 28 29#define REG_TCFG0 0x00 30#define REG_TCFG1 0x04 31#define REG_TCON 0x08 32 33#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc)) 34#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc)) 35 36#define TCFG0_PRESCALER_MASK 0xff 37#define TCFG0_PRESCALER1_SHIFT 8 38 39#define TCFG1_MUX_MASK 0xf 40#define TCFG1_SHIFT(chan) (4 * (chan)) 41 42/* 43 * Each channel occupies 4 bits in TCON register, but there is a gap of 4 44 * bits (one channel) after channel 0, so channels have different numbering 45 * when accessing TCON register. See to_tcon_channel() function. 46 * 47 * In addition, the location of autoreload bit for channel 4 (TCON channel 5) 48 * in its set of bits is 2 as opposed to 3 for other channels. 49 */ 50#define TCON_START(chan) BIT(4 * (chan) + 0) 51#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1) 52#define TCON_INVERT(chan) BIT(4 * (chan) + 2) 53#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3) 54#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2) 55#define TCON_AUTORELOAD(chan) \ 56 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan)) 57 58/** 59 * struct samsung_pwm_channel - private data of PWM channel 60 * @period_ns: current period in nanoseconds programmed to the hardware 61 * @duty_ns: current duty time in nanoseconds programmed to the hardware 62 * @tin_ns: time of one timer tick in nanoseconds with current timer rate 63 */ 64struct samsung_pwm_channel { 65 u32 period_ns; 66 u32 duty_ns; 67 u32 tin_ns; 68}; 69 70/** 71 * struct samsung_pwm_chip - private data of PWM chip 72 * @variant: local copy of hardware variant data 73 * @inverter_mask: inverter status for all channels - one bit per channel 74 * @disabled_mask: disabled status for all channels - one bit per channel 75 * @base: base address of mapped PWM registers 76 * @base_clk: base clock used to drive the timers 77 * @tclk0: external clock 0 (can be ERR_PTR if not present) 78 * @tclk1: external clock 1 (can be ERR_PTR if not present) 79 * @channel: per channel driver data 80 */ 81struct samsung_pwm_chip { 82 struct samsung_pwm_variant variant; 83 u8 inverter_mask; 84 u8 disabled_mask; 85 86 void __iomem *base; 87 struct clk *base_clk; 88 struct clk *tclk0; 89 struct clk *tclk1; 90 struct samsung_pwm_channel channel[SAMSUNG_PWM_NUM]; 91}; 92 93#ifndef CONFIG_CLKSRC_SAMSUNG_PWM 94/* 95 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers 96 * and some registers need access synchronization. If both drivers are 97 * compiled in, the spinlock is defined in the clocksource driver, 98 * otherwise following definition is used. 99 * 100 * Currently we do not need any more complex synchronization method 101 * because all the supported SoCs contain only one instance of the PWM 102 * IP. Should this change, both drivers will need to be modified to 103 * properly synchronize accesses to particular instances. 104 */ 105static DEFINE_SPINLOCK(samsung_pwm_lock); 106#endif 107 108static inline 109struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip) 110{ 111 return pwmchip_get_drvdata(chip); 112} 113 114static inline unsigned int to_tcon_channel(unsigned int channel) 115{ 116 /* TCON register has a gap of 4 bits (1 channel) after channel 0 */ 117 return (channel == 0) ? 0 : (channel + 1); 118} 119 120static void __pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip, 121 struct pwm_device *pwm) 122{ 123 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 124 u32 tcon; 125 126 tcon = readl(our_chip->base + REG_TCON); 127 tcon |= TCON_MANUALUPDATE(tcon_chan); 128 writel(tcon, our_chip->base + REG_TCON); 129 130 tcon &= ~TCON_MANUALUPDATE(tcon_chan); 131 writel(tcon, our_chip->base + REG_TCON); 132} 133 134static void pwm_samsung_set_divisor(struct samsung_pwm_chip *our_chip, 135 unsigned int channel, u8 divisor) 136{ 137 u8 shift = TCFG1_SHIFT(channel); 138 unsigned long flags; 139 u32 reg; 140 u8 bits; 141 142 bits = (fls(divisor) - 1) - our_chip->variant.div_base; 143 144 spin_lock_irqsave(&samsung_pwm_lock, flags); 145 146 reg = readl(our_chip->base + REG_TCFG1); 147 reg &= ~(TCFG1_MUX_MASK << shift); 148 reg |= bits << shift; 149 writel(reg, our_chip->base + REG_TCFG1); 150 151 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 152} 153 154static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *our_chip, unsigned int chan) 155{ 156 struct samsung_pwm_variant *variant = &our_chip->variant; 157 u32 reg; 158 159 reg = readl(our_chip->base + REG_TCFG1); 160 reg >>= TCFG1_SHIFT(chan); 161 reg &= TCFG1_MUX_MASK; 162 163 return (BIT(reg) & variant->tclk_mask) == 0; 164} 165 166static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *our_chip, 167 unsigned int chan) 168{ 169 unsigned long rate; 170 u32 reg; 171 172 rate = clk_get_rate(our_chip->base_clk); 173 174 reg = readl(our_chip->base + REG_TCFG0); 175 if (chan >= 2) 176 reg >>= TCFG0_PRESCALER1_SHIFT; 177 reg &= TCFG0_PRESCALER_MASK; 178 179 return rate / (reg + 1); 180} 181 182static unsigned long pwm_samsung_calc_tin(struct pwm_chip *chip, 183 unsigned int chan, unsigned long freq) 184{ 185 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 186 struct samsung_pwm_variant *variant = &our_chip->variant; 187 unsigned long rate; 188 struct clk *clk; 189 u8 div; 190 191 if (!pwm_samsung_is_tdiv(our_chip, chan)) { 192 clk = (chan < 2) ? our_chip->tclk0 : our_chip->tclk1; 193 if (!IS_ERR(clk)) { 194 rate = clk_get_rate(clk); 195 if (rate) 196 return rate; 197 } 198 199 dev_warn(pwmchip_parent(chip), 200 "tclk of PWM %d is inoperational, using tdiv\n", chan); 201 } 202 203 rate = pwm_samsung_get_tin_rate(our_chip, chan); 204 dev_dbg(pwmchip_parent(chip), "tin parent at %lu\n", rate); 205 206 /* 207 * Compare minimum PWM frequency that can be achieved with possible 208 * divider settings and choose the lowest divisor that can generate 209 * frequencies lower than requested. 210 */ 211 if (variant->bits < 32) { 212 /* Only for s3c24xx */ 213 for (div = variant->div_base; div < 4; ++div) 214 if ((rate >> (variant->bits + div)) < freq) 215 break; 216 } else { 217 /* 218 * Other variants have enough counter bits to generate any 219 * requested rate, so no need to check higher divisors. 220 */ 221 div = variant->div_base; 222 } 223 224 pwm_samsung_set_divisor(our_chip, chan, BIT(div)); 225 226 return rate >> div; 227} 228 229static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm) 230{ 231 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 232 233 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { 234 dev_warn(pwmchip_parent(chip), 235 "tried to request PWM channel %d without output\n", 236 pwm->hwpwm); 237 return -EINVAL; 238 } 239 240 memset(&our_chip->channel[pwm->hwpwm], 0, sizeof(our_chip->channel[pwm->hwpwm])); 241 242 return 0; 243} 244 245static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) 246{ 247 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 248 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 249 unsigned long flags; 250 u32 tcon; 251 252 spin_lock_irqsave(&samsung_pwm_lock, flags); 253 254 tcon = readl(our_chip->base + REG_TCON); 255 256 tcon &= ~TCON_START(tcon_chan); 257 tcon |= TCON_MANUALUPDATE(tcon_chan); 258 writel(tcon, our_chip->base + REG_TCON); 259 260 tcon &= ~TCON_MANUALUPDATE(tcon_chan); 261 tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan); 262 writel(tcon, our_chip->base + REG_TCON); 263 264 our_chip->disabled_mask &= ~BIT(pwm->hwpwm); 265 266 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 267 268 return 0; 269} 270 271static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm) 272{ 273 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 274 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 275 unsigned long flags; 276 u32 tcon; 277 278 spin_lock_irqsave(&samsung_pwm_lock, flags); 279 280 tcon = readl(our_chip->base + REG_TCON); 281 tcon &= ~TCON_AUTORELOAD(tcon_chan); 282 writel(tcon, our_chip->base + REG_TCON); 283 284 /* 285 * In case the PWM is at 100% duty cycle, force a manual 286 * update to prevent the signal from staying high. 287 */ 288 if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U) 289 __pwm_samsung_manual_update(our_chip, pwm); 290 291 our_chip->disabled_mask |= BIT(pwm->hwpwm); 292 293 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 294} 295 296static void pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip, 297 struct pwm_device *pwm) 298{ 299 unsigned long flags; 300 301 spin_lock_irqsave(&samsung_pwm_lock, flags); 302 303 __pwm_samsung_manual_update(our_chip, pwm); 304 305 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 306} 307 308static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, 309 int duty_ns, int period_ns, bool force_period) 310{ 311 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 312 struct samsung_pwm_channel *chan = &our_chip->channel[pwm->hwpwm]; 313 u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp; 314 315 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); 316 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm)); 317 318 /* We need tick count for calculation, not last tick. */ 319 ++tcnt; 320 321 /* Check to see if we are changing the clock rate of the PWM. */ 322 if (chan->period_ns != period_ns || force_period) { 323 unsigned long tin_rate; 324 u32 period; 325 326 period = NSEC_PER_SEC / period_ns; 327 328 dev_dbg(pwmchip_parent(chip), "duty_ns=%d, period_ns=%d (%u)\n", 329 duty_ns, period_ns, period); 330 331 tin_rate = pwm_samsung_calc_tin(chip, pwm->hwpwm, period); 332 333 dev_dbg(pwmchip_parent(chip), "tin_rate=%lu\n", tin_rate); 334 335 tin_ns = NSEC_PER_SEC / tin_rate; 336 tcnt = period_ns / tin_ns; 337 } 338 339 /* Period is too short. */ 340 if (tcnt <= 1) 341 return -ERANGE; 342 343 /* Note that counters count down. */ 344 tcmp = duty_ns / tin_ns; 345 346 /* 0% duty is not available */ 347 if (!tcmp) 348 ++tcmp; 349 350 tcmp = tcnt - tcmp; 351 352 /* Decrement to get tick numbers, instead of tick counts. */ 353 --tcnt; 354 /* -1UL will give 100% duty. */ 355 --tcmp; 356 357 dev_dbg(pwmchip_parent(chip), "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt); 358 359 /* Update PWM registers. */ 360 writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm)); 361 writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm)); 362 363 /* 364 * In case the PWM is currently at 100% duty cycle, force a manual 365 * update to prevent the signal staying high if the PWM is disabled 366 * shortly afer this update (before it autoreloaded the new values). 367 */ 368 if (oldtcmp == (u32) -1) { 369 dev_dbg(pwmchip_parent(chip), "Forcing manual update"); 370 pwm_samsung_manual_update(our_chip, pwm); 371 } 372 373 chan->period_ns = period_ns; 374 chan->tin_ns = tin_ns; 375 chan->duty_ns = duty_ns; 376 377 return 0; 378} 379 380static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, 381 int duty_ns, int period_ns) 382{ 383 return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false); 384} 385 386static void pwm_samsung_set_invert(struct samsung_pwm_chip *our_chip, 387 unsigned int channel, bool invert) 388{ 389 unsigned int tcon_chan = to_tcon_channel(channel); 390 unsigned long flags; 391 u32 tcon; 392 393 spin_lock_irqsave(&samsung_pwm_lock, flags); 394 395 tcon = readl(our_chip->base + REG_TCON); 396 397 if (invert) { 398 our_chip->inverter_mask |= BIT(channel); 399 tcon |= TCON_INVERT(tcon_chan); 400 } else { 401 our_chip->inverter_mask &= ~BIT(channel); 402 tcon &= ~TCON_INVERT(tcon_chan); 403 } 404 405 writel(tcon, our_chip->base + REG_TCON); 406 407 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 408} 409 410static int pwm_samsung_set_polarity(struct pwm_chip *chip, 411 struct pwm_device *pwm, 412 enum pwm_polarity polarity) 413{ 414 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 415 bool invert = (polarity == PWM_POLARITY_NORMAL); 416 417 /* Inverted means normal in the hardware. */ 418 pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert); 419 420 return 0; 421} 422 423static int pwm_samsung_apply(struct pwm_chip *chip, struct pwm_device *pwm, 424 const struct pwm_state *state) 425{ 426 int err, enabled = pwm->state.enabled; 427 428 if (state->polarity != pwm->state.polarity) { 429 if (enabled) { 430 pwm_samsung_disable(chip, pwm); 431 enabled = false; 432 } 433 434 err = pwm_samsung_set_polarity(chip, pwm, state->polarity); 435 if (err) 436 return err; 437 } 438 439 if (!state->enabled) { 440 if (enabled) 441 pwm_samsung_disable(chip, pwm); 442 443 return 0; 444 } 445 446 /* 447 * We currently avoid using 64bit arithmetic by using the 448 * fact that anything faster than 1Hz is easily representable 449 * by 32bits. 450 */ 451 if (state->period > NSEC_PER_SEC) 452 return -ERANGE; 453 454 err = pwm_samsung_config(chip, pwm, state->duty_cycle, state->period); 455 if (err) 456 return err; 457 458 if (!pwm->state.enabled) 459 err = pwm_samsung_enable(chip, pwm); 460 461 return err; 462} 463 464static const struct pwm_ops pwm_samsung_ops = { 465 .request = pwm_samsung_request, 466 .apply = pwm_samsung_apply, 467}; 468 469#ifdef CONFIG_OF 470static const struct samsung_pwm_variant s3c24xx_variant = { 471 .bits = 16, 472 .div_base = 1, 473 .has_tint_cstat = false, 474 .tclk_mask = BIT(4), 475}; 476 477static const struct samsung_pwm_variant s3c64xx_variant = { 478 .bits = 32, 479 .div_base = 0, 480 .has_tint_cstat = true, 481 .tclk_mask = BIT(7) | BIT(6) | BIT(5), 482}; 483 484static const struct samsung_pwm_variant s5p64x0_variant = { 485 .bits = 32, 486 .div_base = 0, 487 .has_tint_cstat = true, 488 .tclk_mask = 0, 489}; 490 491static const struct samsung_pwm_variant s5pc100_variant = { 492 .bits = 32, 493 .div_base = 0, 494 .has_tint_cstat = true, 495 .tclk_mask = BIT(5), 496}; 497 498static const struct of_device_id samsung_pwm_matches[] = { 499 { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant }, 500 { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant }, 501 { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant }, 502 { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant }, 503 { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant }, 504 {}, 505}; 506MODULE_DEVICE_TABLE(of, samsung_pwm_matches); 507 508static int pwm_samsung_parse_dt(struct pwm_chip *chip) 509{ 510 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 511 struct device_node *np = pwmchip_parent(chip)->of_node; 512 const struct of_device_id *match; 513 struct property *prop; 514 const __be32 *cur; 515 u32 val; 516 517 match = of_match_node(samsung_pwm_matches, np); 518 if (!match) 519 return -ENODEV; 520 521 memcpy(&our_chip->variant, match->data, sizeof(our_chip->variant)); 522 523 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { 524 if (val >= SAMSUNG_PWM_NUM) { 525 dev_err(pwmchip_parent(chip), 526 "%s: invalid channel index in samsung,pwm-outputs property\n", 527 __func__); 528 continue; 529 } 530 our_chip->variant.output_mask |= BIT(val); 531 } 532 533 return 0; 534} 535#else 536static int pwm_samsung_parse_dt(struct pwm_chip *chip) 537{ 538 return -ENODEV; 539} 540#endif 541 542static int pwm_samsung_probe(struct platform_device *pdev) 543{ 544 struct device *dev = &pdev->dev; 545 struct samsung_pwm_chip *our_chip; 546 struct pwm_chip *chip; 547 unsigned int chan; 548 int ret; 549 550 chip = devm_pwmchip_alloc(&pdev->dev, SAMSUNG_PWM_NUM, sizeof(*our_chip)); 551 if (IS_ERR(chip)) 552 return PTR_ERR(chip); 553 our_chip = to_samsung_pwm_chip(chip); 554 555 chip->ops = &pwm_samsung_ops; 556 our_chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1; 557 558 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { 559 ret = pwm_samsung_parse_dt(chip); 560 if (ret) 561 return ret; 562 } else { 563 if (!pdev->dev.platform_data) 564 return dev_err_probe(&pdev->dev, -EINVAL, 565 "no platform data specified\n"); 566 567 memcpy(&our_chip->variant, pdev->dev.platform_data, 568 sizeof(our_chip->variant)); 569 } 570 571 our_chip->base = devm_platform_ioremap_resource(pdev, 0); 572 if (IS_ERR(our_chip->base)) 573 return PTR_ERR(our_chip->base); 574 575 our_chip->base_clk = devm_clk_get_enabled(&pdev->dev, "timers"); 576 if (IS_ERR(our_chip->base_clk)) 577 return dev_err_probe(dev, PTR_ERR(our_chip->base_clk), 578 "failed to get timer base clk\n"); 579 580 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) 581 if (our_chip->variant.output_mask & BIT(chan)) 582 pwm_samsung_set_invert(our_chip, chan, true); 583 584 /* Following clocks are optional. */ 585 our_chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0"); 586 our_chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1"); 587 588 platform_set_drvdata(pdev, chip); 589 590 ret = devm_pwmchip_add(&pdev->dev, chip); 591 if (ret < 0) 592 return dev_err_probe(dev, ret, "failed to register PWM chip\n"); 593 594 dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n", 595 clk_get_rate(our_chip->base_clk), 596 !IS_ERR(our_chip->tclk0) ? clk_get_rate(our_chip->tclk0) : 0, 597 !IS_ERR(our_chip->tclk1) ? clk_get_rate(our_chip->tclk1) : 0); 598 599 return 0; 600} 601 602static int pwm_samsung_resume(struct device *dev) 603{ 604 struct pwm_chip *chip = dev_get_drvdata(dev); 605 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 606 unsigned int i; 607 608 for (i = 0; i < SAMSUNG_PWM_NUM; i++) { 609 struct pwm_device *pwm = &chip->pwms[i]; 610 struct samsung_pwm_channel *chan = &our_chip->channel[i]; 611 612 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 613 continue; 614 615 if (our_chip->variant.output_mask & BIT(i)) 616 pwm_samsung_set_invert(our_chip, i, 617 our_chip->inverter_mask & BIT(i)); 618 619 if (chan->period_ns) { 620 __pwm_samsung_config(chip, pwm, chan->duty_ns, 621 chan->period_ns, true); 622 /* needed to make PWM disable work on Odroid-XU3 */ 623 pwm_samsung_manual_update(our_chip, pwm); 624 } 625 626 if (our_chip->disabled_mask & BIT(i)) 627 pwm_samsung_disable(chip, pwm); 628 else 629 pwm_samsung_enable(chip, pwm); 630 } 631 632 return 0; 633} 634 635static DEFINE_SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume); 636 637static struct platform_driver pwm_samsung_driver = { 638 .driver = { 639 .name = "samsung-pwm", 640 .pm = pm_ptr(&pwm_samsung_pm_ops), 641 .of_match_table = of_match_ptr(samsung_pwm_matches), 642 }, 643 .probe = pwm_samsung_probe, 644}; 645module_platform_driver(pwm_samsung_driver); 646 647MODULE_LICENSE("GPL"); 648MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>"); 649MODULE_ALIAS("platform:samsung-pwm"); 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