Searched refs:divider (Results 1 - 25 of 147) sorted by path

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/linux-master/drivers/clk/actions/
H A DMakefile7 clk-owl-y += owl-divider.o
/linux-master/drivers/clk/berlin/
H A Dberlin2-avpll.c255 u32 reg, div_av2, div_av3, divider = 1; local
271 divider = reg & VCO_SYNC1_MASK;
281 * HDMI divider start at VCO_CTRL11, bit 7; MSB is enable, lower 2 bit
282 * determine divider.
287 divider *= div_hdmi[reg & 0x3];
290 * AV1 divider start at VCO_CTRL11, bit 28; MSB is enable, lower 2 bit
291 * determine divider.
301 divider *= div_av1[reg & 0x3];
304 * AV2 divider start at VCO_CTRL12, bit 18; each 7 bits wide,
318 divider *
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H A Dberlin2-div.c20 * input pll and divider. The virtual structure as it is used in Marvell
35 * (C) programmable clock divider controlled by <Select[1:n]>
36 * (D) constant div-by-3 clock divider
37 * (E) programmable clock divider bypass controlled by <Switch>
181 u32 divsw, div3sw, divider = 1; local
193 divider = 3;
194 /* divider can be bypassed with DIV_SWITCH == 0 */
196 divider = 1;
197 /* clock divider determined by DIV_SELECT */
203 divider
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/linux-master/drivers/clk/meson/
H A Dvid-pll-div.c20 * This vid_pll divided is a fully programmable fractionnal divider to
29 unsigned int divider; member in struct:vid_pll_div
37 .divider = (_ft), \
84 if (!div || !div->divider) {
89 return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);
97 MODULE_DESCRIPTION("Amlogic video pll divider driver");
/linux-master/drivers/clk/mxs/
H A Dclk-div.c12 * struct clk_div - mxs integer divider clock
13 * @divider: the parent class
18 * The mxs divider clock is a subclass of basic clk_divider with an
22 struct clk_divider divider; member in struct:clk_div
30 struct clk_divider *divider = to_clk_divider(hw); local
32 return container_of(divider, struct clk_div, divider);
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate);
48 return div->ops->round_rate(&div->divider.hw, rate, prate);
57 ret = div->ops->set_rate(&div->divider
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/linux-master/drivers/clk/nxp/
H A Dclk-lpc32xx.c253 * divider register does not contain information about selected rate.
657 * and post-divider must be 4, this slightly simplifies calculation of
658 * USB divider, USB PLL N and M parameters.
663 /* USB divider clock */
674 /* Check if valid USB divider and USB PLL parameters exists */
946 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); local
949 regmap_read(clk_regmap, divider->reg, &val);
951 val >>= divider->shift;
952 val &= div_mask(divider->width);
954 return divider_recalc_rate(hw, parent_rate, val, divider
961 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); local
981 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); local
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/linux-master/drivers/clk/qcom/
H A Dclk-regmap-divider.c11 #include "clk-regmap-divider.h"
21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); local
22 struct clk_regmap *clkr = &divider->clkr;
25 regmap_read(clkr->regmap, divider->reg, &val);
26 val >>= divider->shift;
27 val &= BIT(divider->width) - 1;
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width,
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width,
45 struct clk_regmap_div *divider local
60 struct clk_regmap_div *divider = to_clk_regmap_div(hw); local
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/linux-master/drivers/clk/zynqmp/
H A DMakefile4 obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o
/linux-master/drivers/gpu/drm/radeon/
H A Drv6xx_dpm.c380 u32 index, u32 divider)
383 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);
387 u32 index, u32 divider)
389 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
394 u32 index, u32 divider)
397 LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK);
379 rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
386 rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
393 rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
/linux-master/arch/m68k/coldfire/
H A Dm53xx.c549 /* Check bounds of divider */
559 /* Apply the divider to the system clock */
585 int divider; local
589 divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
590 return (FREF/(2 << divider));
/linux-master/arch/mips/include/asm/sgi/
H A Dmc.h57 volatile u32 divider; /* Divider reg for RPSS */ member in struct:sgimc_regs
/linux-master/arch/mips/sgi-ip22/
H A Dip22-mc.c124 /* Step 4: Initialize the RPSS divider register to run as fast
138 sgimc->divider = 0x101;
/linux-master/arch/sh/boards/mach-ecovec24/
H A Dsetup.c514 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
519 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
/linux-master/arch/x86/kernel/
H A Dtsc_msr.c40 u32 divider; member in struct:muldiv
197 if (md->divider) {
199 freq = DIV_ROUND_CLOSEST(tscref, md->divider);
204 res = DIV_ROUND_CLOSEST(tscref * ratio, md->divider);
/linux-master/drivers/clk/
H A DMakefile6 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
14 obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
H A Dclk-axi-clkgen.c193 static void axi_clkgen_calc_clk_params(unsigned int divider, argument
199 if (divider == 1) {
205 params->high = divider / 2;
206 params->edge = divider % 2;
207 params->low = divider - params->high;
212 params->high = divider / 2;
213 params->edge = divider % 2;
224 (divider == 2 && frac_divider == 1))
H A Dclk-cdce706.c84 struct cdce706_hw_data divider[6]; member in struct:cdce706_dev_data
284 "%s, divider: %d, div: %u\n",
354 "%s, divider: %d, div: %lu\n",
367 "%s, divider: %d, div: %u\n",
567 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) {
573 cdce->divider[i].parent =
580 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK;
583 cdce->divider[i].parent, cdce->divider[i].div);
586 ret = cdce706_register_hw(cdce, cdce->divider,
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H A Dclk-cdce925.c349 /* Disable clock by setting divider to "0" */
366 unsigned long divider; local
373 divider = DIV_ROUND_CLOSEST(parent_rate, rate);
374 if (divider > 0x7F)
375 divider = 0x7F;
377 return (u16)divider;
427 u16 divider = cdce925_calc_divider(rate, l_parent_rate); local
429 if (l_parent_rate / divider != rate) {
431 divider = cdce925_calc_divider(rate, l_parent_rate);
435 if (divider)
462 unsigned long divider; local
480 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); local
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H A Dclk-divider.c7 * Adjustable divider clock implementation
20 * DOC: basic adjustable divider clock that cannot gate
29 static inline u32 clk_div_readl(struct clk_divider *divider) argument
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
32 return ioread32be(divider->reg);
34 return readl(divider->reg);
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val) argument
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
40 iowrite32be(val, divider->reg);
42 writel(val, divider
152 struct clk_divider *divider = to_clk_divider(hw); local
431 struct clk_divider *divider = to_clk_divider(hw); local
452 struct clk_divider *divider = to_clk_divider(hw); local
490 struct clk_divider *divider = to_clk_divider(hw); local
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H A Dclk-milbeaut.c379 struct m10v_clk_divider *divider = to_m10v_div(hw); local
382 val = readl(divider->reg) >> divider->shift;
383 val &= clk_div_mask(divider->width);
385 return divider_recalc_rate(hw, parent_rate, val, divider->table,
386 divider->flags, divider->width);
392 struct m10v_clk_divider *divider = to_m10v_div(hw); local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
398 val = readl(divider
413 struct m10v_clk_divider *divider = to_m10v_div(hw); local
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/linux-master/drivers/clk/baikal-t1/
H A Dccu-div.c78 unsigned long divider)
85 nd = ccu_div_lock_delay_ns(parent_rate, divider);
211 unsigned long divider; local
215 divider = ccu_div_get(div->mask, val);
217 return ccu_div_calc_freq(parent_rate, divider);
224 unsigned long divider; local
226 divider = parent_rate / rate;
227 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
235 unsigned long divider; local
237 divider
76 ccu_div_var_update_clkdiv(struct ccu_div *div, unsigned long parent_rate, unsigned long divider) argument
251 unsigned long flags, divider; local
285 unsigned long flags, divider; local
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H A Dccu-div.h26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
43 * @CCU_DIV_VAR: Clocks gate with variable divider.
44 * @CCU_DIV_GATE: Clocks gate with fixed divider.
45 * @CCU_DIV_BUF: Clock gate with no divider.
46 * @CCU_DIV_FIXED: Ungateable clock with fixed divider.
63 * @type: CCU divider type (variable, fixed with and without gate).
65 * @divider: Divider fixed value.
79 unsigned int divider; member in union:ccu_div_init_data::__anon8
105 unsigned int divider; member in union:ccu_div::__anon9
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H A Dclk-ccu-div.c76 .divider = _divider \
95 .divider = _divider \
106 unsigned int divider; member in union:ccu_div_info::__anon91
374 init.divider = info->divider;
379 init.divider = info->divider;
385 pr_err("Couldn't register divider '%s' hw\n",
439 pr_err("Couldn't register divider '%s' reset controller\n",
/linux-master/drivers/clk/bcm/
H A Dclk-bcm2835.c494 /* Number of integer bits in the divider */
496 /* Number of fractional bits in the divider */
804 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
805 struct bcm2835_cprman *cprman = divider->cprman;
806 const struct bcm2835_pll_divider_data *data = divider->data;
825 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
826 struct bcm2835_cprman *cprman = divider->cprman;
827 const struct bcm2835_pll_divider_data *data = divider->data;
841 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
842 struct bcm2835_cprman *cprman = divider
861 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
883 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
1376 struct bcm2835_pll_divider *divider; local
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H A Dclk-kona.c49 /* Convert a divider into the scaled divisor value it represents. */
56 * Build a scaled divider value as close as possible to the
73 /* The scaled minimum divisor representable by a divider */
83 /* The scaled maximum divisor representable by a divider */
97 * Convert a scaled divisor into its divider representation as
98 * stored in a divider register field.
101 divider(struct bcm_clk_div *div, u64 scaled_div) function
555 /* Read a divider value and return the scaled divisor it represents. */
569 /* Extract the full divider field from the register value */
577 * Convert a divider'
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