drivers/clk/clk-divider.c

7  * Adjustable divider clock implementation
20  * DOC: basic adjustable divider clock that cannot gate
29 static inline u32 clk_div_readl(struct clk_divider *divider)
31 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
32 		return ioread32be(divider->reg);
34 	return readl(divider->reg);
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val)
39 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
40 		iowrite32be(val, divider->reg);
42 		writel(val, divider->reg);
152 	struct clk_divider *divider = to_clk_divider(hw);
155 	val = clk_div_readl(divider) >> divider->shift;
156 	val &= clk_div_mask(divider->width);
158 	return divider_recalc_rate(hw, parent_rate, val, divider->table,
159 				   divider->flags, divider->width);
313 	 * The maximum divider we can use without overflowing
324 			 * parent rate, so return the divider immediately.
431 	struct clk_divider *divider = to_clk_divider(hw);
434 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
437 		val = clk_div_readl(divider) >> divider->shift;
438 		val &= clk_div_mask(divider->width);
440 		return divider_ro_round_rate(hw, rate, prate, divider->table,
441 					     divider->width, divider->flags,
445 	return divider_round_rate(hw, rate, prate, divider->table,
446 				  divider->width, divider->flags);
452 	struct clk_divider *divider = to_clk_divider(hw);
455 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
458 		val = clk_div_readl(divider) >> divider->shift;
459 		val &= clk_div_mask(divider->width);
461 		return divider_ro_determine_rate(hw, req, divider->table,
462 						 divider->width,
463 						 divider->flags, val);
466 	return divider_determine_rate(hw, req, divider->table, divider->width,
467 				      divider->flags);
490 	struct clk_divider *divider = to_clk_divider(hw);
495 	value = divider_get_val(rate, parent_rate, divider->table,
496 				divider->width, divider->flags);
500 	if (divider->lock)
501 		spin_lock_irqsave(divider->lock, flags);
503 		__acquire(divider->lock);
505 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
506 		val = clk_div_mask(divider->width) << (divider->shift + 16);
508 		val = clk_div_readl(divider);
509 		val &= ~(clk_div_mask(divider->width) << divider->shift);
511 	val |= (u32)value << divider->shift;
512 	clk_div_writel(divider, val);
514 	if (divider->lock)
515 		spin_unlock_irqrestore(divider->lock, flags);
517 		__release(divider->lock);
551 			pr_warn("divider value exceeds LOWORD field\n");
556 	/* allocate the divider */
597  * clk_register_divider_table - register a table based divider clock with
603  * @reg: register address to adjust divider
606  * @clk_divider_flags: divider-specific flags for this clock
607  * @table: array of divider/value pairs ending with a div set to 0
644  * clk_hw_unregister_divider - unregister a clk divider