1/* 2 * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer 3 * 4 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1, 5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve 6 * basis. Clients can directly request any frequency that the chip can 7 * deliver using the standard clk framework. In addition, the device can 8 * be configured and activated via the devicetree. 9 * 10 * Copyright (C) 2014, Topic Embedded Products 11 * Licenced under GPL 12 */ 13#include <linux/clk.h> 14#include <linux/clk-provider.h> 15#include <linux/delay.h> 16#include <linux/module.h> 17#include <linux/i2c.h> 18#include <linux/regmap.h> 19#include <linux/regulator/consumer.h> 20#include <linux/slab.h> 21#include <linux/gcd.h> 22 23/* Each chip has different number of PLLs and outputs, for example: 24 * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs. 25 * Model this as 2 PLL clocks which are parents to the outputs. 26 */ 27 28struct clk_cdce925_chip_info { 29 int num_plls; 30 int num_outputs; 31}; 32 33#define MAX_NUMBER_OF_PLLS 4 34#define MAX_NUMBER_OF_OUTPUTS 9 35 36#define CDCE925_REG_GLOBAL1 0x01 37#define CDCE925_REG_Y1SPIPDIVH 0x02 38#define CDCE925_REG_PDIVL 0x03 39#define CDCE925_REG_XCSEL 0x05 40/* PLL parameters start at 0x10, steps of 0x10 */ 41#define CDCE925_OFFSET_PLL 0x10 42/* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */ 43#define CDCE925_PLL_MUX_OUTPUTS 0x14 44#define CDCE925_PLL_MULDIV 0x18 45 46#define CDCE925_PLL_FREQUENCY_MIN 80000000ul 47#define CDCE925_PLL_FREQUENCY_MAX 230000000ul 48struct clk_cdce925_chip; 49 50struct clk_cdce925_output { 51 struct clk_hw hw; 52 struct clk_cdce925_chip *chip; 53 u8 index; 54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ 55}; 56#define to_clk_cdce925_output(_hw) \ 57 container_of(_hw, struct clk_cdce925_output, hw) 58 59struct clk_cdce925_pll { 60 struct clk_hw hw; 61 struct clk_cdce925_chip *chip; 62 u8 index; 63 u16 m; /* 1..511 */ 64 u16 n; /* 1..4095 */ 65}; 66#define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw) 67 68struct clk_cdce925_chip { 69 struct regmap *regmap; 70 struct i2c_client *i2c_client; 71 const struct clk_cdce925_chip_info *chip_info; 72 struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS]; 73 struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS]; 74}; 75 76/* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ 77 78static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, 79 u16 n, u16 m) 80{ 81 if ((!m || !n) || (m == n)) 82 return parent_rate; /* In bypass mode runs at same frequency */ 83 return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); 84} 85 86static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw, 87 unsigned long parent_rate) 88{ 89 /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */ 90 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 91 92 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); 93} 94 95static void cdce925_pll_find_rate(unsigned long rate, 96 unsigned long parent_rate, u16 *n, u16 *m) 97{ 98 unsigned long un; 99 unsigned long um; 100 unsigned long g; 101 102 if (rate <= parent_rate) { 103 /* Can always deliver parent_rate in bypass mode */ 104 *n = 0; 105 *m = 0; 106 } else { 107 /* In PLL mode, need to apply min/max range */ 108 if (rate < CDCE925_PLL_FREQUENCY_MIN) 109 rate = CDCE925_PLL_FREQUENCY_MIN; 110 else if (rate > CDCE925_PLL_FREQUENCY_MAX) 111 rate = CDCE925_PLL_FREQUENCY_MAX; 112 113 g = gcd(rate, parent_rate); 114 um = parent_rate / g; 115 un = rate / g; 116 /* When outside hw range, reduce to fit (rounding errors) */ 117 while ((un > 4095) || (um > 511)) { 118 un >>= 1; 119 um >>= 1; 120 } 121 if (un == 0) 122 un = 1; 123 if (um == 0) 124 um = 1; 125 126 *n = un; 127 *m = um; 128 } 129} 130 131static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate, 132 unsigned long *parent_rate) 133{ 134 u16 n, m; 135 136 cdce925_pll_find_rate(rate, *parent_rate, &n, &m); 137 return (long)cdce925_pll_calculate_rate(*parent_rate, n, m); 138} 139 140static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate, 141 unsigned long parent_rate) 142{ 143 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 144 145 if (!rate || (rate == parent_rate)) { 146 data->m = 0; /* Bypass mode */ 147 data->n = 0; 148 return 0; 149 } 150 151 if ((rate < CDCE925_PLL_FREQUENCY_MIN) || 152 (rate > CDCE925_PLL_FREQUENCY_MAX)) { 153 pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate); 154 return -EINVAL; 155 } 156 157 if (rate < parent_rate) { 158 pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__, 159 rate, parent_rate); 160 return -EINVAL; 161 } 162 163 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); 164 return 0; 165} 166 167 168/* calculate p = max(0, 4 - int(log2 (n/m))) */ 169static u8 cdce925_pll_calc_p(u16 n, u16 m) 170{ 171 u8 p; 172 u16 r = n / m; 173 174 if (r >= 16) 175 return 0; 176 p = 4; 177 while (r > 1) { 178 r >>= 1; 179 --p; 180 } 181 return p; 182} 183 184/* Returns VCO range bits for VCO1_0_RANGE */ 185static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m) 186{ 187 struct clk *parent = clk_get_parent(hw->clk); 188 unsigned long rate = clk_get_rate(parent); 189 190 rate = mult_frac(rate, (unsigned long)n, (unsigned long)m); 191 if (rate >= 175000000) 192 return 0x3; 193 if (rate >= 150000000) 194 return 0x02; 195 if (rate >= 125000000) 196 return 0x01; 197 return 0x00; 198} 199 200/* I2C clock, hence everything must happen in (un)prepare because this 201 * may sleep */ 202static int cdce925_pll_prepare(struct clk_hw *hw) 203{ 204 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 205 u16 n = data->n; 206 u16 m = data->m; 207 u16 r; 208 u8 q; 209 u8 p; 210 u16 nn; 211 u8 pll[4]; /* Bits are spread out over 4 byte registers */ 212 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 213 unsigned i; 214 215 if ((!m || !n) || (m == n)) { 216 /* Set PLL mux to bypass mode, leave the rest as is */ 217 regmap_update_bits(data->chip->regmap, 218 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 219 } else { 220 /* According to data sheet: */ 221 /* p = max(0, 4 - int(log2 (n/m))) */ 222 p = cdce925_pll_calc_p(n, m); 223 /* nn = n * 2^p */ 224 nn = n * BIT(p); 225 /* q = int(nn/m) */ 226 q = nn / m; 227 if ((q < 16) || (q > 63)) { 228 pr_debug("%s invalid q=%d\n", __func__, q); 229 return -EINVAL; 230 } 231 r = nn - (m*q); 232 if (r > 511) { 233 pr_debug("%s invalid r=%d\n", __func__, r); 234 return -EINVAL; 235 } 236 pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__, 237 n, m, p, q, r); 238 /* encode into register bits */ 239 pll[0] = n >> 4; 240 pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); 241 pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); 242 pll[3] = ((q & 0x07) << 5) | (p << 2) | 243 cdce925_pll_calc_range_bits(hw, n, m); 244 /* Write to registers */ 245 for (i = 0; i < ARRAY_SIZE(pll); ++i) 246 regmap_write(data->chip->regmap, 247 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); 248 /* Enable PLL */ 249 regmap_update_bits(data->chip->regmap, 250 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); 251 } 252 253 return 0; 254} 255 256static void cdce925_pll_unprepare(struct clk_hw *hw) 257{ 258 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 259 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 260 261 regmap_update_bits(data->chip->regmap, 262 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 263} 264 265static const struct clk_ops cdce925_pll_ops = { 266 .prepare = cdce925_pll_prepare, 267 .unprepare = cdce925_pll_unprepare, 268 .recalc_rate = cdce925_pll_recalc_rate, 269 .round_rate = cdce925_pll_round_rate, 270 .set_rate = cdce925_pll_set_rate, 271}; 272 273 274static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) 275{ 276 switch (data->index) { 277 case 0: 278 regmap_update_bits(data->chip->regmap, 279 CDCE925_REG_Y1SPIPDIVH, 280 0x03, (pdiv >> 8) & 0x03); 281 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); 282 break; 283 case 1: 284 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); 285 break; 286 case 2: 287 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); 288 break; 289 case 3: 290 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); 291 break; 292 case 4: 293 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); 294 break; 295 case 5: 296 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); 297 break; 298 case 6: 299 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); 300 break; 301 case 7: 302 regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv); 303 break; 304 case 8: 305 regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv); 306 break; 307 } 308} 309 310static void cdce925_clk_activate(struct clk_cdce925_output *data) 311{ 312 switch (data->index) { 313 case 0: 314 regmap_update_bits(data->chip->regmap, 315 CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c); 316 break; 317 case 1: 318 case 2: 319 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); 320 break; 321 case 3: 322 case 4: 323 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); 324 break; 325 case 5: 326 case 6: 327 regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03); 328 break; 329 case 7: 330 case 8: 331 regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03); 332 break; 333 } 334} 335 336static int cdce925_clk_prepare(struct clk_hw *hw) 337{ 338 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 339 340 cdce925_clk_set_pdiv(data, data->pdiv); 341 cdce925_clk_activate(data); 342 return 0; 343} 344 345static void cdce925_clk_unprepare(struct clk_hw *hw) 346{ 347 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 348 349 /* Disable clock by setting divider to "0" */ 350 cdce925_clk_set_pdiv(data, 0); 351} 352 353static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw, 354 unsigned long parent_rate) 355{ 356 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 357 358 if (data->pdiv) 359 return parent_rate / data->pdiv; 360 return 0; 361} 362 363static u16 cdce925_calc_divider(unsigned long rate, 364 unsigned long parent_rate) 365{ 366 unsigned long divider; 367 368 if (!rate) 369 return 0; 370 if (rate >= parent_rate) 371 return 1; 372 373 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 374 if (divider > 0x7F) 375 divider = 0x7F; 376 377 return (u16)divider; 378} 379 380static unsigned long cdce925_clk_best_parent_rate( 381 struct clk_hw *hw, unsigned long rate) 382{ 383 struct clk *pll = clk_get_parent(hw->clk); 384 struct clk *root = clk_get_parent(pll); 385 unsigned long root_rate = clk_get_rate(root); 386 unsigned long best_rate_error = rate; 387 u16 pdiv_min; 388 u16 pdiv_max; 389 u16 pdiv_best; 390 u16 pdiv_now; 391 392 if (root_rate % rate == 0) 393 return root_rate; /* Don't need the PLL, use bypass */ 394 395 pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate)); 396 pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate); 397 398 if (pdiv_min > pdiv_max) 399 return 0; /* No can do? */ 400 401 pdiv_best = pdiv_min; 402 for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) { 403 unsigned long target_rate = rate * pdiv_now; 404 long pll_rate = clk_round_rate(pll, target_rate); 405 unsigned long actual_rate; 406 unsigned long rate_error; 407 408 if (pll_rate <= 0) 409 continue; 410 actual_rate = pll_rate / pdiv_now; 411 rate_error = abs((long)actual_rate - (long)rate); 412 if (rate_error < best_rate_error) { 413 pdiv_best = pdiv_now; 414 best_rate_error = rate_error; 415 } 416 /* TODO: Consider PLL frequency based on smaller n/m values 417 * and pick the better one if the error is equal */ 418 } 419 420 return rate * pdiv_best; 421} 422 423static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate, 424 unsigned long *parent_rate) 425{ 426 unsigned long l_parent_rate = *parent_rate; 427 u16 divider = cdce925_calc_divider(rate, l_parent_rate); 428 429 if (l_parent_rate / divider != rate) { 430 l_parent_rate = cdce925_clk_best_parent_rate(hw, rate); 431 divider = cdce925_calc_divider(rate, l_parent_rate); 432 *parent_rate = l_parent_rate; 433 } 434 435 if (divider) 436 return (long)(l_parent_rate / divider); 437 return 0; 438} 439 440static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate, 441 unsigned long parent_rate) 442{ 443 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 444 445 data->pdiv = cdce925_calc_divider(rate, parent_rate); 446 447 return 0; 448} 449 450static const struct clk_ops cdce925_clk_ops = { 451 .prepare = cdce925_clk_prepare, 452 .unprepare = cdce925_clk_unprepare, 453 .recalc_rate = cdce925_clk_recalc_rate, 454 .round_rate = cdce925_clk_round_rate, 455 .set_rate = cdce925_clk_set_rate, 456}; 457 458 459static u16 cdce925_y1_calc_divider(unsigned long rate, 460 unsigned long parent_rate) 461{ 462 unsigned long divider; 463 464 if (!rate) 465 return 0; 466 if (rate >= parent_rate) 467 return 1; 468 469 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 470 if (divider > 0x3FF) /* Y1 has 10-bit divider */ 471 divider = 0x3FF; 472 473 return (u16)divider; 474} 475 476static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate, 477 unsigned long *parent_rate) 478{ 479 unsigned long l_parent_rate = *parent_rate; 480 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); 481 482 if (divider) 483 return (long)(l_parent_rate / divider); 484 return 0; 485} 486 487static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate, 488 unsigned long parent_rate) 489{ 490 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 491 492 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); 493 494 return 0; 495} 496 497static const struct clk_ops cdce925_clk_y1_ops = { 498 .prepare = cdce925_clk_prepare, 499 .unprepare = cdce925_clk_unprepare, 500 .recalc_rate = cdce925_clk_recalc_rate, 501 .round_rate = cdce925_clk_y1_round_rate, 502 .set_rate = cdce925_clk_y1_set_rate, 503}; 504 505#define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00 506#define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80 507 508static int cdce925_regmap_i2c_write( 509 void *context, const void *data, size_t count) 510{ 511 struct device *dev = context; 512 struct i2c_client *i2c = to_i2c_client(dev); 513 int ret; 514 u8 reg_data[2]; 515 516 if (count != 2) 517 return -ENOTSUPP; 518 519 /* First byte is command code */ 520 reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0]; 521 reg_data[1] = ((u8 *)data)[1]; 522 523 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, 524 reg_data[0], reg_data[1]); 525 526 ret = i2c_master_send(i2c, reg_data, count); 527 if (likely(ret == count)) 528 return 0; 529 else if (ret < 0) 530 return ret; 531 else 532 return -EIO; 533} 534 535static int cdce925_regmap_i2c_read(void *context, 536 const void *reg, size_t reg_size, void *val, size_t val_size) 537{ 538 struct device *dev = context; 539 struct i2c_client *i2c = to_i2c_client(dev); 540 struct i2c_msg xfer[2]; 541 int ret; 542 u8 reg_data[2]; 543 544 if (reg_size != 1) 545 return -ENOTSUPP; 546 547 xfer[0].addr = i2c->addr; 548 xfer[0].flags = 0; 549 xfer[0].buf = reg_data; 550 if (val_size == 1) { 551 reg_data[0] = 552 CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0]; 553 xfer[0].len = 1; 554 } else { 555 reg_data[0] = 556 CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0]; 557 reg_data[1] = val_size; 558 xfer[0].len = 2; 559 } 560 561 xfer[1].addr = i2c->addr; 562 xfer[1].flags = I2C_M_RD; 563 xfer[1].len = val_size; 564 xfer[1].buf = val; 565 566 ret = i2c_transfer(i2c->adapter, xfer, 2); 567 if (likely(ret == 2)) { 568 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, 569 reg_size, val_size, reg_data[0], *((u8 *)val)); 570 return 0; 571 } else if (ret < 0) 572 return ret; 573 else 574 return -EIO; 575} 576 577static struct clk_hw * 578of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data) 579{ 580 struct clk_cdce925_chip *data = _data; 581 unsigned int idx = clkspec->args[0]; 582 583 if (idx >= ARRAY_SIZE(data->clk)) { 584 pr_err("%s: invalid index %u\n", __func__, idx); 585 return ERR_PTR(-EINVAL); 586 } 587 588 return &data->clk[idx].hw; 589} 590 591static int cdce925_regulator_enable(struct device *dev, const char *name) 592{ 593 int err; 594 595 err = devm_regulator_get_enable(dev, name); 596 if (err) 597 dev_err_probe(dev, err, "Failed to enable %s:\n", name); 598 599 return err; 600} 601 602/* The CDCE925 uses a funky way to read/write registers. Bulk mode is 603 * just weird, so just use the single byte mode exclusively. */ 604static struct regmap_bus regmap_cdce925_bus = { 605 .write = cdce925_regmap_i2c_write, 606 .read = cdce925_regmap_i2c_read, 607}; 608 609static int cdce925_probe(struct i2c_client *client) 610{ 611 struct clk_cdce925_chip *data; 612 struct device_node *node = client->dev.of_node; 613 const char *parent_name; 614 const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,}; 615 struct clk_init_data init; 616 u32 value; 617 int i; 618 int err; 619 struct device_node *np_output; 620 char child_name[6]; 621 struct regmap_config config = { 622 .name = "configuration0", 623 .reg_bits = 8, 624 .val_bits = 8, 625 .cache_type = REGCACHE_MAPLE, 626 }; 627 628 dev_dbg(&client->dev, "%s\n", __func__); 629 630 err = cdce925_regulator_enable(&client->dev, "vdd"); 631 if (err) 632 return err; 633 634 err = cdce925_regulator_enable(&client->dev, "vddout"); 635 if (err) 636 return err; 637 638 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 639 if (!data) 640 return -ENOMEM; 641 642 data->i2c_client = client; 643 data->chip_info = i2c_get_match_data(client); 644 config.max_register = CDCE925_OFFSET_PLL + 645 data->chip_info->num_plls * 0x10 - 1; 646 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, 647 &client->dev, &config); 648 if (IS_ERR(data->regmap)) { 649 dev_err(&client->dev, "failed to allocate register map\n"); 650 return PTR_ERR(data->regmap); 651 } 652 i2c_set_clientdata(client, data); 653 654 parent_name = of_clk_get_parent_name(node, 0); 655 if (!parent_name) { 656 dev_err(&client->dev, "missing parent clock\n"); 657 return -ENODEV; 658 } 659 dev_dbg(&client->dev, "parent is: %s\n", parent_name); 660 661 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) 662 regmap_write(data->regmap, 663 CDCE925_REG_XCSEL, (value << 3) & 0xF8); 664 /* PWDN bit */ 665 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); 666 667 /* Set input source for Y1 to be the XTAL */ 668 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); 669 670 init.ops = &cdce925_pll_ops; 671 init.flags = 0; 672 init.parent_names = &parent_name; 673 init.num_parents = 1; 674 675 /* Register PLL clocks */ 676 for (i = 0; i < data->chip_info->num_plls; ++i) { 677 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d", 678 client->dev.of_node, i); 679 if (!pll_clk_name[i]) { 680 err = -ENOMEM; 681 goto error; 682 } 683 init.name = pll_clk_name[i]; 684 data->pll[i].chip = data; 685 data->pll[i].hw.init = &init; 686 data->pll[i].index = i; 687 err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); 688 if (err) { 689 dev_err(&client->dev, "Failed register PLL %d\n", i); 690 goto error; 691 } 692 sprintf(child_name, "PLL%d", i+1); 693 np_output = of_get_child_by_name(node, child_name); 694 if (!np_output) 695 continue; 696 if (!of_property_read_u32(np_output, 697 "clock-frequency", &value)) { 698 err = clk_set_rate(data->pll[i].hw.clk, value); 699 if (err) 700 dev_err(&client->dev, 701 "unable to set PLL frequency %ud\n", 702 value); 703 } 704 if (!of_property_read_u32(np_output, 705 "spread-spectrum", &value)) { 706 u8 flag = of_property_read_bool(np_output, 707 "spread-spectrum-center") ? 0x80 : 0x00; 708 regmap_update_bits(data->regmap, 709 0x16 + (i*CDCE925_OFFSET_PLL), 710 0x80, flag); 711 regmap_update_bits(data->regmap, 712 0x12 + (i*CDCE925_OFFSET_PLL), 713 0x07, value & 0x07); 714 } 715 of_node_put(np_output); 716 } 717 718 /* Register output clock Y1 */ 719 init.ops = &cdce925_clk_y1_ops; 720 init.flags = 0; 721 init.num_parents = 1; 722 init.parent_names = &parent_name; /* Mux Y1 to input */ 723 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node); 724 if (!init.name) { 725 err = -ENOMEM; 726 goto error; 727 } 728 data->clk[0].chip = data; 729 data->clk[0].hw.init = &init; 730 data->clk[0].index = 0; 731 data->clk[0].pdiv = 1; 732 err = devm_clk_hw_register(&client->dev, &data->clk[0].hw); 733 kfree(init.name); /* clock framework made a copy of the name */ 734 if (err) { 735 dev_err(&client->dev, "clock registration Y1 failed\n"); 736 goto error; 737 } 738 739 /* Register output clocks Y2 .. Y5*/ 740 init.ops = &cdce925_clk_ops; 741 init.flags = CLK_SET_RATE_PARENT; 742 init.num_parents = 1; 743 for (i = 1; i < data->chip_info->num_outputs; ++i) { 744 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d", 745 client->dev.of_node, i+1); 746 if (!init.name) { 747 err = -ENOMEM; 748 goto error; 749 } 750 data->clk[i].chip = data; 751 data->clk[i].hw.init = &init; 752 data->clk[i].index = i; 753 data->clk[i].pdiv = 1; 754 switch (i) { 755 case 1: 756 case 2: 757 /* Mux Y2/3 to PLL1 */ 758 init.parent_names = &pll_clk_name[0]; 759 break; 760 case 3: 761 case 4: 762 /* Mux Y4/5 to PLL2 */ 763 init.parent_names = &pll_clk_name[1]; 764 break; 765 case 5: 766 case 6: 767 /* Mux Y6/7 to PLL3 */ 768 init.parent_names = &pll_clk_name[2]; 769 break; 770 case 7: 771 case 8: 772 /* Mux Y8/9 to PLL4 */ 773 init.parent_names = &pll_clk_name[3]; 774 break; 775 } 776 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); 777 kfree(init.name); /* clock framework made a copy of the name */ 778 if (err) { 779 dev_err(&client->dev, "clock registration failed\n"); 780 goto error; 781 } 782 } 783 784 /* Register the output clocks */ 785 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get, 786 data); 787 if (err) 788 dev_err(&client->dev, "unable to add OF clock provider\n"); 789 790 err = 0; 791 792error: 793 for (i = 0; i < data->chip_info->num_plls; ++i) 794 /* clock framework made a copy of the name */ 795 kfree(pll_clk_name[i]); 796 797 return err; 798} 799 800static const struct clk_cdce925_chip_info clk_cdce913_info = { 801 .num_plls = 1, 802 .num_outputs = 3, 803}; 804 805static const struct clk_cdce925_chip_info clk_cdce925_info = { 806 .num_plls = 2, 807 .num_outputs = 5, 808}; 809 810static const struct clk_cdce925_chip_info clk_cdce937_info = { 811 .num_plls = 3, 812 .num_outputs = 7, 813}; 814 815static const struct clk_cdce925_chip_info clk_cdce949_info = { 816 .num_plls = 4, 817 .num_outputs = 9, 818}; 819 820static const struct i2c_device_id cdce925_id[] = { 821 { "cdce913", (kernel_ulong_t)&clk_cdce913_info }, 822 { "cdce925", (kernel_ulong_t)&clk_cdce925_info }, 823 { "cdce937", (kernel_ulong_t)&clk_cdce937_info }, 824 { "cdce949", (kernel_ulong_t)&clk_cdce949_info }, 825 { } 826}; 827MODULE_DEVICE_TABLE(i2c, cdce925_id); 828 829static const struct of_device_id clk_cdce925_of_match[] = { 830 { .compatible = "ti,cdce913", .data = &clk_cdce913_info }, 831 { .compatible = "ti,cdce925", .data = &clk_cdce925_info }, 832 { .compatible = "ti,cdce937", .data = &clk_cdce937_info }, 833 { .compatible = "ti,cdce949", .data = &clk_cdce949_info }, 834 { } 835}; 836MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); 837 838static struct i2c_driver cdce925_driver = { 839 .driver = { 840 .name = "cdce925", 841 .of_match_table = clk_cdce925_of_match, 842 }, 843 .probe = cdce925_probe, 844 .id_table = cdce925_id, 845}; 846module_i2c_driver(cdce925_driver); 847 848MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 849MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver"); 850MODULE_LICENSE("GPL"); 851