Lines Matching refs:divider
78 unsigned long divider)
85 nd = ccu_div_lock_delay_ns(parent_rate, divider);
211 unsigned long divider;
215 divider = ccu_div_get(div->mask, val);
217 return ccu_div_calc_freq(parent_rate, divider);
224 unsigned long divider;
226 divider = parent_rate / rate;
227 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
235 unsigned long divider;
237 divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask);
239 return ccu_div_calc_freq(*parent_rate, divider);
243 * This method is used for the clock divider blocks, which support the
251 unsigned long flags, divider;
255 divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
256 if (divider == 1 && div->features & CCU_DIV_SKIP_ONE) {
257 divider = 0;
259 if (divider == 1 || divider == 2)
260 divider = 0;
261 else if (divider == 3)
262 divider = 4;
265 val = ccu_div_prep(div->mask, divider);
269 ret = ccu_div_var_update_clkdiv(div, parent_rate, divider);
278 * This method is used for the clock divider blocks, which don't support
285 unsigned long flags, divider;
288 divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
289 val = ccu_div_prep(div->mask, divider);
292 * Also disable the clock divider block if it was enabled by default
308 return ccu_div_calc_freq(parent_rate, div->divider);
316 return ccu_div_calc_freq(*parent_rate, div->divider);
428 *val = div->divider;
611 div->divider = div_init->divider;
616 div->divider = div_init->divider;