Lines Matching refs:divider
379 struct m10v_clk_divider *divider = to_m10v_div(hw);
382 val = readl(divider->reg) >> divider->shift;
383 val &= clk_div_mask(divider->width);
385 return divider_recalc_rate(hw, parent_rate, val, divider->table,
386 divider->flags, divider->width);
392 struct m10v_clk_divider *divider = to_m10v_div(hw);
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
398 val = readl(divider->reg) >> divider->shift;
399 val &= clk_div_mask(divider->width);
401 return divider_ro_round_rate(hw, rate, prate, divider->table,
402 divider->width, divider->flags,
406 return divider_round_rate(hw, rate, prate, divider->table,
407 divider->width, divider->flags);
413 struct m10v_clk_divider *divider = to_m10v_div(hw);
417 u32 write_en = BIT(divider->width - 1);
419 value = divider_get_val(rate, parent_rate, divider->table,
420 divider->width, divider->flags);
424 if (divider->lock)
425 spin_lock_irqsave(divider->lock, flags);
427 __acquire(divider->lock);
429 val = readl(divider->reg);
430 val &= ~(clk_div_mask(divider->width) << divider->shift);
432 val |= ((u32)value | write_en) << divider->shift;
433 writel(val, divider->reg);
435 if (divider->write_valid_reg) {
436 writel(M10V_DCHREQ, divider->write_valid_reg);
437 if (readl_poll_timeout(divider->write_valid_reg, val,
443 if (divider->lock)
444 spin_unlock_irqrestore(divider->lock, flags);
446 __release(divider->lock);