| /u-boot/drivers/ddr/fsl/ |
| H A D | mpc85xx_ddr_gen2.c | 68 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
|
| H A D | arm_ddr_gen3.c | 94 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
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| H A D | mpc85xx_ddr_gen3.c | 127 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
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| H A D | fsl_ddr_gen4.c | 170 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
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| H A D | ctrl_regs.c | 441 ddr->timing_cfg_0 = (0
451 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
|
| H A D | interactive.c | 633 CFG_REGS(timing_cfg_0),
724 CFG_REGS(timing_cfg_0),
|
| /u-boot/board/socrates/ |
| H A D | sdram.c | 39 ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
|
| /u-boot/board/freescale/ls1043ardb/ |
| H A D | ddr.h | 60 .timing_cfg_0 = 0x91550018,
|
| /u-boot/board/gdsys/mpc8308/ |
| H A D | sdram.c | 55 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
|
| /u-boot/board/kontron/sl28/ |
| H A D | ddr.c | 27 .timing_cfg_0 = 0x9011010c,
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| /u-boot/board/freescale/ls1021atsn/ |
| H A D | ls1021atsn.c | 39 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
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| /u-boot/board/freescale/ls1021aiot/ |
| H A D | ls1021aiot.c | 63 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
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| /u-boot/drivers/ram/ |
| H A D | mpc83xx_sdram.c | 325 u32 timing_cfg_0; local
583 timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT |
592 out_be32(&im->ddr.timing_cfg_0, timing_cfg_0);
|
| /u-boot/board/keymile/km83xx/ |
| H A D | km83xx.c | 218 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
|
| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | 222 .timing_cfg_0 = CFG_SYS_DDR_TIMING_0,
|
| /u-boot/board/freescale/mpc837xerdb/ |
| H A D | mpc837xerdb.c | 116 im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
|
| /u-boot/include/ |
| H A D | fsl_immap.h | 37 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ member in struct:ccsr_ddr
|
| H A D | fsl_ddr_sdram.h | 249 unsigned int timing_cfg_0; member in struct:fsl_ddr_cfg_regs_s
|
| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| H A D | spd_sdram.c | 474 ddr->timing_cfg_0 = (0
480 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
|
| /u-boot/board/cssi/cmpcpro/ |
| H A D | cmpcpro.c | 307 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
|
| /u-boot/board/freescale/ls1021atwr/ |
| H A D | ls1021atwr.c | 154 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
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| /u-boot/arch/powerpc/include/asm/ |
| H A D | immap_83xx.h | 288 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ member in struct:ddr83xx
|