Searched refs:smc_state_table (Results 1 - 25 of 25) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.h42 struct SMU73_Discrete_DpmTable smc_state_table; member in struct:fiji_smumgr
H A Dci_smumgr.h68 struct SMU7_Discrete_DpmTable smc_state_table; member in struct:ci_smumgr
H A Diceland_smumgr.h62 struct SMU71_Discrete_DpmTable smc_state_table; member in struct:iceland_smumgr
H A Dtonga_smumgr.h66 struct SMU72_Discrete_DpmTable smc_state_table; member in struct:tonga_smumgr
H A Dvegam_smumgr.h66 SMU75_Discrete_DpmTable smc_state_table; member in struct:vegam_smumgr
H A Dpolaris10_smumgr.h57 SMU74_Discrete_DpmTable smc_state_table; member in struct:polaris10_smumgr
H A Dfiji_smumgr.c490 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
847 smu_data->smc_state_table.LinkLevelCount =
1015 smu_data->smc_state_table.GraphicsLevel;
1041 smu_data->smc_state_table.GraphicsDpmLevelCount =
1231 smu_data->smc_state_table.MemoryLevel;
1256 smu_data->smc_state_table.MemoryDpmLevelCount =
1643 smu_data->smc_state_table.GraphicsBootLevel = level;
1652 smu_data->smc_state_table.MemoryBootLevel = level;
1697 smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
1701 smu_data->smc_state_table
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H A Dtonga_smumgr.c530 smu_data->smc_state_table.LinkLevelCount =
700 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
713 &(smu_data->smc_state_table.GraphicsLevel[i]));
719 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
723 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
730 smu_data->smc_state_table.GraphicsDpmLevelCount =
741 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
771 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
774 smu_data->smc_state_table
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H A Diceland_smumgr.c787 smu_data->smc_state_table.LinkLevelCount =
970 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
983 &(smu_data->smc_state_table.GraphicsLevel[i]));
989 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
993 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
1000 smu_data->smc_state_table.GraphicsDpmLevelCount =
1027 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
1031 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
1034 smu_data->smc_state_table
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H A Dvegam_smumgr.c337 smu_data->smc_state_table.UvdBootLevel = 0;
339 smu_data->smc_state_table.UvdBootLevel =
348 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
358 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
372 smu_data->smc_state_table.VceBootLevel =
375 smu_data->smc_state_table.VceBootLevel = 0;
384 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
391 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
590 smu_data->smc_state_table.LinkLevelCount =
723 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
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H A Dpolaris10_smumgr.c432 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
478 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
836 smu_data->smc_state_table.LinkLevelCount =
894 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1029 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1051 smu_data->smc_state_table.GraphicsLevel;
1065 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1071 &(smu_data->smc_state_table.GraphicsLevel[i]));
1081 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1097 smu_data->smc_state_table
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H A Dci_smumgr.c483 smu_data->smc_state_table.GraphicsLevel;
493 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
495 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark =
499 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
501 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
720 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
1015 smu_data->smc_state_table.LinkLevelCount =
1311 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
1320 &(smu_data->smc_state_table.MemoryLevel[i]));
1325 smu_data->smc_state_table
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_hwmgr.c954 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1472 data->smc_state_table.pp_table.UlvOffsetVid =
1475 data->smc_state_table.pp_table.UlvSmnclkDid =
1477 data->smc_state_table.pp_table.UlvMp1clkDid =
1479 data->smc_state_table.pp_table.UlvGfxclkBypass =
1481 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1483 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1512 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1559 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1721 PPTable_t *pp_table = &(data->smc_state_table
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H A Dvega10_thermal.c510 PPTable_t *table = &(data->smc_state_table.pp_table);
555 (uint8_t *)(&(data->smc_state_table.pp_table)),
566 PPTable_t *table = &(data->smc_state_table.pp_table);
580 (uint8_t *)(&(data->smc_state_table.pp_table)),
H A Dvega12_thermal.c256 PPTable_t *table = &(data->smc_state_table.pp_table);
H A Dvega20_thermal.c327 PPTable_t *table = &(data->smc_state_table.pp_table);
H A Dvega10_hwmgr.h381 struct vega10_smc_state_table smc_state_table; member in struct:vega10_hwmgr
H A Dvega12_hwmgr.h392 struct vega12_smc_state_table smc_state_table; member in struct:vega12_hwmgr
H A Dvega20_hwmgr.c784 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
835 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1042 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1243 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1344 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
2941 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2964 &(data->smc_state_table.overdrive_table);
3362 &(data->smc_state_table.overdrive_table);
3363 PPTable_t *pptable = &(data->smc_state_table.pp_table);
3645 Watermarks_t *wm_table = &(data->smc_state_table
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H A Dvega20_hwmgr.h520 struct vega20_smc_state_table smc_state_table; member in struct:vega20_hwmgr
H A Dvega12_hwmgr.c490 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
815 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2001 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2553 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2770 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
H A Dvega10_powertune.c1242 PPTable_t *table = &(data->smc_state_table.pp_table);
H A Dsmu7_hwmgr.c5330 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
/linux-master/drivers/gpu/drm/radeon/
H A Dci_dpm.c405 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
1275 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
2552 pi->smc_state_table.GraphicsBootLevel = level;
2560 pi->smc_state_table.MemoryBootLevel = level;
2599 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
3240 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3249 &pi->smc_state_table.GraphicsLevel[i]);
3253 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3255 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3258 pi->smc_state_table
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H A Dci_dpm.h222 SMU7_Discrete_DpmTable smc_state_table; member in struct:ci_power_info

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