powerplay/smumgr/tonga_smumgr.c

530 	smu_data->smc_state_table.LinkLevelCount =
700 	SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
713 					&(smu_data->smc_state_table.GraphicsLevel[i]));
719 			smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
723 	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
727 		smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
730 	smu_data->smc_state_table.GraphicsDpmLevelCount =
741 			smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
771 			smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
774 		smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
777 		smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
1102 				smu_data->smc_state_table.MemoryLevel;
1114 				&(smu_data->smc_state_table.MemoryLevel[i]));
1120 	smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1127 	smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1128 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1130 	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
1133 	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1192 			smu_data->smc_state_table.GraphicsLevel[0].MinVoltage;
1242 			    smu_data->smc_state_table.MemoryLevel[0].MinVoltage;
1535 	(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
1538 		smu_data->smc_state_table.GraphicsBootLevel = 0;
1547 		(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
1550 		smu_data->smc_state_table.MemoryBootLevel = 0;
1616 	smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
1621 		smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1641 		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1669 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1671 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1673 	clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
1674 			GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
1689 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1691 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1693 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1695 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1706 		smu_data->smc_state_table.ClockStretcherDataTable.
1709 		smu_data->smc_state_table.ClockStretcherDataTable.
1715 		for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
1718 					smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
1729 			smu_data->smc_state_table.ClockStretcherDataTable.
1732 		CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
1831 	SMU72_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
2226 	SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);
2234 	memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
2683 	smu_data->smc_state_table.UvdBootLevel = 0;
2685 		smu_data->smc_state_table.UvdBootLevel =
2694 	mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2705 				(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
2719 	smu_data->smc_state_table.VceBootLevel =
2729 	mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2737 				(uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
3155 			smu_data->smc_state_table.GraphicsLevel;
3162 			smu_data->smc_state_table.MemoryLevel;
3174 		for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
3209 		for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {