Lines Matching refs:smc_state_table
337 smu_data->smc_state_table.UvdBootLevel = 0;
339 smu_data->smc_state_table.UvdBootLevel =
348 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
358 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
372 smu_data->smc_state_table.VceBootLevel =
375 smu_data->smc_state_table.VceBootLevel = 0;
384 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
391 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
590 smu_data->smc_state_table.LinkLevelCount =
723 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
879 smu_data->smc_state_table.GraphicsLevel;
886 vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
892 &(smu_data->smc_state_table.GraphicsLevel[i]));
906 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
908 smu_data->smc_state_table.GraphicsDpmLevelCount =
1046 smu_data->smc_state_table.MemoryLevel;
1066 smu_data->smc_state_table.MemoryDpmLevelCount =
1414 smu_data->smc_state_table.GraphicsBootLevel = level;
1423 smu_data->smc_state_table.MemoryBootLevel = level;
1443 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1510 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1523 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1526 smu_data->smc_state_table.LdoRefSel =
1566 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1925 struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);