1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef _VEGA10_HWMGR_H_ 25#define _VEGA10_HWMGR_H_ 26 27#include "hwmgr.h" 28#include "smu9_driver_if.h" 29#include "ppatomctrl.h" 30#include "ppatomfwctrl.h" 31#include "vega10_ppsmc.h" 32#include "vega10_powertune.h" 33 34#define VEGA10_MAX_HARDWARE_POWERLEVELS 2 35 36#define WaterMarksExist 1 37#define WaterMarksLoaded 2 38 39enum { 40 GNLD_DPM_PREFETCHER = 0, 41 GNLD_DPM_GFXCLK, 42 GNLD_DPM_UCLK, 43 GNLD_DPM_SOCCLK, 44 GNLD_DPM_UVD, 45 GNLD_DPM_VCE, 46 GNLD_ULV, 47 GNLD_DPM_MP0CLK, 48 GNLD_DPM_LINK, 49 GNLD_DPM_DCEFCLK, 50 GNLD_AVFS, 51 GNLD_DS_GFXCLK, 52 GNLD_DS_SOCCLK, 53 GNLD_DS_LCLK, 54 GNLD_PPT, 55 GNLD_TDC, 56 GNLD_THERMAL, 57 GNLD_GFX_PER_CU_CG, 58 GNLD_RM, 59 GNLD_DS_DCEFCLK, 60 GNLD_ACDC, 61 GNLD_VR0HOT, 62 GNLD_VR1HOT, 63 GNLD_FW_CTF, 64 GNLD_LED_DISPLAY, 65 GNLD_FAN_CONTROL, 66 GNLD_FEATURE_FAST_PPT_BIT, 67 GNLD_DIDT, 68 GNLD_ACG, 69 GNLD_PCC_LIMIT, 70 GNLD_FEATURES_MAX 71}; 72 73#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1) 74 75#define SMC_DPM_FEATURES 0x30F 76 77struct smu_features { 78 bool supported; 79 bool enabled; 80 uint32_t smu_feature_id; 81 uint32_t smu_feature_bitmap; 82}; 83 84struct vega10_performance_level { 85 uint32_t soc_clock; 86 uint32_t gfx_clock; 87 uint32_t mem_clock; 88}; 89 90struct vega10_bacos { 91 uint32_t baco_flags; 92 /* struct vega10_performance_level performance_level; */ 93}; 94 95struct vega10_uvd_clocks { 96 uint32_t vclk; 97 uint32_t dclk; 98}; 99 100struct vega10_vce_clocks { 101 uint32_t evclk; 102 uint32_t ecclk; 103}; 104 105struct vega10_power_state { 106 uint32_t magic; 107 struct vega10_uvd_clocks uvd_clks; 108 struct vega10_vce_clocks vce_clks; 109 uint16_t performance_level_count; 110 bool dc_compatible; 111 uint32_t sclk_threshold; 112 struct vega10_performance_level performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS]; 113}; 114 115struct vega10_dpm_level { 116 bool enabled; 117 uint32_t value; 118 uint32_t param1; 119}; 120 121#define VEGA10_MAX_DEEPSLEEP_DIVIDER_ID 5 122#define MAX_REGULAR_DPM_NUMBER 8 123#define MAX_PCIE_CONF 2 124#define VEGA10_MINIMUM_ENGINE_CLOCK 2500 125 126struct vega10_dpm_state { 127 uint32_t soft_min_level; 128 uint32_t soft_max_level; 129 uint32_t hard_min_level; 130 uint32_t hard_max_level; 131}; 132 133struct vega10_single_dpm_table { 134 uint32_t count; 135 struct vega10_dpm_state dpm_state; 136 struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 137}; 138 139struct vega10_pcie_table { 140 uint16_t count; 141 uint8_t pcie_gen[MAX_PCIE_CONF]; 142 uint8_t pcie_lane[MAX_PCIE_CONF]; 143 uint32_t lclk[MAX_PCIE_CONF]; 144}; 145 146struct vega10_dpm_table { 147 struct vega10_single_dpm_table soc_table; 148 struct vega10_single_dpm_table gfx_table; 149 struct vega10_single_dpm_table mem_table; 150 struct vega10_single_dpm_table eclk_table; 151 struct vega10_single_dpm_table vclk_table; 152 struct vega10_single_dpm_table dclk_table; 153 struct vega10_single_dpm_table dcef_table; 154 struct vega10_single_dpm_table pixel_table; 155 struct vega10_single_dpm_table display_table; 156 struct vega10_single_dpm_table phy_table; 157 struct vega10_pcie_table pcie_table; 158}; 159 160#define VEGA10_MAX_LEAKAGE_COUNT 8 161struct vega10_leakage_voltage { 162 uint16_t count; 163 uint16_t leakage_id[VEGA10_MAX_LEAKAGE_COUNT]; 164 uint16_t actual_voltage[VEGA10_MAX_LEAKAGE_COUNT]; 165}; 166 167struct vega10_display_timing { 168 uint32_t min_clock_in_sr; 169 uint32_t num_existing_displays; 170}; 171 172struct vega10_dpmlevel_enable_mask { 173 uint32_t uvd_dpm_enable_mask; 174 uint32_t vce_dpm_enable_mask; 175 uint32_t acp_dpm_enable_mask; 176 uint32_t samu_dpm_enable_mask; 177 uint32_t sclk_dpm_enable_mask; 178 uint32_t mclk_dpm_enable_mask; 179}; 180 181struct vega10_vbios_boot_state { 182 bool bsoc_vddc_lock; 183 uint16_t vddc; 184 uint16_t vddci; 185 uint16_t mvddc; 186 uint16_t vdd_gfx; 187 uint32_t gfx_clock; 188 uint32_t mem_clock; 189 uint32_t soc_clock; 190 uint32_t dcef_clock; 191}; 192 193struct vega10_smc_state_table { 194 uint32_t soc_boot_level; 195 uint32_t gfx_boot_level; 196 uint32_t dcef_boot_level; 197 uint32_t mem_boot_level; 198 uint32_t uvd_boot_level; 199 uint32_t vce_boot_level; 200 uint32_t gfx_max_level; 201 uint32_t mem_max_level; 202 uint32_t soc_max_level; 203 uint8_t vr_hot_gpio; 204 uint8_t ac_dc_gpio; 205 uint8_t therm_out_gpio; 206 uint8_t therm_out_polarity; 207 uint8_t therm_out_mode; 208 PPTable_t pp_table; 209 Watermarks_t water_marks_table; 210 AvfsTable_t avfs_table; 211 AvfsFuseOverride_t avfs_fuse_override_table; 212}; 213 214struct vega10_mclk_latency_entries { 215 uint32_t frequency; 216 uint32_t latency; 217}; 218 219struct vega10_mclk_latency_table { 220 uint32_t count; 221 struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 222}; 223 224struct vega10_registry_data { 225 uint8_t ac_dc_switch_gpio_support; 226 uint8_t avfs_support; 227 uint8_t cac_support; 228 uint8_t clock_stretcher_support; 229 uint8_t db_ramping_support; 230 uint8_t didt_mode; 231 uint8_t didt_support; 232 uint8_t edc_didt_support; 233 uint8_t dynamic_state_patching_support; 234 uint8_t enable_pkg_pwr_tracking_feature; 235 uint8_t enable_tdc_limit_feature; 236 uint32_t fast_watermark_threshold; 237 uint8_t force_dpm_high; 238 uint8_t fuzzy_fan_control_support; 239 uint8_t long_idle_baco_support; 240 uint8_t mclk_dpm_key_disabled; 241 uint8_t od_state_in_dc_support; 242 uint8_t pcieLaneOverride; 243 uint8_t pcieSpeedOverride; 244 uint32_t pcieClockOverride; 245 uint8_t pcie_dpm_key_disabled; 246 uint8_t dcefclk_dpm_key_disabled; 247 uint8_t power_containment_support; 248 uint8_t ppt_support; 249 uint8_t prefetcher_dpm_key_disabled; 250 uint8_t quick_transition_support; 251 uint8_t regulator_hot_gpio_support; 252 uint8_t sclk_deep_sleep_support; 253 uint8_t sclk_dpm_key_disabled; 254 uint8_t sclk_from_vbios; 255 uint8_t sclk_throttle_low_notification; 256 uint8_t show_baco_dbg_info; 257 uint8_t skip_baco_hardware; 258 uint8_t socclk_dpm_key_disabled; 259 uint8_t spll_shutdown_support; 260 uint8_t sq_ramping_support; 261 uint32_t stable_pstate_sclk_dpm_percentage; 262 uint8_t tcp_ramping_support; 263 uint8_t tdc_support; 264 uint8_t td_ramping_support; 265 uint8_t dbr_ramping_support; 266 uint8_t gc_didt_support; 267 uint8_t psm_didt_support; 268 uint8_t thermal_out_gpio_support; 269 uint8_t thermal_support; 270 uint8_t fw_ctf_enabled; 271 uint8_t fan_control_support; 272 uint8_t ulps_support; 273 uint8_t ulv_support; 274 uint32_t vddc_vddci_delta; 275 uint8_t odn_feature_enable; 276 uint8_t disable_water_mark; 277 uint8_t zrpm_stop_temp; 278 uint8_t zrpm_start_temp; 279 uint8_t led_dpm_enabled; 280 uint8_t vr0hot_enabled; 281 uint8_t vr1hot_enabled; 282}; 283 284struct vega10_odn_clock_voltage_dependency_table { 285 uint32_t count; 286 struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 287}; 288 289struct vega10_odn_vddc_lookup_table { 290 uint32_t count; 291 struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER]; 292}; 293 294struct vega10_odn_dpm_table { 295 struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_sclk; 296 struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_mclk; 297 struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_socclk; 298 struct vega10_odn_vddc_lookup_table vddc_lookup_table; 299 uint32_t max_vddc; 300 uint32_t min_vddc; 301}; 302 303struct vega10_odn_fan_table { 304 uint32_t target_fan_speed; 305 uint32_t target_temperature; 306 uint32_t min_performance_clock; 307 uint32_t min_fan_limit; 308}; 309 310struct vega10_hwmgr { 311 struct vega10_dpm_table dpm_table; 312 struct vega10_dpm_table golden_dpm_table; 313 struct vega10_registry_data registry_data; 314 struct vega10_vbios_boot_state vbios_boot_state; 315 struct vega10_mclk_latency_table mclk_latency_table; 316 317 struct vega10_leakage_voltage vddc_leakage; 318 319 uint32_t vddc_control; 320 struct pp_atomfwctrl_voltage_table vddc_voltage_table; 321 uint32_t mvdd_control; 322 struct pp_atomfwctrl_voltage_table mvdd_voltage_table; 323 uint32_t vddci_control; 324 struct pp_atomfwctrl_voltage_table vddci_voltage_table; 325 326 uint32_t active_auto_throttle_sources; 327 uint32_t water_marks_bitmap; 328 struct vega10_bacos bacos; 329 330 struct vega10_odn_dpm_table odn_dpm_table; 331 struct vega10_odn_fan_table odn_fan_table; 332 333 /* ---- General data ---- */ 334 uint8_t need_update_dpm_table; 335 336 bool cac_enabled; 337 bool battery_state; 338 bool is_tlu_enabled; 339 340 uint32_t low_sclk_interrupt_threshold; 341 342 uint32_t total_active_cus; 343 344 struct vega10_display_timing display_timing; 345 346 /* ---- Vega10 Dyn Register Settings ---- */ 347 348 uint32_t debug_settings; 349 uint32_t lowest_uclk_reserved_for_ulv; 350 uint32_t gfxclk_average_alpha; 351 uint32_t socclk_average_alpha; 352 uint32_t uclk_average_alpha; 353 uint32_t gfx_activity_average_alpha; 354 uint32_t display_voltage_mode; 355 uint32_t dcef_clk_quad_eqn_a; 356 uint32_t dcef_clk_quad_eqn_b; 357 uint32_t dcef_clk_quad_eqn_c; 358 uint32_t disp_clk_quad_eqn_a; 359 uint32_t disp_clk_quad_eqn_b; 360 uint32_t disp_clk_quad_eqn_c; 361 uint32_t pixel_clk_quad_eqn_a; 362 uint32_t pixel_clk_quad_eqn_b; 363 uint32_t pixel_clk_quad_eqn_c; 364 uint32_t phy_clk_quad_eqn_a; 365 uint32_t phy_clk_quad_eqn_b; 366 uint32_t phy_clk_quad_eqn_c; 367 368 /* ---- Thermal Temperature Setting ---- */ 369 struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; 370 371 /* ---- Power Gating States ---- */ 372 bool uvd_power_gated; 373 bool vce_power_gated; 374 bool need_long_memory_training; 375 376 /* Internal settings to apply the application power optimization parameters */ 377 uint32_t disable_dpm_mask; 378 379 /* ---- SMU9 ---- */ 380 struct smu_features smu_features[GNLD_FEATURES_MAX]; 381 struct vega10_smc_state_table smc_state_table; 382 383 uint32_t config_telemetry; 384 uint32_t acg_loop_state; 385 uint32_t mem_channels; 386 uint8_t custom_profile_mode[4]; 387}; 388 389#define VEGA10_DPM2_NEAR_TDP_DEC 10 390#define VEGA10_DPM2_ABOVE_SAFE_INC 5 391#define VEGA10_DPM2_BELOW_SAFE_INC 20 392 393#define VEGA10_DPM2_LTA_WINDOW_SIZE 7 394 395#define VEGA10_DPM2_LTS_TRUNCATE 0 396 397#define VEGA10_DPM2_TDP_SAFE_LIMIT_PERCENT 80 398 399#define VEGA10_DPM2_MAXPS_PERCENT_M 90 400#define VEGA10_DPM2_MAXPS_PERCENT_H 90 401 402#define VEGA10_DPM2_PWREFFICIENCYRATIO_MARGIN 50 403 404#define VEGA10_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 405#define VEGA10_DPM2_SQ_RAMP_MIN_POWER 0x12 406#define VEGA10_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 407#define VEGA10_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E 408#define VEGA10_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF 409 410#define VEGA10_VOLTAGE_CONTROL_NONE 0x0 411#define VEGA10_VOLTAGE_CONTROL_BY_GPIO 0x1 412#define VEGA10_VOLTAGE_CONTROL_BY_SVID2 0x2 413#define VEGA10_VOLTAGE_CONTROL_MERGED 0x3 414/* To convert to Q8.8 format for firmware */ 415#define VEGA10_Q88_FORMAT_CONVERSION_UNIT 256 416 417#define VEGA10_UNUSED_GPIO_PIN 0x7F 418 419#define VEGA10_THERM_OUT_MODE_DISABLE 0x0 420#define VEGA10_THERM_OUT_MODE_THERM_ONLY 0x1 421#define VEGA10_THERM_OUT_MODE_THERM_VRHOT 0x2 422 423#define PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT 0xffffffff 424#define PPREGKEY_VEGA10QUADRATICEQUATION_DFLT 0xffffffff 425 426#define PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 427#define PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 428#define PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 429#define PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 430 431#define VEGA10_UMD_PSTATE_GFXCLK_LEVEL 0x3 432#define VEGA10_UMD_PSTATE_SOCCLK_LEVEL 0x3 433#define VEGA10_UMD_PSTATE_MCLK_LEVEL 0x2 434 435extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); 436extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); 437extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr); 438extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); 439extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display); 440int vega10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input); 441int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); 442int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); 443int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate); 444int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); 445int vega10_hwmgr_init(struct pp_hwmgr *hwmgr); 446 447#endif /* _VEGA10_HWMGR_H_ */ 448