/linux-master/arch/arm/mach-rockchip/ |
H A D | rockchip.c | 25 void __iomem *reg_base; local 32 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); 33 if (reg_base) { 34 writel(0, reg_base + 0x30); 35 writel(0xffffffff, reg_base + 0x20); 36 writel(0xffffffff, reg_base + 0x24); 37 writel(1, reg_base + 0x30); 39 iounmap(reg_base);
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/linux-master/include/linux/fpga/ |
H A D | altera-pr-ip-core.h | 15 int alt_pr_register(struct device *dev, void __iomem *reg_base);
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/linux-master/drivers/fpga/ |
H A D | altera-pr-ip-core-plat.c | 18 void __iomem *reg_base; local 21 reg_base = devm_platform_ioremap_resource(pdev, 0); 22 if (IS_ERR(reg_base)) 23 return PTR_ERR(reg_base); 25 return alt_pr_register(dev, reg_base);
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H A D | altera-pr-ip-core.c | 29 void __iomem *reg_base; member in struct:alt_pr_priv 39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); 90 val = readl(priv->reg_base + ALT_PR_CSR_OFST); 99 writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); 116 writel(buffer_32[i++], priv->reg_base); 123 writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); 126 writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); 129 writel(buffer_32[i++] & 0x000000ff, priv->reg_base); 176 int alt_pr_register(struct device *dev, void __iomem *reg_base) argument 186 priv->reg_base [all...] |
/linux-master/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix_dp_reg.c | 31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 61 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); 69 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); 72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); 79 writel(reg, dp->reg_base [all...] |
/linux-master/arch/powerpc/boot/ |
H A D | ns16550.c | 31 static unsigned char *reg_base; variable 36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); 42 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); 43 out_8(reg_base, c); 48 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); 49 return in_8(reg_base); 54 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); 62 if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) { 69 reg_base += be32_to_cpu(reg_offset);
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/linux-master/arch/sh/drivers/pci/ |
H A D | pci-sh7780.c | 100 addr = __raw_readl(hose->reg_base + SH4_PCIALR); 105 status = __raw_readw(hose->reg_base + PCI_STATUS); 113 __raw_writew(cmd, hose->reg_base + PCI_STATUS); 119 status = __raw_readl(hose->reg_base + SH4_PCIAINT); 127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); 132 status = __raw_readl(hose->reg_base + SH4_PCIINT); 140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); 154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); 169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); 177 PCI_STATUS_PARITY, hose->reg_base [all...] |
/linux-master/drivers/spi/ |
H A D | spi-loongson-plat.c | 14 void __iomem *reg_base; local 17 reg_base = devm_platform_ioremap_resource(pdev, 0); 18 if (IS_ERR(reg_base)) 19 return PTR_ERR(reg_base); 21 ret = loongson_spi_init_controller(dev, reg_base);
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H A D | spi-gxp.c | 43 void __iomem *reg_base; member in struct:gxp_spi 53 void __iomem *reg_base = spifi->reg_base; local 55 value = readb(reg_base + OFFSET_SPIMCTRL); 58 writeb(0x55, reg_base + OFFSET_SPICMD); 59 writeb(0xaa, reg_base + OFFSET_SPICMD); 64 writeb(value, reg_base + OFFSET_SPIMCTRL); 71 void __iomem *reg_base = spifi->reg_base; local 74 value = readl(reg_base 109 void __iomem *reg_base = spifi->reg_base; local 158 void __iomem *reg_base = spifi->reg_base; local [all...] |
H A D | spi-loongson-pci.c | 14 void __iomem *reg_base; local 26 reg_base = pcim_iomap_table(pdev)[pci_bar]; 28 ret = loongson_spi_init_controller(dev, reg_base);
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H A D | spi-fsl-spi.c | 93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; local 94 __be32 __iomem *mode = ®_base->mode; 238 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; local 243 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 247 mpc8xxx_spi_write_reg(®_base->transmit, word); 256 struct fsl_spi_reg __iomem *reg_base; local 261 reg_base = mpc8xxx_spi->reg_base; 372 struct fsl_spi_reg __iomem *reg_base; local 428 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; local 463 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; local 483 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; local 498 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; local 535 struct fsl_spi_reg __iomem *reg_base; local [all...] |
/linux-master/drivers/gpio/ |
H A D | gpio-bcm-kona.c | 61 void __iomem *reg_base; member in struct:bcm_kona_gpio 76 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, argument 79 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); 80 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); 92 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); 94 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); 108 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); 110 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); 118 void __iomem *reg_base = kona_gpio->reg_base; local 128 void __iomem *reg_base; local 155 void __iomem *reg_base; local 197 void __iomem *reg_base; local 219 void __iomem *reg_base; local 258 void __iomem *reg_base; local 333 void __iomem *reg_base; local 354 void __iomem *reg_base; local 376 void __iomem *reg_base; local 398 void __iomem *reg_base; local 442 void __iomem *reg_base; local 542 void __iomem *reg_base; local [all...] |
H A D | gpio-loongson1.c | 21 void __iomem *reg_base; member in struct:ls1x_gpio_chip 30 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) | BIT(offset), 31 ls1x_gc->reg_base + GPIO_CFG); 43 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) & ~BIT(offset), 44 ls1x_gc->reg_base + GPIO_CFG); 58 ls1x_gc->reg_base = devm_platform_ioremap_resource(pdev, 0); 59 if (IS_ERR(ls1x_gc->reg_base)) 60 return PTR_ERR(ls1x_gc->reg_base); 62 ret = bgpio_init(&ls1x_gc->gc, dev, 4, ls1x_gc->reg_base + GPIO_DATA, 63 ls1x_gc->reg_base [all...] |
H A D | gpio-amdpt.c | 28 void __iomem *reg_base; member in struct:pt_gpio_chip 41 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); 49 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); 64 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); 66 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); 88 pt_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); 89 if (IS_ERR(pt_gpio->reg_base)) { 91 return PTR_ERR(pt_gpio->reg_base); 95 pt_gpio->reg_base + PT_INPUTDATA_REG, 96 pt_gpio->reg_base [all...] |
/linux-master/drivers/irqchip/ |
H A D | irq-csky-apb-intc.c | 34 static void __iomem *reg_base; variable 60 static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base, argument 66 gc->reg_base = reg_base; 111 reg_base = of_iomap(node, 0); 112 if (!reg_base) { 153 readl(reg_base + GX_INTC_PEN63_32), 32); 158 readl(reg_base + GX_INTC_PEN31_00), 0); 175 writel(0x0, reg_base + GX_INTC_NEN31_00); 176 writel(0x0, reg_base [all...] |
H A D | irq-digicolor.c | 57 static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, argument 63 gc->reg_base = reg_base; 74 void __iomem *reg_base; local 79 reg_base = of_iomap(node, 0); 80 if (!reg_base) { 86 writel(0, reg_base + IC_INT0ENABLE_LO); 87 writel(0, reg_base + IC_INT0ENABLE_XLO); 112 digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); 113 digicolor_set_gc(reg_base, 3 [all...] |
/linux-master/drivers/video/fbdev/mmp/hw/ |
H A D | mmp_spi.c | 34 void __iomem *reg_base = (void __iomem *) local 38 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); 42 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); 45 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); 48 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); 55 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); 58 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); 60 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); 63 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); 71 tmp = readl_relaxed(reg_base 83 void __iomem *reg_base = (void __iomem *) local [all...] |
/linux-master/drivers/ata/ |
H A D | ahci_qoriq.c | 61 struct ccsr_ahci *reg_base; member in struct:ahci_qoriq_priv 167 void __iomem *reg_base = hpriv->mmio; local 175 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 176 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); 177 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); 178 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); 179 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); 180 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 183 reg_base + LS1021A_AXICC_ADDR); 193 writel(AHCI_PORT_PHY_1_CFG, reg_base [all...] |
/linux-master/drivers/net/ethernet/cavium/thunder/ |
H A D | thunder_xcv.c | 47 void __iomem *reg_base; member in struct:xcv 70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); 72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); 75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); 77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); 84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); 87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); 92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); 94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); 95 readq_relaxed(xcv->reg_base [all...] |
/linux-master/drivers/misc/mchp_pci1xxxx/ |
H A D | mchp_pci1xxxx_gpio.c | 39 void __iomem *reg_base; member in struct:pci1xxxx_gpio 51 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); 55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); 82 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); 83 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); 93 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; 104 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false); 105 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true); 106 data = readl(priv->reg_base + OUT_OFFSET(nr)); 111 writel(data, priv->reg_base [all...] |
/linux-master/drivers/remoteproc/ |
H A D | qcom_q6v5_wcss.c | 110 void __iomem *reg_base; member in struct:q6v5_wcss 161 val = readl(wcss->reg_base + Q6SS_RESET_REG); 163 writel(val, wcss->reg_base + Q6SS_RESET_REG); 166 val = readl(wcss->reg_base + Q6SS_XO_CBCR); 168 writel(val, wcss->reg_base + Q6SS_XO_CBCR); 171 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, 180 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); 182 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 187 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 190 val = readl(wcss->reg_base [all...] |
/linux-master/drivers/rtc/ |
H A D | rtc-zynqmp.c | 52 void __iomem *reg_base; member in struct:xlnx_rtc_dev 71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); 81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); 92 status = readl(xrtcdev->reg_base + RTC_INT_STS); 99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); 108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; 119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); 120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; 135 status = readl(xrtcdev->reg_base + RTC_INT_STS); 143 writel(RTC_INT_ALRM, xrtcdev->reg_base [all...] |
/linux-master/drivers/clk/rockchip/ |
H A D | softrst.c | 16 void __iomem *reg_base; member in struct:rockchip_softrst 39 softrst->reg_base + (bank * 4)); 46 reg = readl(softrst->reg_base + (bank * 4)); 47 writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); 70 writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); 77 reg = readl(softrst->reg_base + (bank * 4)); 78 writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); 105 softrst->reg_base = base;
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/linux-master/drivers/net/ethernet/marvell/octeontx2/af/ |
H A D | ptp.c | 130 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI); 134 writeq(500000000, ptp->reg_base + PTP_PPS_THRESH_HI); 159 sec = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; 160 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); 161 sec1 = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; 164 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); 174 return readq(ptp->reg_base + PTP_CLOCK_HI); 258 writeq(timestamp, ptp->reg_base + PTP_NANO_TIMESTAMP); 259 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); 261 ptp->reg_base [all...] |
/linux-master/drivers/clk/samsung/ |
H A D | clk-s5pv210-audss.c | 24 static void __iomem *reg_base; variable 43 reg_save[i][1] = readl(reg_base + reg_save[i][0]); 53 writel(reg_save[i][1], reg_base + reg_save[i][0]); 72 reg_base = devm_platform_ioremap_resource(pdev, 0); 73 if (IS_ERR(reg_base)) 74 return PTR_ERR(reg_base); 116 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 127 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); 131 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); 134 reg_base [all...] |