Lines Matching refs:reg_base
52 void __iomem *reg_base;
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
92 status = readl(xrtcdev->reg_base + RTC_INT_STS);
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
135 status = readl(xrtcdev->reg_base + RTC_INT_STS);
143 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
146 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
148 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
161 writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
173 rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
175 writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
186 calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
243 writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
263 status = readl(xrtcdev->reg_base + RTC_INT_STS);
269 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
295 xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
296 if (IS_ERR(xrtcdev->reg_base))
297 return PTR_ERR(xrtcdev->reg_base);
334 ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
336 writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));