drivers/remoteproc/qcom_q6v5_wcss.c

110 	void __iomem *reg_base;
161 	val = readl(wcss->reg_base + Q6SS_RESET_REG);
163 	writel(val, wcss->reg_base + Q6SS_RESET_REG);
166 	val = readl(wcss->reg_base + Q6SS_XO_CBCR);
168 	writel(val, wcss->reg_base + Q6SS_XO_CBCR);
171 	ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,
180 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
182 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
187 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
190 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
192 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
196 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
199 	val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
202 		writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
208 		val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
212 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
214 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
218 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
221 	val = readl(wcss->reg_base + Q6SS_RESET_REG);
223 	writel(val, wcss->reg_base + Q6SS_RESET_REG);
226 	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
228 	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
231 	val = readl(wcss->reg_base + Q6SS_RESET_REG);
233 	writel(val, wcss->reg_base + Q6SS_RESET_REG);
273 	writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
344 	val = readl(wcss->reg_base + Q6SS_XO_CBCR);
346 	writel(val, wcss->reg_base + Q6SS_XO_CBCR);
348 	ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,
357 	writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE);
360 	val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
362 	writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
370 	val = readl(wcss->reg_base + Q6SS_RESET_REG);
372 	writel(val, wcss->reg_base + Q6SS_RESET_REG);
375 	writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
377 	writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
379 	writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG);
381 	writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
388 		writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) |
389 			(1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL);
392 	writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
393 	writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
395 	val = readl(wcss->reg_base + Q6SS_RESET_REG);
397 	writel(val, wcss->reg_base + Q6SS_RESET_REG);
400 	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
402 	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
412 	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
414 	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
417 	val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
419 	writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
421 	val = readl(wcss->reg_base + Q6SS_XO_CBCR);
423 	writel(val, wcss->reg_base + Q6SS_XO_CBCR);
445 	writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC);
448 	val = readl(wcss->reg_base + Q6SS_RESET_REG);
450 	writel(val, wcss->reg_base + Q6SS_RESET_REG);
476 	writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
538 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
540 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
543 	writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) &
545 		wcss->reg_base + Q6SS_MEM_PWR_CTL);
548 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
550 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
558 	val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
560 	writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
562 	val = readl(wcss->reg_base + Q6SS_XO_CBCR);
564 	writel(val, wcss->reg_base + Q6SS_XO_CBCR);
569 	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
571 	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
650 	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
652 	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
655 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
657 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
661 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
665 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
669 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
673 		val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
675 		writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
680 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
682 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
686 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
690 	ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS,
834 	wcss->reg_base = devm_ioremap(&pdev->dev, res->start,
836 	if (!wcss->reg_base)