Searched refs:pll_base (Results 1 - 22 of 22) sorted by relevance

/linux-master/drivers/clk/imx/
H A Dclk-imxrt1050.c39 void __iomem *pll_base; local
56 pll_base = devm_of_iomap(dev, anp, 0, NULL);
58 if (WARN_ON(IS_ERR(pll_base))) {
59 ret = PTR_ERR(pll_base);
67 pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
69 pll_base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
71 pll_base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
73 pll_base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
76 "pll1_arm_ref_sel", pll_base + 0x0, 0x7f);
78 "pll2_sys_ref_sel", pll_base
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H A Dclk-imx5.c283 void __iomem *pll_base; local
286 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
287 WARN_ON(!pll_base);
288 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
290 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
291 WARN_ON(!pll_base);
292 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
294 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
295 WARN_ON(!pll_base);
296 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
368 void __iomem *pll_base; local
474 void __iomem *pll_base; local
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/linux-master/drivers/clk/visconti/
H A Dpll.c21 void __iomem *pll_base; member in struct:visconti_pll
61 val = readl(pll->pll_base + PLL_FRACMODE_REG);
66 rate_table->fracin = readl(pll->pll_base + PLL_FRACIN_REG) & PLL_FRACIN_MASK;
67 rate_table->intin = readl(pll->pll_base + PLL_INTIN_REG) & PLL_INTIN_MASK;
68 rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK;
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG);
134 writel(PLL_CREATE_FRACMODE(rate_table), pll->pll_base + PLL_FRACMODE_REG);
135 writel(PLL_CREATE_OSTDIV(rate_table), pll->pll_base + PLL_POSTDIV_REG);
136 writel(rate_table->intin, pll->pll_base + PLL_INTIN_REG);
137 writel(rate_table->fracin, pll->pll_base
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/linux-master/arch/mips/ath79/
H A Dclock.c93 static void __init ar71xx_clocks_init(void __iomem *pll_base) argument
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
124 static void __init ar724x_clocks_init(void __iomem *pll_base) argument
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
144 static void __init ar933x_clocks_init(void __iomem *pll_base) argument
165 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
178 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
232 static void __init ar934x_clocks_init(void __iomem *pll_base) argument
265 pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
292 pll = __raw_readl(pll_base
350 qca953x_clocks_init(void __iomem *pll_base) argument
433 qca955x_clocks_init(void __iomem *pll_base) argument
516 qca956x_clocks_init(void __iomem *pll_base) argument
621 void __iomem *pll_base; local
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/linux-master/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c37 void __iomem **pll_base; member in struct:mpfs_ccc_data
173 out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
209 pll_hw->base = data->pll_base[i];
233 void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)]; local
245 pll_base[0] = devm_platform_ioremap_resource(pdev, 0);
246 if (IS_ERR(pll_base[0]))
247 return PTR_ERR(pll_base[0]);
249 pll_base[1] = devm_platform_ioremap_resource(pdev, 1);
250 if (IS_ERR(pll_base[1]))
251 return PTR_ERR(pll_base[
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/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A Dvideo-pll.c133 void __iomem *pll_base, *clkctrl_base; local
140 pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]);
141 if (IS_ERR(pll_base)) {
143 return ERR_CAST(pll_base);
175 pll->base = pll_base;
H A Ddsi.c294 void __iomem *pll_base; member in struct:dsi_data
440 case DSI_PLL: base = dsi->pll_base; break;
456 case DSI_PLL: base = dsi->pll_base; break;
5224 pll->base = dsi->pll_base;
5349 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5351 if (!dsi->pll_base) {
/linux-master/drivers/gpu/drm/omapdrm/dss/
H A Dvideo-pll.c141 void __iomem *pll_base, *clkctrl_base; local
148 pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]);
149 if (IS_ERR(pll_base))
150 return ERR_CAST(pll_base);
179 pll->base = pll_base;
H A Ddsi.h343 void __iomem *pll_base; member in struct:dsi_data
H A Ddsi.c94 case DSI_PLL: base = dsi->pll_base; break;
108 case DSI_PLL: base = dsi->pll_base; break;
4543 pll->base = dsi->pll_base;
4933 dsi->pll_base = devm_platform_ioremap_resource_byname(pdev, "pll");
4934 if (IS_ERR(dsi->pll_base))
4935 return PTR_ERR(dsi->pll_base);
/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm_8960.c77 val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY);
97 void __iomem *base = pll_28nm->phy->pll_base;
146 void __iomem *base = pll_28nm->phy->pll_base;
180 void __iomem *base = pll_28nm->phy->pll_base;
233 dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
347 void __iomem *base = pll_28nm->phy->pll_base;
363 void __iomem *base = pll_28nm->phy->pll_base;
418 bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
439 &pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base +
H A Ddsi_phy_28nm.c86 val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS);
101 void __iomem *base = pll_28nm->phy->pll_base;
120 void __iomem *base = pll_28nm->phy->pll_base;
244 void __iomem *base = pll_28nm->phy->pll_base;
291 void __iomem *base = pll_28nm->phy->pll_base;
385 void __iomem *base = pll_28nm->phy->pll_base;
453 void __iomem *base = pll_28nm->phy->pll_base;
507 dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
560 void __iomem *base = pll_28nm->phy->pll_base;
577 void __iomem *base = pll_28nm->phy->pll_base;
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H A Ddsi_phy_10nm.c185 void __iomem *base = pll->phy->pll_base;
209 void __iomem *base = pll->phy->pll_base;
238 void __iomem *base = pll->phy->pll_base;
293 rc = readl_poll_timeout_atomic(pll->phy->pll_base +
310 dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
322 dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
424 void __iomem *base = pll_10nm->phy->pll_base;
491 cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base +
515 val = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
518 dsi_phy_write(pll_10nm->phy->pll_base
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H A Ddsi_phy_7nm.c192 void __iomem *base = pll->phy->pll_base;
216 void __iomem *base = pll->phy->pll_base;
274 dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
280 void __iomem *base = pll->phy->pll_base;
335 rc = readl_poll_timeout_atomic(pll->phy->pll_base +
352 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
362 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
473 void __iomem *base = pll_7nm->phy->pll_base;
540 cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base +
564 val = dsi_phy_read(pll_7nm->phy->pll_base
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H A Ddsi_phy.h99 void __iomem *pll_base; member in struct:msm_dsi_phy
H A Ddsi_phy_14nm.c114 void __iomem *base = pll_14nm->phy->pll_base;
286 void __iomem *base = pll->phy->pll_base;
321 void __iomem *base = pll->phy->pll_base;
385 void __iomem *base = pll->phy->pll_base;
494 void __iomem *base = pll_14nm->phy->pll_base;
533 void __iomem *base = pll_14nm->phy->pll_base;
742 void __iomem *base = phy->pll_base;
H A Ddsi_phy.c660 phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", &phy->pll_size);
661 if (IS_ERR(phy->pll_base))
662 return dev_err_probe(dev, PTR_ERR(phy->pll_base),
867 phy->pll_size, phy->pll_base,
/linux-master/drivers/clk/
H A Dclk-sp7021.c588 #define PLLA_CTL (pll_base + 0x1c)
589 #define PLLE_CTL (pll_base + 0x30)
590 #define PLLF_CTL (pll_base + 0x34)
591 #define PLLTV_CTL (pll_base + 0x38)
601 void __iomem *clk_base, *pll_base, *sys_base; local
609 pll_base = devm_platform_ioremap_resource(pdev, 1);
610 if (IS_ERR(pll_base))
611 return PTR_ERR(pll_base);
H A Dclk-bm1880.c63 void __iomem *pll_base; member in struct:bm1880_clock_data
530 void __iomem *pll_base = data->pll_base; local
536 hw = bm1880_clk_register_pll(bm1880_clk, pll_base);
877 void __iomem *pll_base, *sys_base; local
881 pll_base = devm_platform_ioremap_resource(pdev, 0);
882 if (IS_ERR(pll_base))
883 return PTR_ERR(pll_base);
900 clk_data->pll_base = pll_base;
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/linux-master/arch/arm/mach-tegra/
H A Dsleep-tegra20.S57 .macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
58 ldr \rd, [\r_car_base, #\pll_base]
67 .macro pll_enable, rd, r_car_base, pll_base, test_mask
71 ldr \rd, [\r_car_base, #\pll_base]
74 streq \rd, [\r_car_base, #\pll_base]
H A Dsleep-tegra30.S104 .macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
105 ldr \rd, [\r_car_base, #\pll_base]
132 .macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask
136 ldr \rd, [\r_car_base, #\pll_base]
139 streq \rd, [\r_car_base, #\pll_base]
153 .macro pll_locked, rd, r_car_base, pll_base, test_mask
157 ldr \rd, [\r_car_base, #\pll_base]
/linux-master/drivers/clk/st/
H A Dclkgen-pll.c755 void __iomem *pll_base; local
765 pll_base = clkgen_get_register_base(np);
766 if (!pll_base)
771 clk = clkgen_pll_register(parent_name, datac->data, pll_base, pll_flags,
808 clk = clkgen_odf_register(pll_name, pll_base, datac->data,

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