1// SPDX-License-Identifier: GPL-2.0-only
2/*
3* Copyright (C) 2014 Texas Instruments Ltd
4*/
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12#include <linux/sched.h>
13
14#include <video/omapfb_dss.h>
15
16#include "dss.h"
17#include "dss_features.h"
18
19struct dss_video_pll {
20	struct dss_pll pll;
21
22	struct device *dev;
23
24	void __iomem *clkctrl_base;
25};
26
27#define REG_MOD(reg, val, start, end) \
28	writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
29
30static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
31{
32	REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
33}
34
35static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
36{
37	REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
38}
39
40static void dss_dpll_power_enable(struct dss_video_pll *vpll)
41{
42	REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
43
44	/*
45	 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
46	 * so we have to use fixed delay here.
47	 */
48	msleep(1);
49}
50
51static void dss_dpll_power_disable(struct dss_video_pll *vpll)
52{
53	REG_MOD(vpll->clkctrl_base, 0, 31, 30);	/* PLL_POWER_OFF */
54}
55
56static int dss_video_pll_enable(struct dss_pll *pll)
57{
58	struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
59	int r;
60
61	r = dss_runtime_get();
62	if (r)
63		return r;
64
65	dss_ctrl_pll_enable(pll->id, true);
66
67	dss_dpll_enable_scp_clk(vpll);
68
69	r = dss_pll_wait_reset_done(pll);
70	if (r)
71		goto err_reset;
72
73	dss_dpll_power_enable(vpll);
74
75	return 0;
76
77err_reset:
78	dss_dpll_disable_scp_clk(vpll);
79	dss_ctrl_pll_enable(pll->id, false);
80	dss_runtime_put();
81
82	return r;
83}
84
85static void dss_video_pll_disable(struct dss_pll *pll)
86{
87	struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
88
89	dss_dpll_power_disable(vpll);
90
91	dss_dpll_disable_scp_clk(vpll);
92
93	dss_ctrl_pll_enable(pll->id, false);
94
95	dss_runtime_put();
96}
97
98static const struct dss_pll_ops dss_pll_ops = {
99	.enable = dss_video_pll_enable,
100	.disable = dss_video_pll_disable,
101	.set_config = dss_pll_write_config_type_a,
102};
103
104static const struct dss_pll_hw dss_dra7_video_pll_hw = {
105	.n_max = (1 << 8) - 1,
106	.m_max = (1 << 12) - 1,
107	.mX_max = (1 << 5) - 1,
108	.fint_min = 500000,
109	.fint_max = 2500000,
110	.clkdco_max = 1800000000,
111
112	.n_msb = 8,
113	.n_lsb = 1,
114	.m_msb = 20,
115	.m_lsb = 9,
116
117	.mX_msb[0] = 25,
118	.mX_lsb[0] = 21,
119	.mX_msb[1] = 30,
120	.mX_lsb[1] = 26,
121
122	.has_refsel = true,
123};
124
125struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
126	struct regulator *regulator)
127{
128	const char * const reg_name[] = { "pll1", "pll2" };
129	const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
130	const char * const clkin_name[] = { "video1_clk", "video2_clk" };
131
132	struct dss_video_pll *vpll;
133	void __iomem *pll_base, *clkctrl_base;
134	struct clk *clk;
135	struct dss_pll *pll;
136	int r;
137
138	/* PLL CONTROL */
139
140	pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]);
141	if (IS_ERR(pll_base)) {
142		dev_err(&pdev->dev, "failed to ioremap pll%d reg_name\n", id);
143		return ERR_CAST(pll_base);
144	}
145
146	/* CLOCK CONTROL */
147
148	clkctrl_base = devm_platform_ioremap_resource_byname(pdev, clkctrl_name[id]);
149	if (IS_ERR(clkctrl_base)) {
150		dev_err(&pdev->dev, "failed to ioremap pll%d clkctrl\n", id);
151		return ERR_CAST(clkctrl_base);
152	}
153
154	/* CLKIN */
155
156	clk = devm_clk_get(&pdev->dev, clkin_name[id]);
157	if (IS_ERR(clk)) {
158		DSSERR("can't get video pll clkin\n");
159		return ERR_CAST(clk);
160	}
161
162	vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
163	if (!vpll)
164		return ERR_PTR(-ENOMEM);
165
166	vpll->dev = &pdev->dev;
167	vpll->clkctrl_base = clkctrl_base;
168
169	pll = &vpll->pll;
170
171	pll->name = id == 0 ? "video0" : "video1";
172	pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
173	pll->clkin = clk;
174	pll->regulator = regulator;
175	pll->base = pll_base;
176	pll->hw = &dss_dra7_video_pll_hw;
177	pll->ops = &dss_pll_ops;
178
179	r = dss_pll_register(pll);
180	if (r)
181		return ERR_PTR(r);
182
183	return pll;
184}
185
186void dss_video_pll_uninit(struct dss_pll *pll)
187{
188	dss_pll_unregister(pll);
189}
190