1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 */
6
7#ifndef __OMAP_DRM_DSS_DSI_H
8#define __OMAP_DRM_DSS_DSI_H
9
10#include <drm/drm_mipi_dsi.h>
11
12struct dsi_reg {
13	u16 module;
14	u16 idx;
15};
16
17#define DSI_REG(mod, idx)		((const struct dsi_reg) { mod, idx })
18
19/* DSI Protocol Engine */
20
21#define DSI_PROTO			0
22#define DSI_PROTO_SZ			0x200
23
24#define DSI_REVISION			DSI_REG(DSI_PROTO, 0x0000)
25#define DSI_SYSCONFIG			DSI_REG(DSI_PROTO, 0x0010)
26#define DSI_SYSSTATUS			DSI_REG(DSI_PROTO, 0x0014)
27#define DSI_IRQSTATUS			DSI_REG(DSI_PROTO, 0x0018)
28#define DSI_IRQENABLE			DSI_REG(DSI_PROTO, 0x001C)
29#define DSI_CTRL			DSI_REG(DSI_PROTO, 0x0040)
30#define DSI_GNQ				DSI_REG(DSI_PROTO, 0x0044)
31#define DSI_COMPLEXIO_CFG1		DSI_REG(DSI_PROTO, 0x0048)
32#define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(DSI_PROTO, 0x004C)
33#define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(DSI_PROTO, 0x0050)
34#define DSI_CLK_CTRL			DSI_REG(DSI_PROTO, 0x0054)
35#define DSI_TIMING1			DSI_REG(DSI_PROTO, 0x0058)
36#define DSI_TIMING2			DSI_REG(DSI_PROTO, 0x005C)
37#define DSI_VM_TIMING1			DSI_REG(DSI_PROTO, 0x0060)
38#define DSI_VM_TIMING2			DSI_REG(DSI_PROTO, 0x0064)
39#define DSI_VM_TIMING3			DSI_REG(DSI_PROTO, 0x0068)
40#define DSI_CLK_TIMING			DSI_REG(DSI_PROTO, 0x006C)
41#define DSI_TX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0070)
42#define DSI_RX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0074)
43#define DSI_COMPLEXIO_CFG2		DSI_REG(DSI_PROTO, 0x0078)
44#define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(DSI_PROTO, 0x007C)
45#define DSI_VM_TIMING4			DSI_REG(DSI_PROTO, 0x0080)
46#define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(DSI_PROTO, 0x0084)
47#define DSI_VM_TIMING5			DSI_REG(DSI_PROTO, 0x0088)
48#define DSI_VM_TIMING6			DSI_REG(DSI_PROTO, 0x008C)
49#define DSI_VM_TIMING7			DSI_REG(DSI_PROTO, 0x0090)
50#define DSI_STOPCLK_TIMING		DSI_REG(DSI_PROTO, 0x0094)
51#define DSI_VC_CTRL(n)			DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
52#define DSI_VC_TE(n)			DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
53#define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
54#define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
55#define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
56#define DSI_VC_IRQSTATUS(n)		DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
57#define DSI_VC_IRQENABLE(n)		DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
58
59/* DSIPHY_SCP */
60
61#define DSI_PHY				1
62#define DSI_PHY_OFFSET			0x200
63#define DSI_PHY_SZ			0x40
64
65#define DSI_DSIPHY_CFG0			DSI_REG(DSI_PHY, 0x0000)
66#define DSI_DSIPHY_CFG1			DSI_REG(DSI_PHY, 0x0004)
67#define DSI_DSIPHY_CFG2			DSI_REG(DSI_PHY, 0x0008)
68#define DSI_DSIPHY_CFG5			DSI_REG(DSI_PHY, 0x0014)
69#define DSI_DSIPHY_CFG10		DSI_REG(DSI_PHY, 0x0028)
70
71/* DSI_PLL_CTRL_SCP */
72
73#define DSI_PLL				2
74#define DSI_PLL_OFFSET			0x300
75#define DSI_PLL_SZ			0x20
76
77#define DSI_PLL_CONTROL			DSI_REG(DSI_PLL, 0x0000)
78#define DSI_PLL_STATUS			DSI_REG(DSI_PLL, 0x0004)
79#define DSI_PLL_GO			DSI_REG(DSI_PLL, 0x0008)
80#define DSI_PLL_CONFIGURATION1		DSI_REG(DSI_PLL, 0x000C)
81#define DSI_PLL_CONFIGURATION2		DSI_REG(DSI_PLL, 0x0010)
82
83/* Global interrupts */
84#define DSI_IRQ_VC0		(1 << 0)
85#define DSI_IRQ_VC1		(1 << 1)
86#define DSI_IRQ_VC2		(1 << 2)
87#define DSI_IRQ_VC3		(1 << 3)
88#define DSI_IRQ_WAKEUP		(1 << 4)
89#define DSI_IRQ_RESYNC		(1 << 5)
90#define DSI_IRQ_PLL_LOCK	(1 << 7)
91#define DSI_IRQ_PLL_UNLOCK	(1 << 8)
92#define DSI_IRQ_PLL_RECALL	(1 << 9)
93#define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
94#define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
95#define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
96#define DSI_IRQ_TE_TRIGGER	(1 << 16)
97#define DSI_IRQ_ACK_TRIGGER	(1 << 17)
98#define DSI_IRQ_SYNC_LOST	(1 << 18)
99#define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
100#define DSI_IRQ_TA_TIMEOUT	(1 << 20)
101#define DSI_IRQ_ERROR_MASK \
102	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
103	DSI_IRQ_TA_TIMEOUT)
104#define DSI_IRQ_CHANNEL_MASK	0xf
105
106/* Virtual channel interrupts */
107#define DSI_VC_IRQ_CS		(1 << 0)
108#define DSI_VC_IRQ_ECC_CORR	(1 << 1)
109#define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
110#define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
111#define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
112#define DSI_VC_IRQ_BTA		(1 << 5)
113#define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
114#define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
115#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
116#define DSI_VC_IRQ_ERROR_MASK \
117	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
118	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
119	DSI_VC_IRQ_FIFO_TX_UDF)
120
121/* ComplexIO interrupts */
122#define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
123#define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
124#define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
125#define DSI_CIO_IRQ_ERRSYNCESC4		(1 << 3)
126#define DSI_CIO_IRQ_ERRSYNCESC5		(1 << 4)
127#define DSI_CIO_IRQ_ERRESC1		(1 << 5)
128#define DSI_CIO_IRQ_ERRESC2		(1 << 6)
129#define DSI_CIO_IRQ_ERRESC3		(1 << 7)
130#define DSI_CIO_IRQ_ERRESC4		(1 << 8)
131#define DSI_CIO_IRQ_ERRESC5		(1 << 9)
132#define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
133#define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
134#define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
135#define DSI_CIO_IRQ_ERRCONTROL4		(1 << 13)
136#define DSI_CIO_IRQ_ERRCONTROL5		(1 << 14)
137#define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
138#define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
139#define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
140#define DSI_CIO_IRQ_STATEULPS4		(1 << 18)
141#define DSI_CIO_IRQ_STATEULPS5		(1 << 19)
142#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
143#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
144#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
145#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
146#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
147#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
148#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4	(1 << 26)
149#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4	(1 << 27)
150#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5	(1 << 28)
151#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5	(1 << 29)
152#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
153#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
154#define DSI_CIO_IRQ_ERROR_MASK \
155	(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
156	 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
157	 DSI_CIO_IRQ_ERRSYNCESC5 | \
158	 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
159	 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
160	 DSI_CIO_IRQ_ERRESC5 | \
161	 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
162	 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
163	 DSI_CIO_IRQ_ERRCONTROL5 | \
164	 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
165	 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
166	 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
167	 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
168	 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
169
170enum omap_dss_dsi_mode {
171	OMAP_DSS_DSI_CMD_MODE = 0,
172	OMAP_DSS_DSI_VIDEO_MODE,
173};
174
175enum omap_dss_dsi_trans_mode {
176	/* Sync Pulses: both sync start and end packets sent */
177	OMAP_DSS_DSI_PULSE_MODE,
178	/* Sync Events: only sync start packets sent */
179	OMAP_DSS_DSI_EVENT_MODE,
180	/* Burst: only sync start packets sent, pixels are time compressed */
181	OMAP_DSS_DSI_BURST_MODE,
182};
183
184struct omap_dss_dsi_videomode_timings {
185	unsigned long hsclk;
186
187	unsigned int ndl;
188	unsigned int bitspp;
189
190	/* pixels */
191	u16 hact;
192	/* lines */
193	u16 vact;
194
195	/* DSI video mode blanking data */
196	/* Unit: byte clock cycles */
197	u16 hss;
198	u16 hsa;
199	u16 hse;
200	u16 hfp;
201	u16 hbp;
202	/* Unit: line clocks */
203	u16 vsa;
204	u16 vfp;
205	u16 vbp;
206
207	/* DSI blanking modes */
208	int blanking_mode;
209	int hsa_blanking_mode;
210	int hbp_blanking_mode;
211	int hfp_blanking_mode;
212
213	enum omap_dss_dsi_trans_mode trans_mode;
214
215	int window_sync;
216};
217
218struct omap_dss_dsi_config {
219	enum omap_dss_dsi_mode mode;
220	enum mipi_dsi_pixel_format pixel_format;
221	const struct videomode *vm;
222
223	unsigned long hs_clk_min, hs_clk_max;
224	unsigned long lp_clk_min, lp_clk_max;
225
226	enum omap_dss_dsi_trans_mode trans_mode;
227};
228
229/* DSI PLL HSDIV indices */
230#define HSDIV_DISPC	0
231#define HSDIV_DSI	1
232
233#define DSI_MAX_NR_ISRS                2
234#define DSI_MAX_NR_LANES	5
235
236enum dsi_model {
237	DSI_MODEL_OMAP3,
238	DSI_MODEL_OMAP4,
239	DSI_MODEL_OMAP5,
240};
241
242enum dsi_lane_function {
243	DSI_LANE_UNUSED	= 0,
244	DSI_LANE_CLK,
245	DSI_LANE_DATA1,
246	DSI_LANE_DATA2,
247	DSI_LANE_DATA3,
248	DSI_LANE_DATA4,
249};
250
251struct dsi_lane_config {
252	enum dsi_lane_function function;
253	u8 polarity;
254};
255
256typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
257
258struct dsi_isr_data {
259	omap_dsi_isr_t	isr;
260	void		*arg;
261	u32		mask;
262};
263
264enum fifo_size {
265	DSI_FIFO_SIZE_0		= 0,
266	DSI_FIFO_SIZE_32	= 1,
267	DSI_FIFO_SIZE_64	= 2,
268	DSI_FIFO_SIZE_96	= 3,
269	DSI_FIFO_SIZE_128	= 4,
270};
271
272enum dsi_vc_source {
273	DSI_VC_SOURCE_L4 = 0,
274	DSI_VC_SOURCE_VP,
275};
276
277struct dsi_irq_stats {
278	unsigned long last_reset;
279	unsigned int irq_count;
280	unsigned int dsi_irqs[32];
281	unsigned int vc_irqs[4][32];
282	unsigned int cio_irqs[32];
283};
284
285struct dsi_isr_tables {
286	struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
287	struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
288	struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
289};
290
291struct dsi_lp_clock_info {
292	unsigned long lp_clk;
293	u16 lp_clk_div;
294};
295
296struct dsi_clk_calc_ctx {
297	struct dsi_data *dsi;
298	struct dss_pll *pll;
299
300	/* inputs */
301
302	const struct omap_dss_dsi_config *config;
303
304	unsigned long req_pck_min, req_pck_nom, req_pck_max;
305
306	/* outputs */
307
308	struct dss_pll_clock_info dsi_cinfo;
309	struct dispc_clock_info dispc_cinfo;
310	struct dsi_lp_clock_info lp_cinfo;
311
312	struct videomode vm;
313	struct omap_dss_dsi_videomode_timings dsi_vm;
314};
315
316struct dsi_module_id_data {
317	u32 address;
318	int id;
319};
320
321enum dsi_quirks {
322	DSI_QUIRK_PLL_PWR_BUG = (1 << 0),	/* DSI-PLL power command 0x3 is not working */
323	DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1),
324	DSI_QUIRK_VC_OCP_WIDTH = (1 << 2),
325	DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3),
326	DSI_QUIRK_GNQ = (1 << 4),
327	DSI_QUIRK_PHY_DCC = (1 << 5),
328};
329
330struct dsi_of_data {
331	enum dsi_model model;
332	const struct dss_pll_hw *pll_hw;
333	const struct dsi_module_id_data *modules;
334	unsigned int max_fck_freq;
335	unsigned int max_pll_lpdiv;
336	enum dsi_quirks quirks;
337};
338
339struct dsi_data {
340	struct device *dev;
341	void __iomem *proto_base;
342	void __iomem *phy_base;
343	void __iomem *pll_base;
344
345	const struct dsi_of_data *data;
346	int module_id;
347
348	int irq;
349
350	bool is_enabled;
351
352	struct clk *dss_clk;
353	struct regmap *syscon;
354	struct dss_device *dss;
355
356	struct mipi_dsi_host host;
357
358	struct dispc_clock_info user_dispc_cinfo;
359	struct dss_pll_clock_info user_dsi_cinfo;
360
361	struct dsi_lp_clock_info user_lp_cinfo;
362	struct dsi_lp_clock_info current_lp_cinfo;
363
364	struct dss_pll pll;
365
366	bool vdds_dsi_enabled;
367	struct regulator *vdds_dsi_reg;
368
369	struct mipi_dsi_device *dsidev;
370
371	struct {
372		enum dsi_vc_source source;
373		enum fifo_size tx_fifo_size;
374		enum fifo_size rx_fifo_size;
375	} vc[4];
376
377	struct mutex lock;
378	struct semaphore bus_lock;
379
380	spinlock_t irq_lock;
381	struct dsi_isr_tables isr_tables;
382	/* space for a copy used by the interrupt handler */
383	struct dsi_isr_tables isr_tables_copy;
384
385	int update_vc;
386#ifdef DSI_PERF_MEASURE
387	unsigned int update_bytes;
388#endif
389
390	/* external TE GPIO */
391	struct gpio_desc *te_gpio;
392	int te_irq;
393	struct delayed_work te_timeout_work;
394	atomic_t do_ext_te_update;
395
396	bool te_enabled;
397	bool iface_enabled;
398	bool video_enabled;
399
400	struct delayed_work framedone_timeout_work;
401
402#ifdef DSI_CATCH_MISSING_TE
403	struct timer_list te_timer;
404#endif
405
406	unsigned long cache_req_pck;
407	unsigned long cache_clk_freq;
408	struct dss_pll_clock_info cache_cinfo;
409
410	u32		errors;
411	spinlock_t	errors_lock;
412#ifdef DSI_PERF_MEASURE
413	ktime_t perf_setup_time;
414	ktime_t perf_start_time;
415#endif
416	int debug_read;
417	int debug_write;
418	struct {
419		struct dss_debugfs_entry *irqs;
420		struct dss_debugfs_entry *regs;
421		struct dss_debugfs_entry *clks;
422	} debugfs;
423
424#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
425	spinlock_t irq_stats_lock;
426	struct dsi_irq_stats irq_stats;
427#endif
428
429	unsigned int num_lanes_supported;
430	unsigned int line_buffer_size;
431
432	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
433	unsigned int num_lanes_used;
434
435	unsigned int scp_clk_refcount;
436
437	struct omap_dss_dsi_config config;
438
439	struct dss_lcd_mgr_config mgr_config;
440	struct videomode vm;
441	enum mipi_dsi_pixel_format pix_fmt;
442	enum omap_dss_dsi_mode mode;
443	struct omap_dss_dsi_videomode_timings vm_timings;
444
445	struct omap_dss_device output;
446	struct drm_bridge bridge;
447
448	struct delayed_work dsi_disable_work;
449};
450
451struct dsi_packet_sent_handler_data {
452	struct dsi_data *dsi;
453	struct completion *completion;
454};
455
456#endif /* __OMAP_DRM_DSS_DSI_H */
457