/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_display_wa.c | 18 intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP); 28 intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0); 34 intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); 37 intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
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H A D | intel_dpt_common.c | 23 intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id), 29 intel_de_rmw(i915, CHICKEN_MISC_2,
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H A D | intel_fdi.c | 499 intel_de_rmw(dev_priv, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); 571 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 573 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), 662 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 713 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 835 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 838 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), 952 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), 979 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); 983 intel_de_rmw(dev_pri [all...] |
H A D | intel_combo_phy.c | 84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), 302 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), 363 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy), 366 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); 367 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 398 intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0, 402 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);
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H A D | icl_dsi.c | 228 intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST); 251 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val); 261 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val); 267 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val); 271 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), 315 intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, 404 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port), 431 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0); 433 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), 439 intel_de_rmw(dev_pri [all...] |
H A D | intel_audio.c | 265 intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 282 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 300 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 314 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 326 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 399 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 408 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 415 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 544 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 550 intel_de_rmw(i91 [all...] |
H A D | vlv_dsi.c | 342 intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); 345 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 350 intel_de_rmw(dev_priv, MIPI_CTRL(port), 384 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); 389 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 394 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 403 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 407 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 411 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); 443 intel_de_rmw(dev_pri [all...] |
H A D | intel_dkl_phy.c | 94 intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set);
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H A D | intel_display_power_well.c | 356 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 369 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 395 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 422 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 426 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), 434 intel_de_rmw(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), 450 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), 453 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 518 intel_de_rmw(dev_priv, DP_AUX_CH_CTL(aux_ch), 521 intel_de_rmw(dev_pri [all...] |
H A D | intel_pch_display.c | 324 intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0); 332 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe), 459 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe), 464 intel_de_rmw(dev_priv, PCH_DPLL_SEL, 575 intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0); 582 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
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H A D | intel_de.h | 45 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) function
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H A D | intel_dpio_phy.c | 392 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask); 411 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy), IREF0RC_OFFSET_MASK, 414 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy), IREF1RC_OFFSET_MASK, 418 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0, 422 intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0, 442 intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy), 449 intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS); 458 intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0); 460 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
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H A D | intel_psr.c | 338 intel_de_rmw(dev_priv, psr_imr_reg(dev_priv, cpu_transcoder), 402 val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0); 422 intel_de_rmw(dev_priv, psr_imr_reg(dev_priv, cpu_transcoder), 754 intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), 810 intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 813 intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, 931 intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder), 1561 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 1564 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 1640 intel_de_rmw(dev_pri [all...] |
H A D | intel_dmc.c | 322 intel_de_rmw(i915, DC_STATE_DEBUG, 0, 372 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 376 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 387 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, 407 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 409 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 420 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 422 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
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H A D | intel_display_power.c | 1064 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST, 1141 intel_de_rmw(dev_priv, DBUF_CTL_S(slice), 1172 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val); 1310 intel_de_rmw(dev_priv, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1354 intel_de_rmw(dev_priv, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1396 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1431 intel_de_rmw(dev_priv, reg, reset_bits, enable ? reset_bits : 0); 1634 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), 1652 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, 1674 intel_de_rmw(dev_pri [all...] |
H A D | intel_dpll_mgr.c | 702 intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); 718 intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0); 1339 intel_de_rmw(i915, DPLL_CTRL1, 1359 intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE); 1378 intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0); 2004 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); 2007 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 2017 intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch), 2021 intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch), 2025 intel_de_rmw(i91 [all...] |
H A D | intel_ddi.c | 688 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 1129 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1146 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1158 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1169 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1203 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1209 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1242 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1244 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1254 intel_de_rmw(dev_pri [all...] |
H A D | intel_dvo.c | 194 intel_de_rmw(i915, DVO(port), DVO_ENABLE, 0); 211 intel_de_rmw(i915, DVO(port), 0, DVO_ENABLE); 462 dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE);
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H A D | vlv_dsi_pll.c | 308 intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0); 558 intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE); 586 intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); 588 intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);
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H A D | intel_pmdemand.c | 97 intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); 456 intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0), 459 intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, 561 intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
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H A D | g4x_hdmi.c | 249 intel_de_rmw(i915, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE); 267 intel_de_rmw(i915, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0); 352 intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), 369 intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),
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H A D | intel_hotplug_irq.c | 997 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, 1006 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, 1013 intel_de_rmw(i915, SHOTPLUG_CTL_TC, 1022 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, 1038 intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val); 1093 intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin), 1132 intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs, 1369 intel_de_rmw(i915, PEG_BAND_GAP_DATA, 0xf, 0xd);
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H A D | intel_dsi_vbt.c | 346 intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI, 356 intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON, 363 intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE, 370 intel_de_rmw(dev_priv, GPIO(dev_priv, index), 379 intel_de_rmw(dev_priv, GPIO(dev_priv, index),
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H A D | intel_cx0_phy.c | 80 intel_de_rmw(i915, 120 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane), 2461 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2483 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), 2519 intel_de_rmw(i915, buf_ctl2_reg, 2534 intel_de_rmw(i915, buf_ctl2_reg, 2548 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), 2551 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port), 2603 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 2612 intel_de_rmw(i91 [all...] |
H A D | intel_lvds.c | 322 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); 324 intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON); 342 intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0); 347 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0);
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