Searched refs:hws (Results 1 - 25 of 246) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn303/
H A Ddcn303_hwseq.c37 hws->ctx
39 hws->regs->reg
43 hws->shifts->field_name, hws->masks->field_name
46 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
51 void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) argument
56 void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) argument
61 void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) argument
H A Ddcn303_hwseq.h32 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
33 void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
34 void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
35 void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
/linux-master/drivers/clk/imx/
H A Dclk-imx6sx.c85 static struct clk_hw **hws; variable in typeref:struct:clk_hw
126 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
132 hws = clk_hw_data->hws;
134 hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
136 hws[IMX6SX_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");
137 hws[IMX6SX_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc");
140 hws[IMX6SX_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0");
141 hws[IMX6SX_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1");
144 hws[IMX6SX_CLK_ANACLK
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H A Dclk-imx6ul.c72 static struct clk_hw **hws; variable in typeref:struct:clk_hw
133 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
139 hws = clk_hw_data->hws;
141 hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
143 hws[IMX6UL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");
144 hws[IMX6UL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc");
147 hws[IMX6UL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0");
148 hws[IMX6UL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1");
155 hws[IMX6UL_PLL1_BYPASS_SR
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H A Dclk-imx6sll.c56 static struct clk_hw **hws; variable in typeref:struct:clk_hw
84 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
90 hws = clk_hw_data->hws;
92 hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
94 hws[IMX6SLL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");
95 hws[IMX6SLL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc");
98 hws[IMX6SLL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0");
99 hws[IMX6SLL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1");
115 hws[IMX6SLL_PLL1_BYPASS_SR
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H A Dclk-imx8mq.c282 static struct clk_hw **hws; variable in typeref:struct:clk_hw
291 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MQ_CLK_END), GFP_KERNEL);
296 hws = clk_hw_data->hws;
298 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
299 hws[IMX8MQ_CLK_32K] = imx_get_clk_hw_by_name(np, "ckil");
300 hws[IMX8MQ_CLK_25M] = imx_get_clk_hw_by_name(np, "osc_25m");
301 hws[IMX8MQ_CLK_27M] = imx_get_clk_hw_by_name(np, "osc_27m");
302 hws[IMX8MQ_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
303 hws[IMX8MQ_CLK_EXT
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H A Dclk-imx8mp.c405 static struct clk_hw **hws; variable in typeref:struct:clk_hw
426 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL);
431 hws = clk_hw_data->hws;
433 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
434 hws[IMX8MP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
435 hws[IMX8MP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
436 hws[IMX8MP_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
437 hws[IMX8MP_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
438 hws[IMX8MP_CLK_EXT
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H A Dclk-imx8mm.c297 static struct clk_hw **hws; variable in typeref:struct:clk_hw
306 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
312 hws = clk_hw_data->hws;
314 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
315 hws[IMX8MM_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
316 hws[IMX8MM_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
317 hws[IMX8MM_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
318 hws[IMX8MM_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
319 hws[IMX8MM_CLK_EXT
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H A Dclk-imx7d.c377 static struct clk_hw **hws; variable in typeref:struct:clk_hw
385 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
391 hws = clk_hw_data->hws;
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
394 hws[IMX7D_OSC_24M_CLK] = imx_get_clk_hw_by_name(ccm_node, "osc");
395 hws[IMX7D_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");
402 hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
403 hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
404 hws[IMX7D_PLL_SYS_MAIN_SR
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H A Dclk-imx7ulp.c49 struct clk_hw **hws; local
52 clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SCG1_END),
58 hws = clk_data->hws;
60 hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
62 hws[IMX7ULP_CLK_ROSC] = imx_get_clk_hw_by_name(np, "rosc");
63 hws[IMX7ULP_CLK_SOSC] = imx_get_clk_hw_by_name(np, "sosc");
64 hws[IMX7ULP_CLK_SIRC] = imx_get_clk_hw_by_name(np, "sirc");
65 hws[IMX7ULP_CLK_FIRC] = imx_get_clk_hw_by_name(np, "firc");
66 hws[IMX7ULP_CLK_UPL
138 struct clk_hw **hws; local
186 struct clk_hw **hws; local
233 struct clk_hw **hws; local
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H A Dclk-imx8mn.c317 static struct clk_hw **hws; variable in typeref:struct:clk_hw
326 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
332 hws = clk_hw_data->hws;
334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
335 hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
336 hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
337 hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
338 hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
339 hws[IMX8MN_CLK_EXT
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H A Dclk-imxrt1050.c33 static struct clk_hw **hws; variable in typeref:struct:clk_hw
45 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
51 hws = clk_hw_data->hws;
53 hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, "osc");
64 hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL);
66 hws[IMXRT1050_CLK_PLL1_REF_SEL] = imx_clk_hw_mux("pll1_arm_ref_sel",
68 hws[IMXRT1050_CLK_PLL2_REF_SEL] = imx_clk_hw_mux("pll2_sys_ref_sel",
70 hws[IMXRT1050_CLK_PLL3_REF_SEL] = imx_clk_hw_mux("pll3_usb_otg_ref_sel",
72 hws[IMXRT1050_CLK_PLL5_REF_SE
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H A Dclk-imx6q.c93 static struct clk_hw **hws; variable in typeref:struct:clk_hw
275 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk,
276 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
350 (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
351 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) {
403 if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
404 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)
442 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
448 hws = clk_hw_data->hws;
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H A Dclk-imx6sl.c100 static struct clk_hw **hws; variable in typeref:struct:clk_hw
188 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
194 hws = clk_hw_data->hws;
196 hws[IMX6SL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
197 hws[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock_hw("ckil", 0);
198 hws[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock_hw("osc", 0);
200 hws[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock_hw("anaclk1", 0);
208 hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
209 hws[IMX6SL_PLL2_BYPASS_SR
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.h31 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
32 void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
33 void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn301/
H A Ddcn301_hwseq.c34 hws->ctx
36 hws->regs->reg
40 hws->shifts->field_name, hws->masks->field_name
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce120/
H A Ddce120_hwseq.h34 bool dce121_xgmi_enabled(struct dce_hwseq *hws);
/linux-master/drivers/clk/nuvoton/
H A Dclk-ma35d1.c464 static struct clk_hw **hws; local
470 struct_size(ma35d1_hw_data, hws, CLK_MAX_IDX),
476 hws = ma35d1_hw_data->hws;
488 hws[HXT] = ma35d1_clk_fixed("hxt", 24000000);
489 hws[HXT_GATE] = ma35d1_clk_gate(dev, "hxt_gate", "hxt",
491 hws[LXT] = ma35d1_clk_fixed("lxt", 32768);
492 hws[LXT_GATE] = ma35d1_clk_gate(dev, "lxt_gate", "lxt",
494 hws[HIRC] = ma35d1_clk_fixed("hirc", 12000000);
495 hws[HIRC_GAT
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.h36 void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
38 void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
44 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
46 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.h36 struct dce_hwseq *hws,
41 struct dce_hwseq *hws,
49 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
50 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);
57 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
/linux-master/drivers/clk/x86/
H A Dclk-fch.c38 static struct clk_hw *hws[ST_MAX_CLKS]; variable in typeref:struct:clk_hw
61 hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
63 hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
66 hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
71 clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
73 hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
77 devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],
80 hws[CLK_48M_FIXED] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
83 hws[CLK_GATE_FIXE
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/linux-master/drivers/clk/meson/
H A Dmeson-clkc-utils.h13 struct clk_hw **hws; member in struct:meson_clk_hw_data
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c32 hws->ctx
34 hws->regs->reg
38 hws->shifts->field_name, hws->masks->field_name
40 void dce_enable_fe_clock(struct dce_hwseq *hws, argument
53 struct dce_hwseq *hws = dc->hwseq; local
75 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
80 if (hws->wa.blnd_crtc_trigger) {
97 void dce_set_blender_mode(struct dce_hwseq *hws, argument
129 if (hws
138 dce_disable_sram_shut_down(struct dce_hwseq *hws) argument
145 dce_underlay_clock_enable(struct dce_hwseq *hws) argument
163 dce_clock_gating_power_up(struct dce_hwseq *hws, bool enable) argument
175 dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst) argument
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/linux-master/drivers/clk/bcm/
H A Dclk-bcm2711-dvp.c38 struct_size(dvp->data, hws, NR_CLOCKS),
59 data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev,
65 if (IS_ERR(data->hws[0]))
66 return PTR_ERR(data->hws[0]);
68 data->hws[1] = clk_hw_register_gate_parent_data(&pdev->dev,
74 if (IS_ERR(data->hws[1])) {
75 ret = PTR_ERR(data->hws[1]);
88 clk_hw_unregister_gate(data->hws[1]);
91 clk_hw_unregister_gate(data->hws[0]);
100 clk_hw_unregister_gate(data->hws[
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/linux-master/drivers/isdn/hardware/mISDN/
H A Diohelper.h25 #define IOFUNC_IO(name, hws, ap) \
27 struct hws *hw = p; \
31 struct hws *hw = p; \
35 struct hws *hw = p; \
39 struct hws *hw = p; \
43 #define IOFUNC_IND(name, hws, ap) \
45 struct hws *hw = p; \
50 struct hws *hw = p; \
55 struct hws *hw = p; \
60 struct hws *h
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