History log of /linux-master/drivers/clk/nuvoton/clk-ma35d1.c
Revision Date Author Comments
# 257cb9f2 05-Jul-2023 Yangtao Li <frank.li@vivo.com>

clk: nuvoton: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-12-frank.li@vivo.com
Acked-by: Jacky Huang <ychuang3@nuvoton.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>


# f50a000b 22-Jun-2023 Jacky Huang <ychuang3@nuvoton.com>

clk: nuvoton: Use clk_parent_data instead of string for parent clock

For the declaration of parent clocks, use struct clk_parent_data instead
of a string. Due to the change in the passed arguments, replace the usage
of devm_clk_hw_register_mux() with clk_hw_register_mux_parent_data() for
all cases.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>


# ebd617b6 22-Jun-2023 Jacky Huang <ychuang3@nuvoton.com>

clk: nuvoton: Update all constant hex values to lowercase

The constant hex values used to define register offsets were written
in uppercase. This patch update all these constant hex values to
be lowercase.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>


# a5e3f372 22-Jun-2023 Jacky Huang <ychuang3@nuvoton.com>

clk: nuvoton: Add clk-ma35d1.h for driver extern functions

Moved the declaration of extern functions ma35d1_reg_clk_pll() and
ma35d1_reg_adc_clkdiv() from the .c files to the newly created header
file clk-ma35d1.h.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>


# 691521a3 04-Jun-2023 Jacky Huang <ychuang3@nuvoton.com>

clk: nuvoton: Add clock driver for ma35d1 clock controller

The clock controller generates clocks for the whole chip, including
system clocks and all peripheral clocks. This driver support ma35d1
clock gating, divider, and individual PLL configuration.

There are 6 PLLs in ma35d1 SoC:
- CA-PLL for the two Cortex-A35 CPU clock
- SYS-PLL for system bus, which comes from the companion MCU
and cannot be programmed by clock controller.
- DDR-PLL for DDR
- EPLL for GMAC and GFX, Display, and VDEC IPs.
- VPLL for video output pixel clock
- APLL for SDHC, I2S audio, and other IPs.
CA-PLL has only one operation mode.
DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3
operation modes: integer mode, fraction mode, and spread specturm mode.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>