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f50a000b |
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22-Jun-2023 |
Jacky Huang <ychuang3@nuvoton.com> |
clk: nuvoton: Use clk_parent_data instead of string for parent clock For the declaration of parent clocks, use struct clk_parent_data instead of a string. Due to the change in the passed arguments, replace the usage of devm_clk_hw_register_mux() with clk_hw_register_mux_parent_data() for all cases. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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691521a3 |
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04-Jun-2023 |
Jacky Huang <ychuang3@nuvoton.com> |
clk: nuvoton: Add clock driver for ma35d1 clock controller The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. This driver support ma35d1 clock gating, divider, and individual PLL configuration. There are 6 PLLs in ma35d1 SoC: - CA-PLL for the two Cortex-A35 CPU clock - SYS-PLL for system bus, which comes from the companion MCU and cannot be programmed by clock controller. - DDR-PLL for DDR - EPLL for GMAC and GFX, Display, and VDEC IPs. - VPLL for video output pixel clock - APLL for SDHC, I2S audio, and other IPs. CA-PLL has only one operation mode. DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3 operation modes: integer mode, fraction mode, and spread specturm mode. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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