#
912d7af4 |
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21-Apr-2023 |
Alexander Stein <alexander.stein@ew.tq-group.com> |
clk: imx6ul: retain early UART clocks during kernel init Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230421115517.1940990-1-alexander.stein@ew.tq-group.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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#
f420f47e |
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10-Mar-2023 |
Oleksij Rempel <linux@rempel-privat.de> |
clk: imx6ul: fix "failed to get parent" error On some configuration we may get following error: [ 0.000000] imx:clk-gpr-mux: failed to get parent (-EINVAL) This happens if selector is configured to not supported value. To avoid this warnings add dummy parents for not supported values. Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/20230310164523.534571-1-o.rempel@pengutronix.de Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Reported-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
4e197ee8 |
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31-Jan-2023 |
Oleksij Rempel <linux@rempel-privat.de> |
clk: imx6ul: add ethernet refclock mux support Add ethernet refclock mux support and set it to internal clock by default. This configuration will not affect existing boards. clock tree before this patch: fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ after this patch: fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... `--<> enet1_ref_pad |- pll6_enet fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... `--<> enet2_ref_pad Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-17-o.rempel@pengutronix.de
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#
5f82bfce |
|
31-Jan-2023 |
Oleksij Rempel <linux@rempel-privat.de> |
clk: imx6ul: fix enet1 gate configuration According to the "i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root of PLL6. It is controlling ENET1 separately. So, instead of this picture (implementation before this patch): fec1 <- enet_ref (divider) <---------------------------, |- pll6_enet (gate) fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ we should have this one (after this patch): fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ With this fix, the RMII reference clock will be turned off, after setting network interface down on each separate interface (ip l s dev eth0 down). Which was not working before, on system with both FECs enabled. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de
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#
8178e245 |
|
13-Nov-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name() The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts. No functional changes intended. The replacements were made with the following command: grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g' Tested on a BSH SystemMaster (SMM) S2 board. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221113180839.1625832-1-dario.binacchi@amarulasolutions.com
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#
d1012253 |
|
27-Sep-2021 |
Stefan Riedmueller <s.riedmueller@phytec.de> |
clk: imx: imx6ul: Fix csi clk gate register According to the imx6ul Reference Manual the csi clk gate register is CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the csi clk gate which is the current setting. Tests have shown though that the correct csi clk gate register for the imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct register for both platforms. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Tested-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210927072857.3940880-2-s.riedmueller@phytec.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
2f9d6186 |
|
27-Sep-2021 |
Stefan Riedmueller <s.riedmueller@phytec.de> |
clk: imx: imx6ul: Move csi_sel mux to correct base register The csi_sel mux register is located in the CCM register base and not the CCM_ANALOG register base. So move it to the correct position in code. Otherwise changing the parent of the csi clock can lead to a complete system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely modified. Also remove the SET_RATE_PARENT flag since one possible supply for the csi_sel mux is the system PLL which we don't want to modify. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210927072857.3940880-1-s.riedmueller@phytec.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
d5b2b225 |
|
18-Mar-2020 |
Waibel Georg <Georg.Waibel@wiedemann-group.com> |
clk: imx: imx6ul: change flexcan clock to support CiA bitrates Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock frequency from 30MHz to 40MHz which allows to support all bitrates recommended by CiA. The patch sets CAN_CLK_SEL to 80MHz by changing its clock parent from CLK_PLL3_60M to CLK_PLL3_80M. The post-divider CAN_CLK_PODF is set to /2 by default which makes 40MHz CAN_CLK_ROOT from its parent CAN_CLK_SEL. Background: CAN in Automation document 102 (CiA102) recommends the CAN bitrates 10, 20, 50, 125, 250, 500, 800 and 1000kbit/s. With the flexcan serial clock at 30MHz (original value) setting some common bitrates ("ip link set canX type can bitrate <bitrate>") gives the following results: requested value / actually set value 5000: bitrate 5000 sample-point 0.708 10000: bitrate 10000 sample-point 0.866 20000: bitrate 20000 sample-point 0.866 40000: bitrate 40000 sample-point 0.866 50000: bitrate 50000 sample-point 0.866 80000: bitrate 80000 sample-point 0.866 100000: bitrate 100000 sample-point 0.866 125000: bitrate 125000 sample-point 0.875 250000: bitrate 250000 sample-point 0.866 400000: bitrate 400000 sample-point 0.866 500000: bitrate 500000 sample-point 0.866 666666: bitrate 666666 sample-point 0.800 800000: bitrate 789473 sample-point 0.789 !!!bitrate error 1.3% 1000000: bitrate 1000000 sample-point 0.733 With the flexcan serial clock at 40MHz (new value) we get this: 5000: no more possible 10000: bitrate 10000 sample-point 0.875 20000: bitrate 20000 sample-point 0.875 40000: bitrate 40000 sample-point 0.850 50000: bitrate 50000 sample-point 0.875 80000: bitrate 80000 sample-point 0.850 100000: bitrate 100000 sample-point 0.875 125000: bitrate 125000 sample-point 0.875 250000: bitrate 250000 sample-point 0.875 400000: bitrate 400000 sample-point 0.850 500000: bitrate 500000 sample-point 0.875 666666: bitrate 666666 sample-point 0.800 800000: bitrate 800000 sample-point 0.800 1000000: bitrate 1000000 sample-point 0.750 A drawback of the modification is that 5kbit/s is no more supported. Setting the flexcan serial clock to 60MHz or 80MHz would produce similar results but with losing even more bitrates at the lower end. Changing the flexcan serial clock to 40MHz might apply for other SoCs using the flaxcan module as well (e.g. imx6q/d/s..). But since I don't have such hardware to test I did not add this to the patch. Signed-off-by: Georg Waibel <georg.waibel@wiedemann-group.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
8f5d4819 |
|
23-Oct-2019 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
1df37992 |
|
01-Jul-2019 |
Stephen Rothwell <sfr@canb.auug.org.au> |
clk: consoldiate the __clk_get_hw() declarations Without this we were getting errors like: In file included from drivers/clk/clkdev.c:22:0: drivers/clk/clk.h:36:23: error: static declaration of '__clk_get_hw' follows non-static declaration include/linux/clk-provider.h:808:16: note: previous declaration of '__clk_get_hw' was here Fixes: 59fcdce425b7 ("clk: Remove ifdef for COMMON_CLK in clk-provider.h") fixes: 73e0e496afda ("clkdev: Always allocate a struct clk and call __clk_get() w/ CCF") Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
1487b60d |
|
28-May-2019 |
Abel Vesa <abel.vesa@nxp.com> |
clk: imx6ul: Switch to clk_hw based API Switch the entire clk-imx6ul driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
fcaf2036 |
|
27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 159 Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
52f93ab8 |
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20-May-2019 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: keep the mmdc p1 ipg clock always on on 6sx/ul/ull/sll The MMDC_P1_IPG clock need to be on always on to make sure the MMDC register can be accessed successfully. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
c129b6fe |
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12-May-2019 |
Anson Huang <anson.huang@nxp.com> |
clk: imx: Use imx_mmdc_mask_handshake() API for masking MMDC channel Use imx_mmdc_mask_handshake() API instead of programming CCM register directly in each platform to mask unused MMDC channel's handshake. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
acc4f98d |
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31-Aug-2018 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx6ul: add mmdc1 ipg clock i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
11177e7a |
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13-Jul-2018 |
Nicholas Mc Guire <hofrat@osadl.org> |
clk: imx6ul: fix missing of_node_put() of_find_compatible_node() is returning a device node with refcount incremented and must be explicitly decremented after the last use which is right after the us in of_iomap() here. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Fixes: 787b4271a6a0 ("clk: imx: add imx6ul clk tree support") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
4a2eaa8e |
|
03-Jun-2018 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx6ul: remove clks_init_on array Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. ARM clock is busy divider type which has the CLK_IS_CRITICAL flag set by default when registered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
debef195 |
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02-Jun-2018 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx6ul: add GPIO clock gates i.MX6UL has GPIO clock gates in CCM CCGR, add them into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
2e5be528 |
|
18-Apr-2018 |
Stefan Agner <stefan@agner.ch> |
clk: imx6ull: use OSC clock during AXI rate change On i.MX6 ULL using PLL3 seems to cause a freeze when setting the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux"), probably because the clock is now forced to be on. Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
f5a4670d |
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20-Apr-2018 |
Michael Trimarchi <michael@amarulasolutions.com> |
clk: imx: Add new clo01 and clo2 controlled by CCOSR osc->cko2_sel->cko2_podf->clk_cko2->clk_cko Example of usage to provide clock to the sgtl5000 codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6UL_CLK_OSC>; #sound-dai-cells = <0>; clocks = <&clks IMX6UL_CLK_CKO>; assigned-clocks = <&clks IMX6UL_CLK_CKO2_SEL>, <&clks IMX6UL_CLK_CKO2_PODF>, <&clks IMX6UL_CLK_CKO2>, <&clks IMX6UL_CLK_CKO>; assigned-clock-parents = <&clks IMX6UL_CLK_OSC>, <&clks IMX6UL_CLK_CKO2_SEL>, <&clks IMX6UL_CLK_CKO2_PODF>, <&clks IMX6UL_CLK_CKO2>; clock-names = "mclk"; wlf,shared-lrclk; Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Tested-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
a43e8683 |
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18-Apr-2018 |
Stefan Agner <stefan@agner.ch> |
clk: imx6ul: fix periph clk2 clock mux selection According to the data sheet the 3rd choice is the bypass clock of pll2. This should not have any effect in practice as this selection is not used currently. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
a5510399 |
|
12-Mar-2018 |
Leonard Crestez <leonard.crestez@nxp.com> |
clk: imx6ull: Add epdc_podf instead of sim_podf This is one of the differences between 6ul and 6ull: imx6ull has no sim but has epdc and this clock is redefined on the same bit. This can be verified in the Reference Manuals. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
7f218065 |
|
12-Oct-2017 |
Philipp Zabel <p.zabel@pengutronix.de> |
clk: imx: clk-imx6ul: allow lcdif_pre_sel to change parent rate Allowing the lcdif_pre_sel to propagate rate changes to its parent PLL allows more fine grained control over the LCDIF pixel clock rate. For example, the Innovision AT043TN24 LCD panel described in the imx6ul-14x14-evk device tree requires a 9 MHz pixel clock. Before this patch, the lcdif_pre_sel clock rate is fixed, and just setting the lcdif_pred and lcdif_podf dividers only allows to get as close as about 8.44 MHz: pll3 1 1 480000000 0 0 pll3_bypass 1 1 480000000 0 0 pll3_usb_otg 1 1 480000000 0 0 pll3_pfd1_540m 1 1 540000000 0 0 lcdif_pre_sel 1 1 540000000 0 0 lcdif_pred 1 1 67500000 0 0 lcdif_podf 1 1 8437500 0 0 lcdif_pix 1 1 8437500 0 0 Once lcdif_pre_sel is allowed to propagate rate requests to its parent, the actual pixel clock matches the requested value: pll3 1 1 480000000 0 0 pll3_bypass 1 1 480000000 0 0 pll3_usb_otg 1 1 480000000 0 0 pll3_pfd1_540m 1 1 288000000 0 0 lcdif_pre_sel 1 1 288000000 0 0 lcdif_pred 1 1 36000000 0 0 lcdif_podf 1 1 9000000 0 0 lcdif_pix 1 1 9000000 0 0 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
fdda6ee9 |
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27-Aug-2017 |
Arvind Yadav <arvind.yadav.cs@gmail.com> |
clk: imx: constify clk_div_table clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
19057195 |
|
06-Mar-2017 |
Robin van der Gracht <robin@protonic.nl> |
clk: imx: correct uart4_serial clock name in driver for i.MX6UL Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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#
cf091ee9 |
|
03-Mar-2017 |
Robin van der Gracht <robin@protonic.nl> |
clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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#
73cd5e53 |
|
14-Nov-2016 |
Bai Ping <ping.bai@nxp.com> |
clk: imx: clk-imx6ul: add clk support for imx6ull imx6ull is the derived SoC from imx6ul Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
bfa10f7d |
|
13-Jun-2016 |
Dong Aisheng <aisheng.dong@nxp.com> |
clk: imx6ul: fix gpt2 clock names fix gpt2 clock names Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
f83d3163 |
|
08-Jun-2016 |
Dong Aisheng <aisheng.dong@nxp.com> |
clk: imx: fix pll clock parents pllx_bypass_src mux shouldn't be the parent of pllx clock since it's only valid when when pllx BYPASS bit is set. Thus it is actually one parent of pllx_bypass only. Instead, pllx parent should be fixed to osc according to reference manual. Other plls have the same issue. e.g. before fix, the pll tree is: osc 6 6 24000000 0 0 pll1_bypass_src 0 0 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 After the fix, it's: osc 6 6 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
f6c3aec2 |
|
12-Jan-2016 |
Lothar Waßmann <LW@KARO-electronics.de> |
clk: imx: add kpp clock for i.MX6UL Add the necessary clock to use the KPP interface on i.MX6UL. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
9797d819 |
|
12-Jan-2016 |
Lothar Waßmann <LW@KARO-electronics.de> |
clk: imx: whitespace cleanup; no functional change remove whitespace before TAB. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
81a467ef |
|
17-Feb-2016 |
Anatolij Gustschin <agust@denx.de> |
clk: imx: correct pwm7 clock name in driver for i.MX6UL Don't capitalize p in the pwm7 clock name. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
31cbb57d |
|
25-Nov-2015 |
Bai Ping <b51503@freescale.com> |
clk: imx: Replace clk error check with imx_check_clocks() As we already have a 'imx_check_clocks' to do the clock error check, so cleanup the error check code. Signed-off-by: Bai Ping <b51503@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
8efaf5ed |
|
06-Aug-2015 |
Anson Huang <b20788@freescale.com> |
clk: imx: increase AXI clock rate to 264MHz for i.MX6UL On i.MX6UL, AXI clock rate's design target is 264MHz, but by default it is only set to 198MHz which is NOT good enough for performance, this patch increases AXI clock rate from 198MHz to 264MHz to meet the design target, this is done by switching its parent clock "periph" from 396MHz PFD to 528MHz PLL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
#
787b4271 |
|
09-Jul-2015 |
Frank Li <Frank.Li@freescale.com> |
clk: imx: add imx6ul clk tree support Add imx6ul clock driver support. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Bai Ping <b51503@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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