1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2023 Nuvoton Technology Corp. 4 * Author: Chi-Fang Li <cfli0@nuvoton.com> 5 */ 6 7#include <linux/clk-provider.h> 8#include <linux/mfd/syscon.h> 9#include <linux/module.h> 10#include <linux/of.h> 11#include <linux/platform_device.h> 12#include <linux/spinlock.h> 13#include <dt-bindings/clock/nuvoton,ma35d1-clk.h> 14 15#include "clk-ma35d1.h" 16 17static DEFINE_SPINLOCK(ma35d1_lock); 18 19#define PLL_MAX_NUM 5 20 21/* Clock Control Registers Offset */ 22#define REG_CLK_PWRCTL 0x00 23#define REG_CLK_SYSCLK0 0x04 24#define REG_CLK_SYSCLK1 0x08 25#define REG_CLK_APBCLK0 0x0c 26#define REG_CLK_APBCLK1 0x10 27#define REG_CLK_APBCLK2 0x14 28#define REG_CLK_CLKSEL0 0x18 29#define REG_CLK_CLKSEL1 0x1c 30#define REG_CLK_CLKSEL2 0x20 31#define REG_CLK_CLKSEL3 0x24 32#define REG_CLK_CLKSEL4 0x28 33#define REG_CLK_CLKDIV0 0x2c 34#define REG_CLK_CLKDIV1 0x30 35#define REG_CLK_CLKDIV2 0x34 36#define REG_CLK_CLKDIV3 0x38 37#define REG_CLK_CLKDIV4 0x3c 38#define REG_CLK_CLKOCTL 0x40 39#define REG_CLK_STATUS 0x50 40#define REG_CLK_PLL0CTL0 0x60 41#define REG_CLK_PLL2CTL0 0x80 42#define REG_CLK_PLL2CTL1 0x84 43#define REG_CLK_PLL2CTL2 0x88 44#define REG_CLK_PLL3CTL0 0x90 45#define REG_CLK_PLL3CTL1 0x94 46#define REG_CLK_PLL3CTL2 0x98 47#define REG_CLK_PLL4CTL0 0xa0 48#define REG_CLK_PLL4CTL1 0xa4 49#define REG_CLK_PLL4CTL2 0xa8 50#define REG_CLK_PLL5CTL0 0xb0 51#define REG_CLK_PLL5CTL1 0xb4 52#define REG_CLK_PLL5CTL2 0xb8 53#define REG_CLK_CLKDCTL 0xc0 54#define REG_CLK_CLKDSTS 0xc4 55#define REG_CLK_CDUPB 0xc8 56#define REG_CLK_CDLOWB 0xcc 57#define REG_CLK_CKFLTRCTL 0xd0 58#define REG_CLK_TESTCLK 0xf0 59#define REG_CLK_PLLCTL 0x40 60 61#define PLL_MODE_INT 0 62#define PLL_MODE_FRAC 1 63#define PLL_MODE_SS 2 64 65static const struct clk_parent_data ca35clk_sel_clks[] = { 66 { .fw_name = "hxt", }, 67 { .fw_name = "capll", }, 68 { .fw_name = "ddrpll", }, 69}; 70 71static const struct clk_parent_data sysclk0_sel_clks[] = { 72 { .fw_name = "epll_div2", }, 73 { .fw_name = "syspll", }, 74}; 75 76static const struct clk_parent_data sysclk1_sel_clks[] = { 77 { .fw_name = "hxt", }, 78 { .fw_name = "syspll", }, 79}; 80 81static const struct clk_parent_data axiclk_sel_clks[] = { 82 { .fw_name = "capll_div2", }, 83 { .fw_name = "capll_div4", }, 84}; 85 86static const struct clk_parent_data ccap_sel_clks[] = { 87 { .fw_name = "hxt", }, 88 { .fw_name = "vpll", }, 89 { .fw_name = "apll", }, 90 { .fw_name = "syspll", }, 91}; 92 93static const struct clk_parent_data sdh_sel_clks[] = { 94 { .fw_name = "syspll", }, 95 { .fw_name = "apll", }, 96}; 97 98static const struct clk_parent_data dcu_sel_clks[] = { 99 { .fw_name = "epll_div2", }, 100 { .fw_name = "syspll", }, 101}; 102 103static const struct clk_parent_data gfx_sel_clks[] = { 104 { .fw_name = "epll", }, 105 { .fw_name = "syspll", }, 106}; 107 108static const struct clk_parent_data dbg_sel_clks[] = { 109 { .fw_name = "hirc", }, 110 { .fw_name = "syspll", }, 111}; 112 113static const struct clk_parent_data timer0_sel_clks[] = { 114 { .fw_name = "hxt", }, 115 { .fw_name = "lxt", }, 116 { .fw_name = "pclk0", }, 117 { .index = -1, }, 118 { .index = -1, }, 119 { .fw_name = "lirc", }, 120 { .index = -1, }, 121 { .fw_name = "hirc", }, 122}; 123 124static const struct clk_parent_data timer1_sel_clks[] = { 125 { .fw_name = "hxt", }, 126 { .fw_name = "lxt", }, 127 { .fw_name = "pclk0", }, 128 { .index = -1, }, 129 { .index = -1, }, 130 { .fw_name = "lirc", }, 131 { .index = -1, }, 132 { .fw_name = "hirc", }, 133}; 134 135static const struct clk_parent_data timer2_sel_clks[] = { 136 { .fw_name = "hxt", }, 137 { .fw_name = "lxt", }, 138 { .fw_name = "pclk1", }, 139 { .index = -1, }, 140 { .index = -1, }, 141 { .fw_name = "lirc", }, 142 { .index = -1, }, 143 { .fw_name = "hirc", }, 144}; 145 146static const struct clk_parent_data timer3_sel_clks[] = { 147 { .fw_name = "hxt", }, 148 { .fw_name = "lxt", }, 149 { .fw_name = "pclk1", }, 150 { .index = -1, }, 151 { .index = -1, }, 152 { .fw_name = "lirc", }, 153 { .index = -1, }, 154 { .fw_name = "hirc", }, 155}; 156 157static const struct clk_parent_data timer4_sel_clks[] = { 158 { .fw_name = "hxt", }, 159 { .fw_name = "lxt", }, 160 { .fw_name = "pclk2", }, 161 { .index = -1, }, 162 { .index = -1, }, 163 { .fw_name = "lirc", }, 164 { .index = -1, }, 165 { .fw_name = "hirc", }, 166}; 167 168static const struct clk_parent_data timer5_sel_clks[] = { 169 { .fw_name = "hxt", }, 170 { .fw_name = "lxt", }, 171 { .fw_name = "pclk2", }, 172 { .index = -1, }, 173 { .index = -1, }, 174 { .fw_name = "lirc", }, 175 { .index = -1, }, 176 { .fw_name = "hirc", }, 177}; 178 179static const struct clk_parent_data timer6_sel_clks[] = { 180 { .fw_name = "hxt", }, 181 { .fw_name = "lxt", }, 182 { .fw_name = "pclk0", }, 183 { .index = -1, }, 184 { .index = -1, }, 185 { .fw_name = "lirc", }, 186 { .index = -1, }, 187 { .fw_name = "hirc", }, 188}; 189 190static const struct clk_parent_data timer7_sel_clks[] = { 191 { .fw_name = "hxt", }, 192 { .fw_name = "lxt", }, 193 { .fw_name = "pclk0", }, 194 { .index = -1, }, 195 { .index = -1, }, 196 { .fw_name = "lirc", }, 197 { .index = -1, }, 198 { .fw_name = "hirc", }, 199}; 200 201static const struct clk_parent_data timer8_sel_clks[] = { 202 { .fw_name = "hxt", }, 203 { .fw_name = "lxt", }, 204 { .fw_name = "pclk1", }, 205 { .index = -1, }, 206 { .index = -1, }, 207 { .fw_name = "lirc", }, 208 { .index = -1, }, 209 { .fw_name = "hirc", }, 210}; 211 212static const struct clk_parent_data timer9_sel_clks[] = { 213 { .fw_name = "hxt", }, 214 { .fw_name = "lxt", }, 215 { .fw_name = "pclk1", }, 216 { .index = -1, }, 217 { .index = -1, }, 218 { .fw_name = "lirc", }, 219 { .index = -1, }, 220 { .fw_name = "hirc", }, 221}; 222 223static const struct clk_parent_data timer10_sel_clks[] = { 224 { .fw_name = "hxt", }, 225 { .fw_name = "lxt", }, 226 { .fw_name = "pclk2", }, 227 { .index = -1, }, 228 { .index = -1, }, 229 { .fw_name = "lirc", }, 230 { .index = -1, }, 231 { .fw_name = "hirc", }, 232}; 233 234static const struct clk_parent_data timer11_sel_clks[] = { 235 { .fw_name = "hxt", }, 236 { .fw_name = "lxt", }, 237 { .fw_name = "pclk2", }, 238 { .index = -1, }, 239 { .index = -1, }, 240 { .fw_name = "lirc", }, 241 { .index = -1, }, 242 { .fw_name = "hirc", }, 243}; 244 245static const struct clk_parent_data uart_sel_clks[] = { 246 { .fw_name = "hxt", }, 247 { .fw_name = "sysclk1_div2", }, 248}; 249 250static const struct clk_parent_data wdt0_sel_clks[] = { 251 { .index = -1, }, 252 { .fw_name = "lxt", }, 253 { .fw_name = "pclk3_div4096", }, 254 { .fw_name = "lirc", }, 255}; 256 257static const struct clk_parent_data wdt1_sel_clks[] = { 258 { .index = -1, }, 259 { .fw_name = "lxt", }, 260 { .fw_name = "pclk3_div4096", }, 261 { .fw_name = "lirc", }, 262}; 263 264static const struct clk_parent_data wdt2_sel_clks[] = { 265 { .index = -1, }, 266 { .fw_name = "lxt", }, 267 { .fw_name = "pclk4_div4096", }, 268 { .fw_name = "lirc", }, 269}; 270 271static const struct clk_parent_data wwdt0_sel_clks[] = { 272 { .index = -1, }, 273 { .index = -1, }, 274 { .fw_name = "pclk3_div4096", }, 275 { .fw_name = "lirc", }, 276}; 277 278static const struct clk_parent_data wwdt1_sel_clks[] = { 279 { .index = -1, }, 280 { .index = -1, }, 281 { .fw_name = "pclk3_div4096", }, 282 { .fw_name = "lirc", }, 283}; 284 285static const struct clk_parent_data wwdt2_sel_clks[] = { 286 { .index = -1, }, 287 { .index = -1, }, 288 { .fw_name = "pclk4_div4096", }, 289 { .fw_name = "lirc", }, 290}; 291 292static const struct clk_parent_data spi0_sel_clks[] = { 293 { .fw_name = "pclk1", }, 294 { .fw_name = "apll", }, 295}; 296 297static const struct clk_parent_data spi1_sel_clks[] = { 298 { .fw_name = "pclk2", }, 299 { .fw_name = "apll", }, 300}; 301 302static const struct clk_parent_data spi2_sel_clks[] = { 303 { .fw_name = "pclk1", }, 304 { .fw_name = "apll", }, 305}; 306 307static const struct clk_parent_data spi3_sel_clks[] = { 308 { .fw_name = "pclk2", }, 309 { .fw_name = "apll", }, 310}; 311 312static const struct clk_parent_data qspi0_sel_clks[] = { 313 { .fw_name = "pclk0", }, 314 { .fw_name = "apll", }, 315}; 316 317static const struct clk_parent_data qspi1_sel_clks[] = { 318 { .fw_name = "pclk0", }, 319 { .fw_name = "apll", }, 320}; 321 322static const struct clk_parent_data i2s0_sel_clks[] = { 323 { .fw_name = "apll", }, 324 { .fw_name = "sysclk1_div2", }, 325}; 326 327static const struct clk_parent_data i2s1_sel_clks[] = { 328 { .fw_name = "apll", }, 329 { .fw_name = "sysclk1_div2", }, 330}; 331 332static const struct clk_parent_data can_sel_clks[] = { 333 { .fw_name = "apll", }, 334 { .fw_name = "vpll", }, 335}; 336 337static const struct clk_parent_data cko_sel_clks[] = { 338 { .fw_name = "hxt", }, 339 { .fw_name = "lxt", }, 340 { .fw_name = "hirc", }, 341 { .fw_name = "lirc", }, 342 { .fw_name = "capll_div4", }, 343 { .fw_name = "syspll", }, 344 { .fw_name = "ddrpll", }, 345 { .fw_name = "epll_div2", }, 346 { .fw_name = "apll", }, 347 { .fw_name = "vpll", }, 348}; 349 350static const struct clk_parent_data smc_sel_clks[] = { 351 { .fw_name = "hxt", }, 352 { .fw_name = "pclk4", }, 353}; 354 355static const struct clk_parent_data kpi_sel_clks[] = { 356 { .fw_name = "hxt", }, 357 { .fw_name = "lxt", }, 358}; 359 360static const struct clk_div_table ip_div_table[] = { 361 {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, 362 {5, 12}, {6, 14}, {7, 16}, {0, 0}, 363}; 364 365static const struct clk_div_table eadc_div_table[] = { 366 {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, 367 {5, 12}, {6, 14}, {7, 16}, {8, 18}, 368 {9, 20}, {10, 22}, {11, 24}, {12, 26}, 369 {13, 28}, {14, 30}, {15, 32}, {0, 0}, 370}; 371 372static struct clk_hw *ma35d1_clk_fixed(const char *name, int rate) 373{ 374 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); 375} 376 377static struct clk_hw *ma35d1_clk_mux_parent(struct device *dev, const char *name, 378 void __iomem *reg, u8 shift, u8 width, 379 const struct clk_parent_data *pdata, 380 int num_pdata) 381{ 382 return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, 383 CLK_SET_RATE_NO_REPARENT, reg, shift, 384 width, 0, &ma35d1_lock); 385} 386 387static struct clk_hw *ma35d1_clk_mux(struct device *dev, const char *name, 388 void __iomem *reg, u8 shift, u8 width, 389 const struct clk_parent_data *pdata, 390 int num_pdata) 391{ 392 return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, 393 CLK_SET_RATE_NO_REPARENT, reg, shift, 394 width, 0, &ma35d1_lock); 395} 396 397static struct clk_hw *ma35d1_clk_divider(struct device *dev, const char *name, 398 const char *parent, void __iomem *reg, 399 u8 shift, u8 width) 400{ 401 return devm_clk_hw_register_divider(dev, name, parent, CLK_SET_RATE_PARENT, 402 reg, shift, width, 0, &ma35d1_lock); 403} 404 405static struct clk_hw *ma35d1_clk_divider_pow2(struct device *dev, const char *name, 406 const char *parent, void __iomem *reg, 407 u8 shift, u8 width) 408{ 409 return devm_clk_hw_register_divider(dev, name, parent, 410 CLK_DIVIDER_POWER_OF_TWO, reg, shift, 411 width, 0, &ma35d1_lock); 412} 413 414static struct clk_hw *ma35d1_clk_divider_table(struct device *dev, const char *name, 415 const char *parent, void __iomem *reg, 416 u8 shift, u8 width, 417 const struct clk_div_table *table) 418{ 419 return devm_clk_hw_register_divider_table(dev, name, parent, 0, 420 reg, shift, width, 0, 421 table, &ma35d1_lock); 422} 423 424static struct clk_hw *ma35d1_clk_fixed_factor(struct device *dev, const char *name, 425 const char *parent, unsigned int mult, 426 unsigned int div) 427{ 428 return devm_clk_hw_register_fixed_factor(dev, name, parent, 429 CLK_SET_RATE_PARENT, mult, div); 430} 431 432static struct clk_hw *ma35d1_clk_gate(struct device *dev, const char *name, const char *parent, 433 void __iomem *reg, u8 shift) 434{ 435 return devm_clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, 436 reg, shift, 0, &ma35d1_lock); 437} 438 439static int ma35d1_get_pll_setting(struct device_node *clk_node, u32 *pllmode) 440{ 441 const char *of_str; 442 int i; 443 444 for (i = 0; i < PLL_MAX_NUM; i++) { 445 if (of_property_read_string_index(clk_node, "nuvoton,pll-mode", i, &of_str)) 446 return -EINVAL; 447 if (!strcmp(of_str, "integer")) 448 pllmode[i] = PLL_MODE_INT; 449 else if (!strcmp(of_str, "fractional")) 450 pllmode[i] = PLL_MODE_FRAC; 451 else if (!strcmp(of_str, "spread-spectrum")) 452 pllmode[i] = PLL_MODE_SS; 453 else 454 return -EINVAL; 455 } 456 return 0; 457} 458 459static int ma35d1_clocks_probe(struct platform_device *pdev) 460{ 461 struct device *dev = &pdev->dev; 462 struct device_node *clk_node = pdev->dev.of_node; 463 void __iomem *clk_base; 464 static struct clk_hw **hws; 465 static struct clk_hw_onecell_data *ma35d1_hw_data; 466 u32 pllmode[PLL_MAX_NUM]; 467 int ret; 468 469 ma35d1_hw_data = devm_kzalloc(dev, 470 struct_size(ma35d1_hw_data, hws, CLK_MAX_IDX), 471 GFP_KERNEL); 472 if (!ma35d1_hw_data) 473 return -ENOMEM; 474 475 ma35d1_hw_data->num = CLK_MAX_IDX; 476 hws = ma35d1_hw_data->hws; 477 478 clk_base = devm_platform_ioremap_resource(pdev, 0); 479 if (IS_ERR(clk_base)) 480 return PTR_ERR(clk_base); 481 482 ret = ma35d1_get_pll_setting(clk_node, pllmode); 483 if (ret < 0) { 484 dev_err(dev, "Invalid PLL setting!\n"); 485 return -EINVAL; 486 } 487 488 hws[HXT] = ma35d1_clk_fixed("hxt", 24000000); 489 hws[HXT_GATE] = ma35d1_clk_gate(dev, "hxt_gate", "hxt", 490 clk_base + REG_CLK_PWRCTL, 0); 491 hws[LXT] = ma35d1_clk_fixed("lxt", 32768); 492 hws[LXT_GATE] = ma35d1_clk_gate(dev, "lxt_gate", "lxt", 493 clk_base + REG_CLK_PWRCTL, 1); 494 hws[HIRC] = ma35d1_clk_fixed("hirc", 12000000); 495 hws[HIRC_GATE] = ma35d1_clk_gate(dev, "hirc_gate", "hirc", 496 clk_base + REG_CLK_PWRCTL, 2); 497 hws[LIRC] = ma35d1_clk_fixed("lirc", 32000); 498 hws[LIRC_GATE] = ma35d1_clk_gate(dev, "lirc_gate", "lirc", 499 clk_base + REG_CLK_PWRCTL, 3); 500 501 hws[CAPLL] = ma35d1_reg_clk_pll(dev, CAPLL, pllmode[0], "capll", 502 hws[HXT], clk_base + REG_CLK_PLL0CTL0); 503 hws[SYSPLL] = ma35d1_clk_fixed("syspll", 180000000); 504 hws[DDRPLL] = ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", 505 hws[HXT], clk_base + REG_CLK_PLL2CTL0); 506 hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", 507 hws[HXT], clk_base + REG_CLK_PLL3CTL0); 508 hws[EPLL] = ma35d1_reg_clk_pll(dev, EPLL, pllmode[3], "epll", 509 hws[HXT], clk_base + REG_CLK_PLL4CTL0); 510 hws[VPLL] = ma35d1_reg_clk_pll(dev, VPLL, pllmode[4], "vpll", 511 hws[HXT], clk_base + REG_CLK_PLL5CTL0); 512 513 hws[EPLL_DIV2] = ma35d1_clk_fixed_factor(dev, "epll_div2", "epll", 1, 2); 514 hws[EPLL_DIV4] = ma35d1_clk_fixed_factor(dev, "epll_div4", "epll", 1, 4); 515 hws[EPLL_DIV8] = ma35d1_clk_fixed_factor(dev, "epll_div8", "epll", 1, 8); 516 517 hws[CA35CLK_MUX] = ma35d1_clk_mux_parent(dev, "ca35clk_mux", 518 clk_base + REG_CLK_CLKSEL0, 0, 2, 519 ca35clk_sel_clks, 520 ARRAY_SIZE(ca35clk_sel_clks)); 521 hws[AXICLK_DIV2] = ma35d1_clk_fixed_factor(dev, "capll_div2", "ca35clk_mux", 1, 2); 522 hws[AXICLK_DIV4] = ma35d1_clk_fixed_factor(dev, "capll_div4", "ca35clk_mux", 1, 4); 523 524 hws[AXICLK_MUX] = ma35d1_clk_mux(dev, "axiclk_mux", clk_base + REG_CLK_CLKDIV0, 525 26, 1, axiclk_sel_clks, 526 ARRAY_SIZE(axiclk_sel_clks)); 527 hws[SYSCLK0_MUX] = ma35d1_clk_mux(dev, "sysclk0_mux", clk_base + REG_CLK_CLKSEL0, 528 2, 1, sysclk0_sel_clks, 529 ARRAY_SIZE(sysclk0_sel_clks)); 530 hws[SYSCLK1_MUX] = ma35d1_clk_mux(dev, "sysclk1_mux", clk_base + REG_CLK_CLKSEL0, 531 4, 1, sysclk1_sel_clks, 532 ARRAY_SIZE(sysclk1_sel_clks)); 533 hws[SYSCLK1_DIV2] = ma35d1_clk_fixed_factor(dev, "sysclk1_div2", "sysclk1_mux", 1, 2); 534 535 /* HCLK0~3 & PCLK0~4 */ 536 hws[HCLK0] = ma35d1_clk_fixed_factor(dev, "hclk0", "sysclk1_mux", 1, 1); 537 hws[HCLK1] = ma35d1_clk_fixed_factor(dev, "hclk1", "sysclk1_mux", 1, 1); 538 hws[HCLK2] = ma35d1_clk_fixed_factor(dev, "hclk2", "sysclk1_mux", 1, 1); 539 hws[PCLK0] = ma35d1_clk_fixed_factor(dev, "pclk0", "sysclk1_mux", 1, 1); 540 hws[PCLK1] = ma35d1_clk_fixed_factor(dev, "pclk1", "sysclk1_mux", 1, 1); 541 hws[PCLK2] = ma35d1_clk_fixed_factor(dev, "pclk2", "sysclk1_mux", 1, 1); 542 543 hws[HCLK3] = ma35d1_clk_fixed_factor(dev, "hclk3", "sysclk1_mux", 1, 2); 544 hws[PCLK3] = ma35d1_clk_fixed_factor(dev, "pclk3", "sysclk1_mux", 1, 2); 545 hws[PCLK4] = ma35d1_clk_fixed_factor(dev, "pclk4", "sysclk1_mux", 1, 2); 546 547 hws[USBPHY0] = ma35d1_clk_fixed("usbphy0", 480000000); 548 hws[USBPHY1] = ma35d1_clk_fixed("usbphy1", 480000000); 549 550 /* DDR */ 551 hws[DDR0_GATE] = ma35d1_clk_gate(dev, "ddr0_gate", "ddrpll", 552 clk_base + REG_CLK_SYSCLK0, 4); 553 hws[DDR6_GATE] = ma35d1_clk_gate(dev, "ddr6_gate", "ddrpll", 554 clk_base + REG_CLK_SYSCLK0, 5); 555 556 hws[CAN0_MUX] = ma35d1_clk_mux(dev, "can0_mux", clk_base + REG_CLK_CLKSEL4, 557 16, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); 558 hws[CAN0_DIV] = ma35d1_clk_divider_table(dev, "can0_div", "can0_mux", 559 clk_base + REG_CLK_CLKDIV0, 560 0, 3, ip_div_table); 561 hws[CAN0_GATE] = ma35d1_clk_gate(dev, "can0_gate", "can0_div", 562 clk_base + REG_CLK_SYSCLK0, 8); 563 hws[CAN1_MUX] = ma35d1_clk_mux(dev, "can1_mux", clk_base + REG_CLK_CLKSEL4, 564 17, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); 565 hws[CAN1_DIV] = ma35d1_clk_divider_table(dev, "can1_div", "can1_mux", 566 clk_base + REG_CLK_CLKDIV0, 567 4, 3, ip_div_table); 568 hws[CAN1_GATE] = ma35d1_clk_gate(dev, "can1_gate", "can1_div", 569 clk_base + REG_CLK_SYSCLK0, 9); 570 hws[CAN2_MUX] = ma35d1_clk_mux(dev, "can2_mux", clk_base + REG_CLK_CLKSEL4, 571 18, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); 572 hws[CAN2_DIV] = ma35d1_clk_divider_table(dev, "can2_div", "can2_mux", 573 clk_base + REG_CLK_CLKDIV0, 574 8, 3, ip_div_table); 575 hws[CAN2_GATE] = ma35d1_clk_gate(dev, "can2_gate", "can2_div", 576 clk_base + REG_CLK_SYSCLK0, 10); 577 hws[CAN3_MUX] = ma35d1_clk_mux(dev, "can3_mux", clk_base + REG_CLK_CLKSEL4, 578 19, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); 579 hws[CAN3_DIV] = ma35d1_clk_divider_table(dev, "can3_div", "can3_mux", 580 clk_base + REG_CLK_CLKDIV0, 581 12, 3, ip_div_table); 582 hws[CAN3_GATE] = ma35d1_clk_gate(dev, "can3_gate", "can3_div", 583 clk_base + REG_CLK_SYSCLK0, 11); 584 585 hws[SDH0_MUX] = ma35d1_clk_mux(dev, "sdh0_mux", clk_base + REG_CLK_CLKSEL0, 586 16, 2, sdh_sel_clks, ARRAY_SIZE(sdh_sel_clks)); 587 hws[SDH0_GATE] = ma35d1_clk_gate(dev, "sdh0_gate", "sdh0_mux", 588 clk_base + REG_CLK_SYSCLK0, 16); 589 hws[SDH1_MUX] = ma35d1_clk_mux(dev, "sdh1_mux", clk_base + REG_CLK_CLKSEL0, 590 18, 2, sdh_sel_clks, ARRAY_SIZE(sdh_sel_clks)); 591 hws[SDH1_GATE] = ma35d1_clk_gate(dev, "sdh1_gate", "sdh1_mux", 592 clk_base + REG_CLK_SYSCLK0, 17); 593 594 hws[NAND_GATE] = ma35d1_clk_gate(dev, "nand_gate", "hclk1", 595 clk_base + REG_CLK_SYSCLK0, 18); 596 597 hws[USBD_GATE] = ma35d1_clk_gate(dev, "usbd_gate", "usbphy0", 598 clk_base + REG_CLK_SYSCLK0, 19); 599 hws[USBH_GATE] = ma35d1_clk_gate(dev, "usbh_gate", "usbphy0", 600 clk_base + REG_CLK_SYSCLK0, 20); 601 hws[HUSBH0_GATE] = ma35d1_clk_gate(dev, "husbh0_gate", "usbphy0", 602 clk_base + REG_CLK_SYSCLK0, 21); 603 hws[HUSBH1_GATE] = ma35d1_clk_gate(dev, "husbh1_gate", "usbphy0", 604 clk_base + REG_CLK_SYSCLK0, 22); 605 606 hws[GFX_MUX] = ma35d1_clk_mux(dev, "gfx_mux", clk_base + REG_CLK_CLKSEL0, 607 26, 1, gfx_sel_clks, ARRAY_SIZE(gfx_sel_clks)); 608 hws[GFX_GATE] = ma35d1_clk_gate(dev, "gfx_gate", "gfx_mux", 609 clk_base + REG_CLK_SYSCLK0, 24); 610 hws[VC8K_GATE] = ma35d1_clk_gate(dev, "vc8k_gate", "sysclk0_mux", 611 clk_base + REG_CLK_SYSCLK0, 25); 612 hws[DCU_MUX] = ma35d1_clk_mux(dev, "dcu_mux", clk_base + REG_CLK_CLKSEL0, 613 24, 1, dcu_sel_clks, ARRAY_SIZE(dcu_sel_clks)); 614 hws[DCU_GATE] = ma35d1_clk_gate(dev, "dcu_gate", "dcu_mux", 615 clk_base + REG_CLK_SYSCLK0, 26); 616 hws[DCUP_DIV] = ma35d1_clk_divider_table(dev, "dcup_div", "vpll", 617 clk_base + REG_CLK_CLKDIV0, 618 16, 3, ip_div_table); 619 620 hws[EMAC0_GATE] = ma35d1_clk_gate(dev, "emac0_gate", "epll_div2", 621 clk_base + REG_CLK_SYSCLK0, 27); 622 hws[EMAC1_GATE] = ma35d1_clk_gate(dev, "emac1_gate", "epll_div2", 623 clk_base + REG_CLK_SYSCLK0, 28); 624 625 hws[CCAP0_MUX] = ma35d1_clk_mux(dev, "ccap0_mux", clk_base + REG_CLK_CLKSEL0, 626 12, 1, ccap_sel_clks, ARRAY_SIZE(ccap_sel_clks)); 627 hws[CCAP0_DIV] = ma35d1_clk_divider(dev, "ccap0_div", "ccap0_mux", 628 clk_base + REG_CLK_CLKDIV1, 8, 4); 629 hws[CCAP0_GATE] = ma35d1_clk_gate(dev, "ccap0_gate", "ccap0_div", 630 clk_base + REG_CLK_SYSCLK0, 29); 631 hws[CCAP1_MUX] = ma35d1_clk_mux(dev, "ccap1_mux", clk_base + REG_CLK_CLKSEL0, 632 14, 1, ccap_sel_clks, ARRAY_SIZE(ccap_sel_clks)); 633 hws[CCAP1_DIV] = ma35d1_clk_divider(dev, "ccap1_div", "ccap1_mux", 634 clk_base + REG_CLK_CLKDIV1, 635 12, 4); 636 hws[CCAP1_GATE] = ma35d1_clk_gate(dev, "ccap1_gate", "ccap1_div", 637 clk_base + REG_CLK_SYSCLK0, 30); 638 639 hws[PDMA0_GATE] = ma35d1_clk_gate(dev, "pdma0_gate", "hclk0", 640 clk_base + REG_CLK_SYSCLK1, 0); 641 hws[PDMA1_GATE] = ma35d1_clk_gate(dev, "pdma1_gate", "hclk0", 642 clk_base + REG_CLK_SYSCLK1, 1); 643 hws[PDMA2_GATE] = ma35d1_clk_gate(dev, "pdma2_gate", "hclk0", 644 clk_base + REG_CLK_SYSCLK1, 2); 645 hws[PDMA3_GATE] = ma35d1_clk_gate(dev, "pdma3_gate", "hclk0", 646 clk_base + REG_CLK_SYSCLK1, 3); 647 648 hws[WH0_GATE] = ma35d1_clk_gate(dev, "wh0_gate", "hclk0", 649 clk_base + REG_CLK_SYSCLK1, 4); 650 hws[WH1_GATE] = ma35d1_clk_gate(dev, "wh1_gate", "hclk0", 651 clk_base + REG_CLK_SYSCLK1, 5); 652 653 hws[HWS_GATE] = ma35d1_clk_gate(dev, "hws_gate", "hclk0", 654 clk_base + REG_CLK_SYSCLK1, 6); 655 656 hws[EBI_GATE] = ma35d1_clk_gate(dev, "ebi_gate", "hclk0", 657 clk_base + REG_CLK_SYSCLK1, 7); 658 659 hws[SRAM0_GATE] = ma35d1_clk_gate(dev, "sram0_gate", "hclk0", 660 clk_base + REG_CLK_SYSCLK1, 8); 661 hws[SRAM1_GATE] = ma35d1_clk_gate(dev, "sram1_gate", "hclk0", 662 clk_base + REG_CLK_SYSCLK1, 9); 663 664 hws[ROM_GATE] = ma35d1_clk_gate(dev, "rom_gate", "hclk0", 665 clk_base + REG_CLK_SYSCLK1, 10); 666 667 hws[TRA_GATE] = ma35d1_clk_gate(dev, "tra_gate", "hclk0", 668 clk_base + REG_CLK_SYSCLK1, 11); 669 670 hws[DBG_MUX] = ma35d1_clk_mux(dev, "dbg_mux", clk_base + REG_CLK_CLKSEL0, 671 27, 1, dbg_sel_clks, ARRAY_SIZE(dbg_sel_clks)); 672 hws[DBG_GATE] = ma35d1_clk_gate(dev, "dbg_gate", "hclk0", 673 clk_base + REG_CLK_SYSCLK1, 12); 674 675 hws[CKO_MUX] = ma35d1_clk_mux(dev, "cko_mux", clk_base + REG_CLK_CLKSEL4, 676 24, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks)); 677 hws[CKO_DIV] = ma35d1_clk_divider_pow2(dev, "cko_div", "cko_mux", 678 clk_base + REG_CLK_CLKOCTL, 0, 4); 679 hws[CKO_GATE] = ma35d1_clk_gate(dev, "cko_gate", "cko_div", 680 clk_base + REG_CLK_SYSCLK1, 13); 681 682 hws[GTMR_GATE] = ma35d1_clk_gate(dev, "gtmr_gate", "hirc", 683 clk_base + REG_CLK_SYSCLK1, 14); 684 685 hws[GPA_GATE] = ma35d1_clk_gate(dev, "gpa_gate", "hclk0", 686 clk_base + REG_CLK_SYSCLK1, 16); 687 hws[GPB_GATE] = ma35d1_clk_gate(dev, "gpb_gate", "hclk0", 688 clk_base + REG_CLK_SYSCLK1, 17); 689 hws[GPC_GATE] = ma35d1_clk_gate(dev, "gpc_gate", "hclk0", 690 clk_base + REG_CLK_SYSCLK1, 18); 691 hws[GPD_GATE] = ma35d1_clk_gate(dev, "gpd_gate", "hclk0", 692 clk_base + REG_CLK_SYSCLK1, 19); 693 hws[GPE_GATE] = ma35d1_clk_gate(dev, "gpe_gate", "hclk0", 694 clk_base + REG_CLK_SYSCLK1, 20); 695 hws[GPF_GATE] = ma35d1_clk_gate(dev, "gpf_gate", "hclk0", 696 clk_base + REG_CLK_SYSCLK1, 21); 697 hws[GPG_GATE] = ma35d1_clk_gate(dev, "gpg_gate", "hclk0", 698 clk_base + REG_CLK_SYSCLK1, 22); 699 hws[GPH_GATE] = ma35d1_clk_gate(dev, "gph_gate", "hclk0", 700 clk_base + REG_CLK_SYSCLK1, 23); 701 hws[GPI_GATE] = ma35d1_clk_gate(dev, "gpi_gate", "hclk0", 702 clk_base + REG_CLK_SYSCLK1, 24); 703 hws[GPJ_GATE] = ma35d1_clk_gate(dev, "gpj_gate", "hclk0", 704 clk_base + REG_CLK_SYSCLK1, 25); 705 hws[GPK_GATE] = ma35d1_clk_gate(dev, "gpk_gate", "hclk0", 706 clk_base + REG_CLK_SYSCLK1, 26); 707 hws[GPL_GATE] = ma35d1_clk_gate(dev, "gpl_gate", "hclk0", 708 clk_base + REG_CLK_SYSCLK1, 27); 709 hws[GPM_GATE] = ma35d1_clk_gate(dev, "gpm_gate", "hclk0", 710 clk_base + REG_CLK_SYSCLK1, 28); 711 hws[GPN_GATE] = ma35d1_clk_gate(dev, "gpn_gate", "hclk0", 712 clk_base + REG_CLK_SYSCLK1, 29); 713 714 hws[TMR0_MUX] = ma35d1_clk_mux(dev, "tmr0_mux", clk_base + REG_CLK_CLKSEL1, 715 0, 3, timer0_sel_clks, 716 ARRAY_SIZE(timer0_sel_clks)); 717 hws[TMR0_GATE] = ma35d1_clk_gate(dev, "tmr0_gate", "tmr0_mux", 718 clk_base + REG_CLK_APBCLK0, 0); 719 hws[TMR1_MUX] = ma35d1_clk_mux(dev, "tmr1_mux", clk_base + REG_CLK_CLKSEL1, 720 4, 3, timer1_sel_clks, 721 ARRAY_SIZE(timer1_sel_clks)); 722 hws[TMR1_GATE] = ma35d1_clk_gate(dev, "tmr1_gate", "tmr1_mux", 723 clk_base + REG_CLK_APBCLK0, 1); 724 hws[TMR2_MUX] = ma35d1_clk_mux(dev, "tmr2_mux", clk_base + REG_CLK_CLKSEL1, 725 8, 3, timer2_sel_clks, 726 ARRAY_SIZE(timer2_sel_clks)); 727 hws[TMR2_GATE] = ma35d1_clk_gate(dev, "tmr2_gate", "tmr2_mux", 728 clk_base + REG_CLK_APBCLK0, 2); 729 hws[TMR3_MUX] = ma35d1_clk_mux(dev, "tmr3_mux", clk_base + REG_CLK_CLKSEL1, 730 12, 3, timer3_sel_clks, 731 ARRAY_SIZE(timer3_sel_clks)); 732 hws[TMR3_GATE] = ma35d1_clk_gate(dev, "tmr3_gate", "tmr3_mux", 733 clk_base + REG_CLK_APBCLK0, 3); 734 hws[TMR4_MUX] = ma35d1_clk_mux(dev, "tmr4_mux", clk_base + REG_CLK_CLKSEL1, 735 16, 3, timer4_sel_clks, 736 ARRAY_SIZE(timer4_sel_clks)); 737 hws[TMR4_GATE] = ma35d1_clk_gate(dev, "tmr4_gate", "tmr4_mux", 738 clk_base + REG_CLK_APBCLK0, 4); 739 hws[TMR5_MUX] = ma35d1_clk_mux(dev, "tmr5_mux", clk_base + REG_CLK_CLKSEL1, 740 20, 3, timer5_sel_clks, 741 ARRAY_SIZE(timer5_sel_clks)); 742 hws[TMR5_GATE] = ma35d1_clk_gate(dev, "tmr5_gate", "tmr5_mux", 743 clk_base + REG_CLK_APBCLK0, 5); 744 hws[TMR6_MUX] = ma35d1_clk_mux(dev, "tmr6_mux", clk_base + REG_CLK_CLKSEL1, 745 24, 3, timer6_sel_clks, 746 ARRAY_SIZE(timer6_sel_clks)); 747 hws[TMR6_GATE] = ma35d1_clk_gate(dev, "tmr6_gate", "tmr6_mux", 748 clk_base + REG_CLK_APBCLK0, 6); 749 hws[TMR7_MUX] = ma35d1_clk_mux(dev, "tmr7_mux", clk_base + REG_CLK_CLKSEL1, 750 28, 3, timer7_sel_clks, 751 ARRAY_SIZE(timer7_sel_clks)); 752 hws[TMR7_GATE] = ma35d1_clk_gate(dev, "tmr7_gate", "tmr7_mux", 753 clk_base + REG_CLK_APBCLK0, 7); 754 hws[TMR8_MUX] = ma35d1_clk_mux(dev, "tmr8_mux", clk_base + REG_CLK_CLKSEL2, 755 0, 3, timer8_sel_clks, 756 ARRAY_SIZE(timer8_sel_clks)); 757 hws[TMR8_GATE] = ma35d1_clk_gate(dev, "tmr8_gate", "tmr8_mux", 758 clk_base + REG_CLK_APBCLK0, 8); 759 hws[TMR9_MUX] = ma35d1_clk_mux(dev, "tmr9_mux", clk_base + REG_CLK_CLKSEL2, 760 4, 3, timer9_sel_clks, 761 ARRAY_SIZE(timer9_sel_clks)); 762 hws[TMR9_GATE] = ma35d1_clk_gate(dev, "tmr9_gate", "tmr9_mux", 763 clk_base + REG_CLK_APBCLK0, 9); 764 hws[TMR10_MUX] = ma35d1_clk_mux(dev, "tmr10_mux", clk_base + REG_CLK_CLKSEL2, 765 8, 3, timer10_sel_clks, 766 ARRAY_SIZE(timer10_sel_clks)); 767 hws[TMR10_GATE] = ma35d1_clk_gate(dev, "tmr10_gate", "tmr10_mux", 768 clk_base + REG_CLK_APBCLK0, 10); 769 hws[TMR11_MUX] = ma35d1_clk_mux(dev, "tmr11_mux", clk_base + REG_CLK_CLKSEL2, 770 12, 3, timer11_sel_clks, 771 ARRAY_SIZE(timer11_sel_clks)); 772 hws[TMR11_GATE] = ma35d1_clk_gate(dev, "tmr11_gate", "tmr11_mux", 773 clk_base + REG_CLK_APBCLK0, 11); 774 775 hws[UART0_MUX] = ma35d1_clk_mux(dev, "uart0_mux", clk_base + REG_CLK_CLKSEL2, 776 16, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 777 hws[UART0_DIV] = ma35d1_clk_divider(dev, "uart0_div", "uart0_mux", 778 clk_base + REG_CLK_CLKDIV1, 779 16, 4); 780 hws[UART0_GATE] = ma35d1_clk_gate(dev, "uart0_gate", "uart0_div", 781 clk_base + REG_CLK_APBCLK0, 12); 782 hws[UART1_MUX] = ma35d1_clk_mux(dev, "uart1_mux", clk_base + REG_CLK_CLKSEL2, 783 18, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 784 hws[UART1_DIV] = ma35d1_clk_divider(dev, "uart1_div", "uart1_mux", 785 clk_base + REG_CLK_CLKDIV1, 786 20, 4); 787 hws[UART1_GATE] = ma35d1_clk_gate(dev, "uart1_gate", "uart1_div", 788 clk_base + REG_CLK_APBCLK0, 13); 789 hws[UART2_MUX] = ma35d1_clk_mux(dev, "uart2_mux", clk_base + REG_CLK_CLKSEL2, 790 20, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 791 hws[UART2_DIV] = ma35d1_clk_divider(dev, "uart2_div", "uart2_mux", 792 clk_base + REG_CLK_CLKDIV1, 793 24, 4); 794 hws[UART2_GATE] = ma35d1_clk_gate(dev, "uart2_gate", "uart2_div", 795 clk_base + REG_CLK_APBCLK0, 14); 796 hws[UART3_MUX] = ma35d1_clk_mux(dev, "uart3_mux", clk_base + REG_CLK_CLKSEL2, 797 22, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 798 hws[UART3_DIV] = ma35d1_clk_divider(dev, "uart3_div", "uart3_mux", 799 clk_base + REG_CLK_CLKDIV1, 800 28, 4); 801 hws[UART3_GATE] = ma35d1_clk_gate(dev, "uart3_gate", "uart3_div", 802 clk_base + REG_CLK_APBCLK0, 15); 803 hws[UART4_MUX] = ma35d1_clk_mux(dev, "uart4_mux", clk_base + REG_CLK_CLKSEL2, 804 24, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 805 hws[UART4_DIV] = ma35d1_clk_divider(dev, "uart4_div", "uart4_mux", 806 clk_base + REG_CLK_CLKDIV2, 807 0, 4); 808 hws[UART4_GATE] = ma35d1_clk_gate(dev, "uart4_gate", "uart4_div", 809 clk_base + REG_CLK_APBCLK0, 16); 810 hws[UART5_MUX] = ma35d1_clk_mux(dev, "uart5_mux", clk_base + REG_CLK_CLKSEL2, 811 26, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 812 hws[UART5_DIV] = ma35d1_clk_divider(dev, "uart5_div", "uart5_mux", 813 clk_base + REG_CLK_CLKDIV2, 814 4, 4); 815 hws[UART5_GATE] = ma35d1_clk_gate(dev, "uart5_gate", "uart5_div", 816 clk_base + REG_CLK_APBCLK0, 17); 817 hws[UART6_MUX] = ma35d1_clk_mux(dev, "uart6_mux", clk_base + REG_CLK_CLKSEL2, 818 28, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 819 hws[UART6_DIV] = ma35d1_clk_divider(dev, "uart6_div", "uart6_mux", 820 clk_base + REG_CLK_CLKDIV2, 821 8, 4); 822 hws[UART6_GATE] = ma35d1_clk_gate(dev, "uart6_gate", "uart6_div", 823 clk_base + REG_CLK_APBCLK0, 18); 824 hws[UART7_MUX] = ma35d1_clk_mux(dev, "uart7_mux", clk_base + REG_CLK_CLKSEL2, 825 30, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 826 hws[UART7_DIV] = ma35d1_clk_divider(dev, "uart7_div", "uart7_mux", 827 clk_base + REG_CLK_CLKDIV2, 828 12, 4); 829 hws[UART7_GATE] = ma35d1_clk_gate(dev, "uart7_gate", "uart7_div", 830 clk_base + REG_CLK_APBCLK0, 19); 831 hws[UART8_MUX] = ma35d1_clk_mux(dev, "uart8_mux", clk_base + REG_CLK_CLKSEL3, 832 0, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 833 hws[UART8_DIV] = ma35d1_clk_divider(dev, "uart8_div", "uart8_mux", 834 clk_base + REG_CLK_CLKDIV2, 835 16, 4); 836 hws[UART8_GATE] = ma35d1_clk_gate(dev, "uart8_gate", "uart8_div", 837 clk_base + REG_CLK_APBCLK0, 20); 838 hws[UART9_MUX] = ma35d1_clk_mux(dev, "uart9_mux", clk_base + REG_CLK_CLKSEL3, 839 2, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 840 hws[UART9_DIV] = ma35d1_clk_divider(dev, "uart9_div", "uart9_mux", 841 clk_base + REG_CLK_CLKDIV2, 842 20, 4); 843 hws[UART9_GATE] = ma35d1_clk_gate(dev, "uart9_gate", "uart9_div", 844 clk_base + REG_CLK_APBCLK0, 21); 845 hws[UART10_MUX] = ma35d1_clk_mux(dev, "uart10_mux", clk_base + REG_CLK_CLKSEL3, 846 4, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 847 hws[UART10_DIV] = ma35d1_clk_divider(dev, "uart10_div", "uart10_mux", 848 clk_base + REG_CLK_CLKDIV2, 849 24, 4); 850 hws[UART10_GATE] = ma35d1_clk_gate(dev, "uart10_gate", "uart10_div", 851 clk_base + REG_CLK_APBCLK0, 22); 852 hws[UART11_MUX] = ma35d1_clk_mux(dev, "uart11_mux", clk_base + REG_CLK_CLKSEL3, 853 6, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 854 hws[UART11_DIV] = ma35d1_clk_divider(dev, "uart11_div", "uart11_mux", 855 clk_base + REG_CLK_CLKDIV2, 856 28, 4); 857 hws[UART11_GATE] = ma35d1_clk_gate(dev, "uart11_gate", "uart11_div", 858 clk_base + REG_CLK_APBCLK0, 23); 859 hws[UART12_MUX] = ma35d1_clk_mux(dev, "uart12_mux", clk_base + REG_CLK_CLKSEL3, 860 8, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 861 hws[UART12_DIV] = ma35d1_clk_divider(dev, "uart12_div", "uart12_mux", 862 clk_base + REG_CLK_CLKDIV3, 863 0, 4); 864 hws[UART12_GATE] = ma35d1_clk_gate(dev, "uart12_gate", "uart12_div", 865 clk_base + REG_CLK_APBCLK0, 24); 866 hws[UART13_MUX] = ma35d1_clk_mux(dev, "uart13_mux", clk_base + REG_CLK_CLKSEL3, 867 10, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 868 hws[UART13_DIV] = ma35d1_clk_divider(dev, "uart13_div", "uart13_mux", 869 clk_base + REG_CLK_CLKDIV3, 870 4, 4); 871 hws[UART13_GATE] = ma35d1_clk_gate(dev, "uart13_gate", "uart13_div", 872 clk_base + REG_CLK_APBCLK0, 25); 873 hws[UART14_MUX] = ma35d1_clk_mux(dev, "uart14_mux", clk_base + REG_CLK_CLKSEL3, 874 12, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 875 hws[UART14_DIV] = ma35d1_clk_divider(dev, "uart14_div", "uart14_mux", 876 clk_base + REG_CLK_CLKDIV3, 877 8, 4); 878 hws[UART14_GATE] = ma35d1_clk_gate(dev, "uart14_gate", "uart14_div", 879 clk_base + REG_CLK_APBCLK0, 26); 880 hws[UART15_MUX] = ma35d1_clk_mux(dev, "uart15_mux", clk_base + REG_CLK_CLKSEL3, 881 14, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 882 hws[UART15_DIV] = ma35d1_clk_divider(dev, "uart15_div", "uart15_mux", 883 clk_base + REG_CLK_CLKDIV3, 884 12, 4); 885 hws[UART15_GATE] = ma35d1_clk_gate(dev, "uart15_gate", "uart15_div", 886 clk_base + REG_CLK_APBCLK0, 27); 887 hws[UART16_MUX] = ma35d1_clk_mux(dev, "uart16_mux", clk_base + REG_CLK_CLKSEL3, 888 16, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); 889 hws[UART16_DIV] = ma35d1_clk_divider(dev, "uart16_div", "uart16_mux", 890 clk_base + REG_CLK_CLKDIV3, 891 16, 4); 892 hws[UART16_GATE] = ma35d1_clk_gate(dev, "uart16_gate", "uart16_div", 893 clk_base + REG_CLK_APBCLK0, 28); 894 895 hws[RTC_GATE] = ma35d1_clk_gate(dev, "rtc_gate", "lxt", 896 clk_base + REG_CLK_APBCLK0, 29); 897 hws[DDR_GATE] = ma35d1_clk_gate(dev, "ddr_gate", "ddrpll", 898 clk_base + REG_CLK_APBCLK0, 30); 899 900 hws[KPI_MUX] = ma35d1_clk_mux(dev, "kpi_mux", clk_base + REG_CLK_CLKSEL4, 901 30, 1, kpi_sel_clks, ARRAY_SIZE(kpi_sel_clks)); 902 hws[KPI_DIV] = ma35d1_clk_divider(dev, "kpi_div", "kpi_mux", 903 clk_base + REG_CLK_CLKDIV4, 904 24, 8); 905 hws[KPI_GATE] = ma35d1_clk_gate(dev, "kpi_gate", "kpi_div", 906 clk_base + REG_CLK_APBCLK0, 31); 907 908 hws[I2C0_GATE] = ma35d1_clk_gate(dev, "i2c0_gate", "pclk0", 909 clk_base + REG_CLK_APBCLK1, 0); 910 hws[I2C1_GATE] = ma35d1_clk_gate(dev, "i2c1_gate", "pclk1", 911 clk_base + REG_CLK_APBCLK1, 1); 912 hws[I2C2_GATE] = ma35d1_clk_gate(dev, "i2c2_gate", "pclk2", 913 clk_base + REG_CLK_APBCLK1, 2); 914 hws[I2C3_GATE] = ma35d1_clk_gate(dev, "i2c3_gate", "pclk0", 915 clk_base + REG_CLK_APBCLK1, 3); 916 hws[I2C4_GATE] = ma35d1_clk_gate(dev, "i2c4_gate", "pclk1", 917 clk_base + REG_CLK_APBCLK1, 4); 918 hws[I2C5_GATE] = ma35d1_clk_gate(dev, "i2c5_gate", "pclk2", 919 clk_base + REG_CLK_APBCLK1, 5); 920 921 hws[QSPI0_MUX] = ma35d1_clk_mux(dev, "qspi0_mux", clk_base + REG_CLK_CLKSEL4, 922 8, 2, qspi0_sel_clks, ARRAY_SIZE(qspi0_sel_clks)); 923 hws[QSPI0_GATE] = ma35d1_clk_gate(dev, "qspi0_gate", "qspi0_mux", 924 clk_base + REG_CLK_APBCLK1, 6); 925 hws[QSPI1_MUX] = ma35d1_clk_mux(dev, "qspi1_mux", clk_base + REG_CLK_CLKSEL4, 926 10, 2, qspi1_sel_clks, ARRAY_SIZE(qspi1_sel_clks)); 927 hws[QSPI1_GATE] = ma35d1_clk_gate(dev, "qspi1_gate", "qspi1_mux", 928 clk_base + REG_CLK_APBCLK1, 7); 929 930 hws[SMC0_MUX] = ma35d1_clk_mux(dev, "smc0_mux", clk_base + REG_CLK_CLKSEL4, 931 28, 1, smc_sel_clks, ARRAY_SIZE(smc_sel_clks)); 932 hws[SMC0_DIV] = ma35d1_clk_divider(dev, "smc0_div", "smc0_mux", 933 clk_base + REG_CLK_CLKDIV1, 934 0, 4); 935 hws[SMC0_GATE] = ma35d1_clk_gate(dev, "smc0_gate", "smc0_div", 936 clk_base + REG_CLK_APBCLK1, 12); 937 hws[SMC1_MUX] = ma35d1_clk_mux(dev, "smc1_mux", clk_base + REG_CLK_CLKSEL4, 938 29, 1, smc_sel_clks, ARRAY_SIZE(smc_sel_clks)); 939 hws[SMC1_DIV] = ma35d1_clk_divider(dev, "smc1_div", "smc1_mux", 940 clk_base + REG_CLK_CLKDIV1, 941 4, 4); 942 hws[SMC1_GATE] = ma35d1_clk_gate(dev, "smc1_gate", "smc1_div", 943 clk_base + REG_CLK_APBCLK1, 13); 944 945 hws[WDT0_MUX] = ma35d1_clk_mux(dev, "wdt0_mux", clk_base + REG_CLK_CLKSEL3, 946 20, 2, wdt0_sel_clks, ARRAY_SIZE(wdt0_sel_clks)); 947 hws[WDT0_GATE] = ma35d1_clk_gate(dev, "wdt0_gate", "wdt0_mux", 948 clk_base + REG_CLK_APBCLK1, 16); 949 hws[WDT1_MUX] = ma35d1_clk_mux(dev, "wdt1_mux", clk_base + REG_CLK_CLKSEL3, 950 24, 2, wdt1_sel_clks, ARRAY_SIZE(wdt1_sel_clks)); 951 hws[WDT1_GATE] = ma35d1_clk_gate(dev, "wdt1_gate", "wdt1_mux", 952 clk_base + REG_CLK_APBCLK1, 17); 953 hws[WDT2_MUX] = ma35d1_clk_mux(dev, "wdt2_mux", clk_base + REG_CLK_CLKSEL3, 954 28, 2, wdt2_sel_clks, ARRAY_SIZE(wdt2_sel_clks)); 955 hws[WDT2_GATE] = ma35d1_clk_gate(dev, "wdt2_gate", "wdt2_mux", 956 clk_base + REG_CLK_APBCLK1, 18); 957 958 hws[WWDT0_MUX] = ma35d1_clk_mux(dev, "wwdt0_mux", clk_base + REG_CLK_CLKSEL3, 959 22, 2, wwdt0_sel_clks, ARRAY_SIZE(wwdt0_sel_clks)); 960 hws[WWDT1_MUX] = ma35d1_clk_mux(dev, "wwdt1_mux", clk_base + REG_CLK_CLKSEL3, 961 26, 2, wwdt1_sel_clks, ARRAY_SIZE(wwdt1_sel_clks)); 962 hws[WWDT2_MUX] = ma35d1_clk_mux(dev, "wwdt2_mux", clk_base + REG_CLK_CLKSEL3, 963 30, 2, wwdt2_sel_clks, ARRAY_SIZE(wwdt2_sel_clks)); 964 965 hws[EPWM0_GATE] = ma35d1_clk_gate(dev, "epwm0_gate", "pclk1", 966 clk_base + REG_CLK_APBCLK1, 24); 967 hws[EPWM1_GATE] = ma35d1_clk_gate(dev, "epwm1_gate", "pclk2", 968 clk_base + REG_CLK_APBCLK1, 25); 969 hws[EPWM2_GATE] = ma35d1_clk_gate(dev, "epwm2_gate", "pclk1", 970 clk_base + REG_CLK_APBCLK1, 26); 971 972 hws[I2S0_MUX] = ma35d1_clk_mux(dev, "i2s0_mux", clk_base + REG_CLK_CLKSEL4, 973 12, 2, i2s0_sel_clks, ARRAY_SIZE(i2s0_sel_clks)); 974 hws[I2S0_GATE] = ma35d1_clk_gate(dev, "i2s0_gate", "i2s0_mux", 975 clk_base + REG_CLK_APBCLK2, 0); 976 hws[I2S1_MUX] = ma35d1_clk_mux(dev, "i2s1_mux", clk_base + REG_CLK_CLKSEL4, 977 14, 2, i2s1_sel_clks, ARRAY_SIZE(i2s1_sel_clks)); 978 hws[I2S1_GATE] = ma35d1_clk_gate(dev, "i2s1_gate", "i2s1_mux", 979 clk_base + REG_CLK_APBCLK2, 1); 980 981 hws[SSMCC_GATE] = ma35d1_clk_gate(dev, "ssmcc_gate", "pclk3", 982 clk_base + REG_CLK_APBCLK2, 2); 983 hws[SSPCC_GATE] = ma35d1_clk_gate(dev, "sspcc_gate", "pclk3", 984 clk_base + REG_CLK_APBCLK2, 3); 985 986 hws[SPI0_MUX] = ma35d1_clk_mux(dev, "spi0_mux", clk_base + REG_CLK_CLKSEL4, 987 0, 2, spi0_sel_clks, ARRAY_SIZE(spi0_sel_clks)); 988 hws[SPI0_GATE] = ma35d1_clk_gate(dev, "spi0_gate", "spi0_mux", 989 clk_base + REG_CLK_APBCLK2, 4); 990 hws[SPI1_MUX] = ma35d1_clk_mux(dev, "spi1_mux", clk_base + REG_CLK_CLKSEL4, 991 2, 2, spi1_sel_clks, ARRAY_SIZE(spi1_sel_clks)); 992 hws[SPI1_GATE] = ma35d1_clk_gate(dev, "spi1_gate", "spi1_mux", 993 clk_base + REG_CLK_APBCLK2, 5); 994 hws[SPI2_MUX] = ma35d1_clk_mux(dev, "spi2_mux", clk_base + REG_CLK_CLKSEL4, 995 4, 2, spi2_sel_clks, ARRAY_SIZE(spi2_sel_clks)); 996 hws[SPI2_GATE] = ma35d1_clk_gate(dev, "spi2_gate", "spi2_mux", 997 clk_base + REG_CLK_APBCLK2, 6); 998 hws[SPI3_MUX] = ma35d1_clk_mux(dev, "spi3_mux", clk_base + REG_CLK_CLKSEL4, 999 6, 2, spi3_sel_clks, ARRAY_SIZE(spi3_sel_clks)); 1000 hws[SPI3_GATE] = ma35d1_clk_gate(dev, "spi3_gate", "spi3_mux", 1001 clk_base + REG_CLK_APBCLK2, 7); 1002 1003 hws[ECAP0_GATE] = ma35d1_clk_gate(dev, "ecap0_gate", "pclk1", 1004 clk_base + REG_CLK_APBCLK2, 8); 1005 hws[ECAP1_GATE] = ma35d1_clk_gate(dev, "ecap1_gate", "pclk2", 1006 clk_base + REG_CLK_APBCLK2, 9); 1007 hws[ECAP2_GATE] = ma35d1_clk_gate(dev, "ecap2_gate", "pclk1", 1008 clk_base + REG_CLK_APBCLK2, 10); 1009 1010 hws[QEI0_GATE] = ma35d1_clk_gate(dev, "qei0_gate", "pclk1", 1011 clk_base + REG_CLK_APBCLK2, 12); 1012 hws[QEI1_GATE] = ma35d1_clk_gate(dev, "qei1_gate", "pclk2", 1013 clk_base + REG_CLK_APBCLK2, 13); 1014 hws[QEI2_GATE] = ma35d1_clk_gate(dev, "qei2_gate", "pclk1", 1015 clk_base + REG_CLK_APBCLK2, 14); 1016 1017 hws[ADC_DIV] = ma35d1_reg_adc_clkdiv(dev, "adc_div", hws[PCLK0], 1018 &ma35d1_lock, 0, 1019 clk_base + REG_CLK_CLKDIV4, 1020 4, 17, 0x1ffff); 1021 hws[ADC_GATE] = ma35d1_clk_gate(dev, "adc_gate", "adc_div", 1022 clk_base + REG_CLK_APBCLK2, 24); 1023 1024 hws[EADC_DIV] = ma35d1_clk_divider_table(dev, "eadc_div", "pclk2", 1025 clk_base + REG_CLK_CLKDIV4, 1026 0, 4, eadc_div_table); 1027 hws[EADC_GATE] = ma35d1_clk_gate(dev, "eadc_gate", "eadc_div", 1028 clk_base + REG_CLK_APBCLK2, 25); 1029 1030 return devm_of_clk_add_hw_provider(dev, 1031 of_clk_hw_onecell_get, 1032 ma35d1_hw_data); 1033} 1034 1035static const struct of_device_id ma35d1_clk_of_match[] = { 1036 { .compatible = "nuvoton,ma35d1-clk" }, 1037 { } 1038}; 1039MODULE_DEVICE_TABLE(of, ma35d1_clk_of_match); 1040 1041static struct platform_driver ma35d1_clk_driver = { 1042 .probe = ma35d1_clocks_probe, 1043 .driver = { 1044 .name = "ma35d1-clk", 1045 .of_match_table = ma35d1_clk_of_match, 1046 }, 1047}; 1048 1049static int __init ma35d1_clocks_init(void) 1050{ 1051 return platform_driver_register(&ma35d1_clk_driver); 1052} 1053 1054postcore_initcall(ma35d1_clocks_init); 1055 1056MODULE_AUTHOR("Chi-Fang Li <cfli0@nuvoton.com>"); 1057MODULE_DESCRIPTION("NUVOTON MA35D1 Clock Driver"); 1058MODULE_LICENSE("GPL"); 1059