#
8bb289bb |
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31-Jan-2023 |
Oleksij Rempel <linux@rempel-privat.de> |
clk: imx6q: add ethernet refclock mux support Add ethernet refclock mux support and set it to internal clock by default. This configuration will not affect existing boards since machine code currently overwrites this default. The machine code will be fixed in a separate patch. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-3-o.rempel@pengutronix.de
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#
2d5513bf |
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04-Jan-2023 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: remove clk_count of imx_register_uart_clocks The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com
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#
283f1b9a |
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02-Jul-2021 |
Dong Aisheng <aisheng.dong@nxp.com> |
clk: imx6q: fix uart earlycon unwork The earlycon depends on the bootloader setup UART clocks being retained. There're actually two uart clocks (ipg, per) on MX6QDL, but the 'Fixes' commit change to register only one which means another clock may be disabled during booting phase and result in the earlycon unwork. Cc: stable@vger.kernel.org # v5.10+ Fixes: 379c9a24cc23 ("clk: imx: Fix reparenting of UARTs not associated with stdout") Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20210702085438.1988087-1-aisheng.dong@nxp.com Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
379c9a24 |
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13-Mar-2021 |
Adam Ford <aford173@gmail.com> |
clk: imx: Fix reparenting of UARTs not associated with stdout Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already. clk: failed to reparent uart1 to sys_pll1_80m: -16 Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks. When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized. Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
f3afd3fb |
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17-Jan-2021 |
Ahmad Fatoum <a.fatoum@pengutronix.de> |
clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting Since 5d283b083800 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK"), the clock driver warns if ldb_di\d_sel is changed from reset value on system boot. This warning is printed even if the bootloader (or a previous kernel that did kexec) followed the correct procedure for glitch-free reparenting. As such systems are doing everything correctly, a warning is too harsh. Demote to a notice, so users are still alerted, but without cluttering a loglevel=5 boot. While at it, add the words "possible glitch" into the log message, to make it more user-friendly. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
7d6b5e4f |
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04-Aug-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx: Explicitly include bits.h It is better to explicitly include the required header file rather then get it through some recursive include. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
3ff86050 |
|
02-Dec-2019 |
Jan Remmet <j.remmet@phytec.de> |
clk: imx6q: disable non functional divider The /2 divider between pll4_audio_div and pll4_post_div is not working on imx6q. The frequency is not halved as reported by the clock tree and measured on clko. In the technical reference manual the divider was removed in revision 4. It's also not listed in the imx6qp manual. imx6dl manual mentions a divider for PLL4 and the according register description. So keep the divider here. Signed-off-by: Jan Remmet <j.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
1df37992 |
|
01-Jul-2019 |
Stephen Rothwell <sfr@canb.auug.org.au> |
clk: consoldiate the __clk_get_hw() declarations Without this we were getting errors like: In file included from drivers/clk/clkdev.c:22:0: drivers/clk/clk.h:36:23: error: static declaration of '__clk_get_hw' follows non-static declaration include/linux/clk-provider.h:808:16: note: previous declaration of '__clk_get_hw' was here Fixes: 59fcdce425b7 ("clk: Remove ifdef for COMMON_CLK in clk-provider.h") fixes: 73e0e496afda ("clkdev: Always allocate a struct clk and call __clk_get() w/ CCF") Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
0e12248c |
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17-Jun-2019 |
Arnd Bergmann <arnd@arndb.de> |
clk: imx6q: fix section mismatch warning The imx6q_obtain_fixed_clk_hw lacks an __init marker, which leads to this otherwise harmless warning: WARNING: vmlinux.o(.text+0x495358): Section mismatch in reference from the function imx6q_obtain_fixed_clk_hw() to the function .init.text:imx_obtain_fixed_clock_hw() The function imx6q_obtain_fixed_clk_hw() references the function __init imx_obtain_fixed_clock_hw(). This is often because imx6q_obtain_fixed_clk_hw lacks a __init annotation or the annotation of imx_obtain_fixed_clock_hw is wrong. Fixes: 992b703b5b38 ("clk: imx6q: Switch to clk_hw based API") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
992b703b |
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28-May-2019 |
Abel Vesa <abel.vesa@nxp.com> |
clk: imx6q: Switch to clk_hw based API Switch the entire clk-imx6q driver to clk_hw based API. Add imx6q_obtain_fixed_clk_hw helper to clean up the registration of the clocks that are either found in device tree or are assigned a fixed zero rate. This switch allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
f5697226 |
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28-May-2019 |
Abel Vesa <abel.vesa@nxp.com> |
clk: imx6q: Do not reparent uninitialized IMX6QDL_CLK_PERIPH2 clock The clock is registered later than these two re-parentings. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
fcaf2036 |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 159 Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
c129b6fe |
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12-May-2019 |
Anson Huang <anson.huang@nxp.com> |
clk: imx: Use imx_mmdc_mask_handshake() API for masking MMDC channel Use imx_mmdc_mask_handshake() API instead of programming CCM register directly in each platform to mask unused MMDC channel's handshake. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
c9ec1d8f |
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26-Dec-2018 |
Yangtao Li <tiny.windzz@gmail.com> |
clk: imx6q: fix refcount leak in imx6q_clocks_init() The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: 2acd1b6f889c ("ARM: i.MX6: implement clocks using common clock framework") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
3cc48976 |
|
15-Nov-2018 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx6q: handle ENET PLL bypass The ENET PLL is different from the other i.MX6 PLLs, as it has multiple outputs with different post-dividers, which are all bypassed if the single bypass bit is activated. The hardware setup looks something like this: _ refclk-o---PLL---o----DIV1-----| \ | | |M |----OUT1 o-----------------------|_/ | | _ | o----DIV2-----| \ | | |M |----OUT2 o-----------------------|_/ | | _ | `----DIV3-----| \ | |M |----OUT3 `-----------------------|_/ The bypass bit not only bypasses the PLL, but also the attached post-dividers. This would be reasonbly straight forward to model with a single output, or with different bypass bits for each output, but sadly the HW guys decided that it would be good to actuate all 3 muxes with a single bit. So the need to have the PLL bypassed for one of the outputs always affects 2 other (in our model) independent branches of the clock tree. This means the decision to bypass this PLL is a system wide design choice and should not be changed on-the-fly, so we can treat any bapass configuration as static. As such we can just register the post-dividiers with a ratio that reflects the bypass status, which allows us to bypass the PLL without breaking our abstraction model and with it DT stability. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
a29be918 |
|
15-Nov-2018 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx6q: optionally get CCM inputs via standard clock handles When specifying external clock inputs to the CCM the current code requires the clocks to be in a "clocks" child node of the DT root. This is not really conformant with DT best practices. To avoid the need to deviate from those best practices, allow the clock inputs to be specified via standard clock handles. This is in line with how drivers of the later CCM driver revisions on newer i.MX SoCs handle this. As we can't retroactively change the DT binding, allow this as an option with a fallback to the old way of how this has been handled. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
f7542d81 |
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15-Nov-2018 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx6q: reset exclusive gates on init The exclusive gates may be set up in the wrong way by software running before the clock driver comes up. In that case the exclusive setup is locked in its initial state, as the complementary function can't be activated without disabling the initial setup first. To avoid this lock situation, reset the exclusive gates to the off state and allow the kernel to provide the proper setup. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Dong Aisheng <Aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
92991494 |
|
29-Nov-2018 |
Anson Huang <anson.huang@nxp.com> |
clk: imx6q: add DCICx clocks gate On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks gate in CCM_CCGR0 register, add them into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
341ce356 |
|
31-Aug-2018 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx6q: add mmdc0 ipg clock i.MX6Q has MMDC0 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
a7047564 |
|
07-Jun-2018 |
Philipp Puschmann <pp@emlix.com> |
clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL q/dl datasheets list the 5th selection value for ck01_sel as video_27M_clk_root. By replacing the dummy value we then can set IMX6QDL_CLK_VIDEO_27M as parent for IMX6QDL_CLK_CKO1_SEL. Signed-off-by: Philipp Puschmann <pp@emlix.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
54614d12 |
|
03-Jun-2018 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx6q: remove clks_init_on array Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. ARM clock is busy divider type which has the CLK_IS_CRITICAL flag set by default when registered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
b1569380 |
|
29-May-2018 |
Colin Didier <colin.didier@devialet.com> |
clk: imx6: add EPIT clock support Add EPIT clock support to the i.MX6Q clocking infrastructure. Signed-off-by: Colin Didier <colin.didier@devialet.com> Signed-off-by: Clément Peron <clement.peron@devialet.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
c68ee58d |
|
31-Jul-2017 |
Sébastien Szymanski <sebastien.szymanski@armadeus.com> |
clk: imx6: refine hdmi_isfr's parent to make HDMI work on i.MX6 SoCs w/o VPU On i.MX6 SoCs without VPU (in my case MCIMX6D4AVT10AC), the hdmi driver fails to probe: [ 2.540030] dwhdmi-imx 120000.hdmi: Unsupported HDMI controller (0000:00:00) [ 2.548199] imx-drm display-subsystem: failed to bind 120000.hdmi (ops dw_hdmi_imx_ops): -19 [ 2.557403] imx-drm display-subsystem: master bind failed: -19 That's because hdmi_isfr's parent, video_27m, is not correctly ungated. As explained in commit 5ccc248cc537 ("ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate"), video_27m is gated by CCM_CCGR3[CG8]. On i.MX6 SoCs with VPU, the hdmi is working thanks to the CCM_CMEOR[mod_en_ov_vpu] bit which makes the video_27m ungated whatever is in CCM_CCGR3[CG8]. The issue can be reproduced by setting CCMEOR[mod_en_ov_vpu] to 0. Make the HDMI work in every case by setting hdmi_isfr's parent to mipi_core_cfg. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
f4a0a6c3 |
|
13-Jan-2017 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx6: don't restrict LDB mux changes on QuadPlus The LDB mux/gate layout has been fixed on QuadPlus, so there is no need to restrict the LDB mux changes on this hardware, as the erratum preventing this from working properly is gone. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
5d283b08 |
|
17-Oct-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. The glitchy muxes are then registered as read-only. The clock parent can be selected using the assigned-clocks and assigned-clock-parents properties of the ccm device tree node: &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; }; The issue is explained in detail in EB821 ("LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines") [1]. [1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com> Tested-by Joshua Clayton <stillcompiling@gmail.com> Tested-by: Charles Kang <Charles.Kang@advantech.com.tw> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
03d576f2 |
|
17-Oct-2016 |
Philipp Zabel <p.zabel@pengutronix.de> |
clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. As this can not be guaranteed by the clock framework during runtime, make the ldb_di[x]_sel muxes read-only. A workaround to set the muxes once during boot could be added to the kernel or bootloader. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
f13abeff |
|
17-Oct-2016 |
Philipp Zabel <p.zabel@pengutronix.de> |
clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never succeed. Disable the handshake mechanism to allow changing the frequency of mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI clock. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
d8846023 |
|
16-Sep-2016 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx6: initialize GPU clocks Initialize the GPU clock muxes to sane inputs. Until now they have not been changed from their default values, which means that both GPU3D shader and GPU2D core were fed by clock inputs whose rates exceed the maximium allowed frequency of the cores by as much as 200MHz. This fixes a severe GPU stability issue on i.MX6DL. Cc: stable@vger.kernel.org Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
b1d51b44 |
|
16-Sep-2016 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx6: fix i.MX6DL clock tree to reflect reality The current clock tree only implements the minimal set of differences between the i.MX6Q and the i.MX6DL, but that doesn't really reflect reality. Apply the following fixes to match the RM: - DL has no GPU3D_SHADER_SEL/PODF, the shader domain is clocked by GPU3D_CORE - GPU3D_SHADER_SEL/PODF has been repurposed as GPU2D_CORE_SEL/PODF - GPU2D_CORE_SEL/PODF has been repurposed as MLB_SEL/PODF Cc: stable@vger.kernel.org Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
f83d3163 |
|
08-Jun-2016 |
Dong Aisheng <aisheng.dong@nxp.com> |
clk: imx: fix pll clock parents pllx_bypass_src mux shouldn't be the parent of pllx clock since it's only valid when when pllx BYPASS bit is set. Thus it is actually one parent of pllx_bypass only. Instead, pllx parent should be fixed to osc according to reference manual. Other plls have the same issue. e.g. before fix, the pll tree is: osc 6 6 24000000 0 0 pll1_bypass_src 0 0 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 After the fix, it's: osc 6 6 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
7196c52c |
|
30-Mar-2016 |
Lothar Waßmann <LW@KARO-electronics.de> |
clk: imx6q: fix typo in CAN clock definition commit ee36027427c7 ("clk: imx: Add clock support for imx6qp") introduced a regression due to a subtle typo in the 'can_root' clock definition. The effect is that trying to configure the bitrate of the can interfaces fails with -EDOM or produces a division by zero error due to the clock_freq of the can serial clock being reported as '0'. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Fixes: ee36027427c7 ("clk: imx: Add clock support for imx6qp") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
ee360274 |
|
02-Feb-2016 |
Bai Ping <ping.bai@nxp.com> |
clk: imx: Add clock support for imx6qp most of the clock tree structures on i.MX6 Quad Plus are same as on i.MX6Q. there still some differences between these two SOCs. compared to the i.XM6Q, the differents of clocks on i.MX6QP is mainly on: 1. New clock gate added to support the PRE and PRG modules 2. 24MHz OSC clock option added to the UART, IPG, ECSPI, and CAN clock roots. 3. MMDC channel 1 clock gate is now controllable. 4. clock gating added to the LDB_DIx_IPU clocks on i.MX6QP 5. EMI clock root divider fix 6. other updates fo CSCMRx, CSCDRx and CS2CDR registers. detailed infomation, please refer to the i.MX6QP RM. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
#
2e133f61 |
|
15-Nov-2015 |
Michael Trimarchi <michael@amarulasolutions.com> |
clk: imx: clk-imx6q: Let OSC to be routed to anaclk2/2b OSC can be used as USB hub source clock. An example we can route to CLK2_P imx6 pin. This show a usage example: [...] usb_hub: usb-hub { compatible = "smsc,usb3503a"; clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; clock-names = "refclk"; }; }; [...] &clks { assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; }; /sys/kernel/debug/clk/clk_summary osc 5 5 24000000 0 0 [...] lvds2_sel 1 1 24000000 0 0 lvds2_gate 1 1 24000000 0 0 [...] Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
84a87250 |
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10-Oct-2015 |
Shengjiu Wang <shengjiu.wang@freescale.com> |
clk: imx6: Add SPDIF_GCLK clock in clock tree Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also one clock of SPDIF, which is missed before. We found an issue that imx can't enter low power mode with spdif if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe, so its parent clock (PLL clock) is prepared, the prepare operation of PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled, then it can enter low power mode. So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock. SPDIF_GCLK's parent clock is ipg clock. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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0822f933 |
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21-Sep-2015 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx6: retain early UART clocks during kernel init Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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dd503f66 |
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05-Aug-2015 |
Victoria Milhoan <vicki.milhoan@freescale.com> |
ARM: clk-imx6q: Add CAAM clock support Add CAAM clock support to the i.MX6 clocking infrastructure. Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com> Tested-by: Horia Geantă <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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05e062f9 |
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26-Jun-2015 |
Fabio Estevam <fabio.estevam@freescale.com> |
clk: imx: clk-imx6q: Provide initial IPU clock settings for mx6dl Currently it is not possible to use HDMI and LVDS at the same time on a imx6dl-sabresd board. Fix this usecase by setting IMX6QDL_CLK_PLL3_PFD1_540M to 540MHz and also by setting it as the parent of IMX6QDL_CLK_IPU1_SEL. Based on the configuration done in the FSL kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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da946aea |
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20-May-2015 |
Sébastien Szymanski <sebastien.szymanski@armadeus.com> |
ARM: clk-imx6q: refine sata's parent According to IMX6D/Q RM, table 18-3, sata clock's parent is ahb, not ipg. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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11f68120 |
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26-Apr-2015 |
Shawn Guo <shawn.guo@linaro.org> |
ARM: imx: move clock drivers into drivers/clk After the cleanup on clock drivers, they are now ready to be moved into drivers/clk. Let's move them into drivers/clk/imx folder. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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