#
c30f600f |
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31-Jul-2023 |
Marco Felsch <m.felsch@pengutronix.de> |
clk: imx8mp: fix sai4 clock The reference manual don't mention a SAI4 hardware block. This would be clock slice 78 which is skipped (TRM, page 237). Remove any reference to this clock to align the driver with the reality. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.kernel.org/r/20230731142150.3186650-1-m.felsch@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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#
878b02d5 |
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03-May-2023 |
Yuxing Liu <lyx2022@hust.edu.cn> |
clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe() Replace of_iomap() and kzalloc() with devm_of_iomap() and devm_kzalloc() which can automatically release the related memory when the device or driver is removed or unloaded to avoid potential memory leak. In this case, iounmap(anatop_base) in line 427,433 are removed as manual release is not required. Besides, referring to clk-imx8mq.c, check the return code of of_clk_add_hw_provider, if it returns negtive, print error info and unregister hws, which makes the program more robust. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Yuxing Liu <lyx2022@hust.edu.cn> Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230503070607.2462-1-lyx2022@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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#
7875ee29 |
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03-Apr-2023 |
Haibo Chen <haibo.chen@nxp.com> |
clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-critical The 'nand_usdhc_bus' clock is only need to be enabled when usdhc or nand module is active, so change it to non-critical clock type. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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#
82afc344 |
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03-Apr-2023 |
Liu Ying <victor.liu@nxp.com> |
clk: imx: imx8mp: Add LDB root clock This patch adds "media_ldb_root_clk" clock for the LDB in the MEDIAMIX subsystem. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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#
3ea7c4c9 |
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03-Apr-2023 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: imx8mp: correct DISP2 pixel clock type The MEDIA_DISP2_CLK_ROOT use ccm_ahb_channel, it is bus type. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403094633.3366446-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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#
2d5513bf |
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04-Jan-2023 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: remove clk_count of imx_register_uart_clocks The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com
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#
8178e245 |
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13-Nov-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name() The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts. No functional changes intended. The replacements were made with the following command: grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g' Tested on a BSH SystemMaster (SMM) S2 board. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221113180839.1625832-1-dario.binacchi@amarulasolutions.com
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#
b1f12a68 |
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07-Nov-2022 |
Abel Vesa <abelvesa@kernel.org> |
clk: imx8mp: Add audio shared gate According to the RM, the CCGR101 is shared for the following root clocks: - AUDIO_AHB_CLK_ROOT - AUDIO_AXI_CLK_ROOT - SAI1_CLK_ROOT - SAI2_CLK_ROOT - SAI3_CLK_ROOT - SAI5_CLK_ROOT - SAI6_CLK_ROOT - SAI7_CLK_ROOT - PDM_CLK_ROOT IMX8MP_CLK_AUDIO_ROOT is same as AUDIO_AHB_CLK_ROOT which can avoid break any users. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/1667811007-19222-3-git-send-email-shengjiu.wang@nxp.com
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#
ed1f4ccf |
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30-Sep-2022 |
Li Jun <jun.li@nxp.com> |
clk: imx: imx8mp: add shared clk gate for usb suspend clk 32K usb suspend clock gate is shared with usb_root_clk, this shared clock gate was initially defined only for usb suspend clock, usb suspend clk is kept on while system is active or system sleep with usb wakeup enabled, so usb root clock is fine with this situation; with the commit cf7f3f4fa9e5 ("clk: imx8mp: fix usb_root_clk parent"), this clock gate is changed to be for usb root clock, but usb root clock will be off while usb is suspended, so usb suspend clock will be gated too, this cause some usb functionalities will not work, so define this clock to be a shared clock gate to conform with the real HW status. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Cc: stable@vger.kernel.org # v5.19+ Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/1664549663-20364-2-git-send-email-jun.li@nxp.com
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#
c68cd258 |
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14-Aug-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8mp: tune the order of enet_qos_root_clk The enet_qos_root_clk takes sim_enet_root_clk as parent. When registering enet_qos_root_clk, it will be put into clk orphan list, because sim_enet_root_clk is not ready. When sim_enet_root_clk is ready, clk_core_reparent_orphans_nolock will set enet_qos_root_clk parent to sim_enet_root_clk. Because CLK_OPS_PARENT_ENABLE is set, sim_enet_root_clk will be enabled and disabled during the enet_qos_root_clk reparent phase. All the above are correct. But with M7 booted early and using enet, M7 enet feature will be broken, because clk driver probe phase disable the needed clks, in case M7 firmware not configure sim_enet_root_clk. And tune the order would also save cpu cycles. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220815013428.476015-1-peng.fan@oss.nxp.com
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#
cf7f3f4f |
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07-May-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8mp: fix usb_root_clk parent According to reference mannual CCGR77(usb) sources from hsio_axi, fix it. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220507125430.793287-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
43896f56 |
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27-Apr-2022 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx8mp: add clkout1/2 support clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220427162131.3127303-1-l.stach@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
39772efd |
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13-Mar-2022 |
Marek Vasut <marex@denx.de> |
clk: imx8mp: Add DISP2 pixel clock Add pixel clock for second LCDIFv3 interface. Both LCDIFv3 interfaces use the same set of parent clock, so deduplicate imx8mp_media_disp1_pix_sels into common imx8mp_media_disp_pix_sels and use it for both. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220313123949.207284-1-marex@denx.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
56fddc69 |
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10-Mar-2022 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: Remove the snvs clock The SNVS moudule is not used only by the linux, it may also used by other SW component is secure world. No sense to populate it in linux, so remove it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220310093404.236966-1-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
19565ea1 |
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28-Feb-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: add mcore_booted module paratemter Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX8M, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and CCGR (clock gating) to gate clocks to peripherals. As below: anatop->ccm->ccgr->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for CCGR and CCM, auxiliary core normally only use CCGR hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Per NXP hardware design, because CCGR already support gate to peripherals, and clk root gate power leakage is negligible. So when in AMP case, we could not register the clk root gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220228124112.3974242-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
d097cc04 |
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25-Feb-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8mp: remove SYS PLL 1/2 clock gates Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220225081733.2294166-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
39d1e443 |
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11-Feb-2022 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock The IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock derives from the media_mipi_phy1_ref clock and is gated by the shared media clock gate. Its identifier is defined in dt-bindings/clock/imx8mp-clock.h but its definition is missing from the driver. Add it. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Paul Elder <paul.elder@ideasonboard.com> Link: https://lore.kernel.org/r/20220211091311.28146-1-laurent.pinchart@ideasonboard.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
9dd81021 |
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09-Nov-2021 |
Hui Wang <hui.wang@canonical.com> |
clk: imx8mp: Fix the parent clk of the audio_root_clk Having the parent of the audio_root_clk set to ipg_root in the clk-imx8mp.c, there is a hang happening when the audiomix IP regs are accessed. Switch parent to audio_ahb. And we could also refer to the section "5.1.4 System Clocks" of the IMX8MPRM.pdf, the parent clk of CCGR101 (Audiomix) is the AUDIO_AHB_CLK_ROOT. Signed-off-by: Hui Wang <hui.wang@canonical.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211109125657.63485-2-hui.wang@canonical.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
b24e288d |
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19-Apr-2021 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: Remove the audio ipg clock from imx8mp There is no audio ipg clock on i.MX8MP, so remove this from the clock driver. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
1840518a |
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15-Mar-2021 |
Richard Zhu <hongxing.zhu@nxp.com> |
clk: imx8mp: Remove the none exist pcie clocks In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC or internal system PLL. It is configured in the IOMUX_GPR14 register directly, and can't be contolled by CCM at all. Remove the PCIE PHY clock from clock driver to clean up codes. There is only one PCIe in i.MX8MP, remove the none exist second PCIe related clocks. Remove the none exsits clocks IDs together. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jason Liu <jason.hui.liu@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
379c9a24 |
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13-Mar-2021 |
Adam Ford <aford173@gmail.com> |
clk: imx: Fix reparenting of UARTs not associated with stdout Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already. clk: failed to reparent uart1 to sys_pll1_80m: -16 Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks. When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized. Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
f32e42f0 |
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03-Nov-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
clk: imx8mp: drop of_match_ptr from of_device_id table The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might be not relevant here). This fixes compile warning (!CONFIG_OF && !CONFIG_MODULES): drivers/clk/imx/clk-imx8mp.c:751:34: warning: ‘imx8mp_clk_of_match’ defined but not used [-Wunused-const-variable=] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
c277ca15 |
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01-Nov-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8m: fix bus critical clk registration noc/axi/ahb are bus clk, not peripheral clk. Since peripheral clk has a limitation that for peripheral clock slice, IP clock slices must be stopped to change the clock source. However if the bus clk is marked as critical clk peripheral, the assigned clock parent operation will fail. So we added CLK_SET_PARENT_GATE flag to avoid glitch. And add imx8m_clk_hw_composite_bus_critical for bus critical clock usage Fixes: 936c383673b9e ("clk: imx: fix composite peripheral flags") Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reported-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1604229834-25594-1-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
f2644bd7 |
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29-Oct-2020 |
Colin Ian King <colin.king@canonical.com> |
clk: imx: remove redundant assignment to pointer np Pointer np is being initialized with a value that is never read and it is being updated with a value later on. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
f1859198 |
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24-Aug-2020 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: Correct the memrepair clock on imx8mp The root clock slice at offset 0xbf80 should be memrepair clock, so correct it. And this clock should be always on to make sure the memory repair function can works well. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
afff77ce |
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24-Aug-2020 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: Correct the root clk of media ldb on imx8mp The root clock slice at 0xbf00 is media_ldb clock, not csi_phy2_ref, so correct it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
9a976cd2 |
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29-Jul-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx8m: Support module build Change configuration to "tristate", add module author, description and license to support building i.MX8M SoCs clock driver as module. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
94ae59ac |
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01-Jun-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8mp: add mu root clk Add mu root clk for mu mailbox usage. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
b1657ad7 |
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06-May-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice Switch the bus clk use imx8m_clk_hw_composite_bus, then we could avoid possible issue when setting mux of the clk. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
8c83a8ff |
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06-May-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk slice. Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
77f5d2d9 |
|
06-May-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8mp: Define gates for pll1/2 fixed dividers Inspried from commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers") On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
dc6e21da |
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06-May-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: imx8mp: fix pll mux bit Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
cccc4647 |
|
06-May-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx8m: drop clk_hw_set_parent for A53 The parent settings have been moved to dtsi, we no need to set parent here. And clk_hw_set_parent will trigger lockdep warning, because this api not have prepare_lock. Reported-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
857c9d31 |
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18-Feb-2020 |
Fugang Duan <fugang.duan@nxp.com> |
clk: imx8mp: Correct the enet_qos parent clock enet_qos is for eqos tsn AXI bus clock whose clock source is from ccm_enet_axi_clk_root, and controlled by CCM_CCGR59(offset 0x43b0) and CCM_CCGR64(offset 0x4400), so correct enet_qos root clock's parent clock to sim_enet. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
78ef3c9e |
|
18-Feb-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx8mp: Correct IMX8MP_CLK_HDMI_AXI clock parent IMX8MP_CLK_HDMI_AXI should be from imx8mp_media_axi_sels instead of imx8mp_media_apb_sels, fix it. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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#
0d77abc4 |
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25-Feb-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx8mp: A53 core clock no need to be critical 'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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7ab22721 |
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19-Feb-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: imx8mp: fix a53 cpu clock The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clk Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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c267bd44 |
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18-Feb-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock On i.MX8MP, internal HDMI 27M clock is actually 24MHz, so rename the IMX8MP_CLK_HDMI_27M to IMX8MP_CLK_HDMI_24M. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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64bee9c6 |
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18-Feb-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx8mp: Include slab.h instead of clkdev.h slab.h is necessary and included indirectly by clkdev.h, actually, there is nothing in use from clkdev.h, so just include slab.h instead of clkdev.h. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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680fbce5 |
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12-Feb-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx8mp: Add missing of_node_put() After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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14875e57 |
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19-Jan-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: imx8mp: add ocotp root clk Add ocotp root clk, then when using nvmem to read fuse, clk could be managed. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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9c140d99 |
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07-Jan-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx: Add support for i.MX8MP clock driver Add clock driver support for i.MX8MP which is a new SoC of i.MX8M family. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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