Searched refs:NUM_FCLK_DPM_LEVELS (Results 1 - 20 of 20) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h102 #define NUM_FCLK_DPM_LEVELS 4 macro
113 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
H A Dsmu11_driver_if.h43 #define NUM_FCLK_DPM_LEVELS 8 macro
58 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
426 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ];
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu14_driver_if_v14_0_0.h106 #define NUM_FCLK_DPM_LEVELS 8 macro
128 uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
129 uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
159 uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
160 uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
H A Dsmu12_driver_if.h107 #define NUM_FCLK_DPM_LEVELS 4 macro
119 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
H A Dsmu11_driver_if_vangogh.h110 #define NUM_FCLK_DPM_LEVELS 4 macro
138 df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
H A Dsmu13_driver_if_aldebaran.h34 #define NUM_FCLK_DPM_LEVELS 8 macro
302 uint32_t FidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
303 uint8_t DidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
H A Dsmu13_driver_if_v13_0_0.h44 #define NUM_FCLK_DPM_LEVELS 8 macro
1051 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1129 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state.
1130 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state.
1131 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state
1411 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
H A Dsmu13_driver_if_v13_0_7.h45 #define NUM_FCLK_DPM_LEVELS 8 macro
1060 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1131 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state.
1132 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state.
1133 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state
1404 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
H A Dsmu11_driver_if_arcturus.h40 #define NUM_FCLK_DPM_LEVELS 8 macro
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
520 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
H A Dsmu_v13_0_6_pmfw.h31 #define NUM_FCLK_DPM_LEVELS 4 macro
H A Dsmu11_driver_if_sienna_cichlid.h48 #define NUM_FCLK_DPM_LEVELS 8 macro
67 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
691 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1051 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h83 #define NUM_FCLK_DPM_LEVELS 8 macro
111 uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
112 uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
H A Ddcn35_clk_mgr.c761 num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS :
821 find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c218 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
228 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
572 count = NUM_FCLK_DPM_LEVELS;
774 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c2183 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2188 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
H A Darcturus_ppt.c1715 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
H A Dsienna_cichlid_ppt.c2748 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3387 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_processpptables.c336 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
H A Dsmu10_hwmgr.c516 NUM_FCLK_DPM_LEVELS,
H A Dvega20_hwmgr.c3609 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS,

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