1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef SMU13_DRIVER_IF_ALDEBARAN_H 25#define SMU13_DRIVER_IF_ALDEBARAN_H 26 27#define SMU13_DRIVER_IF_VERSION_ALDE 0x08 28 29#define NUM_VCLK_DPM_LEVELS 8 30#define NUM_DCLK_DPM_LEVELS 8 31#define NUM_SOCCLK_DPM_LEVELS 8 32#define NUM_LCLK_DPM_LEVELS 8 33#define NUM_UCLK_DPM_LEVELS 4 34#define NUM_FCLK_DPM_LEVELS 8 35#define NUM_XGMI_DPM_LEVELS 4 36 37// Feature Control Defines 38#define FEATURE_DATA_CALCULATIONS 0 39#define FEATURE_DPM_GFXCLK_BIT 1 40#define FEATURE_DPM_UCLK_BIT 2 41#define FEATURE_DPM_SOCCLK_BIT 3 42#define FEATURE_DPM_FCLK_BIT 4 43#define FEATURE_DPM_LCLK_BIT 5 44#define FEATURE_DPM_XGMI_BIT 6 45#define FEATURE_DS_GFXCLK_BIT 7 46#define FEATURE_DS_SOCCLK_BIT 8 47#define FEATURE_DS_LCLK_BIT 9 48#define FEATURE_DS_FCLK_BIT 10 49#define FEATURE_DS_UCLK_BIT 11 50#define FEATURE_GFX_SS_BIT 12 51#define FEATURE_DPM_VCN_BIT 13 52#define FEATURE_RSMU_SMN_CG_BIT 14 53#define FEATURE_WAFL_CG_BIT 15 54#define FEATURE_PPT_BIT 16 55#define FEATURE_TDC_BIT 17 56#define FEATURE_APCC_PLUS_BIT 18 57#define FEATURE_APCC_DFLL_BIT 19 58#define FEATURE_FW_CTF_BIT 20 59#define FEATURE_THERMAL_BIT 21 60#define FEATURE_OUT_OF_BAND_MONITOR_BIT 22 61#define FEATURE_SPARE_23_BIT 23 62#define FEATURE_XGMI_PER_LINK_PWR_DWN 24 63#define FEATURE_DF_CSTATE 25 64#define FEATURE_FUSE_CG_BIT 26 65#define FEATURE_MP1_CG_BIT 27 66#define FEATURE_SMUIO_CG_BIT 28 67#define FEATURE_THM_CG_BIT 29 68#define FEATURE_CLK_CG_BIT 30 69#define FEATURE_EDC_BIT 31 70#define FEATURE_SPARE_32_BIT 32 71#define FEATURE_SPARE_33_BIT 33 72#define FEATURE_SPARE_34_BIT 34 73#define FEATURE_SPARE_35_BIT 35 74#define FEATURE_SPARE_36_BIT 36 75#define FEATURE_SPARE_37_BIT 37 76#define FEATURE_SPARE_38_BIT 38 77#define FEATURE_SPARE_39_BIT 39 78#define FEATURE_SPARE_40_BIT 40 79#define FEATURE_SPARE_41_BIT 41 80#define FEATURE_SPARE_42_BIT 42 81#define FEATURE_SPARE_43_BIT 43 82#define FEATURE_SPARE_44_BIT 44 83#define FEATURE_SPARE_45_BIT 45 84#define FEATURE_SPARE_46_BIT 46 85#define FEATURE_SPARE_47_BIT 47 86#define FEATURE_SPARE_48_BIT 48 87#define FEATURE_SPARE_49_BIT 49 88#define FEATURE_SPARE_50_BIT 50 89#define FEATURE_SPARE_51_BIT 51 90#define FEATURE_SPARE_52_BIT 52 91#define FEATURE_SPARE_53_BIT 53 92#define FEATURE_SPARE_54_BIT 54 93#define FEATURE_SPARE_55_BIT 55 94#define FEATURE_SPARE_56_BIT 56 95#define FEATURE_SPARE_57_BIT 57 96#define FEATURE_SPARE_58_BIT 58 97#define FEATURE_SPARE_59_BIT 59 98#define FEATURE_SPARE_60_BIT 60 99#define FEATURE_SPARE_61_BIT 61 100#define FEATURE_SPARE_62_BIT 62 101#define FEATURE_SPARE_63_BIT 63 102 103#define NUM_FEATURES 64 104 105// I2C Config Bit Defines 106#define I2C_CONTROLLER_ENABLED 1 107#define I2C_CONTROLLER_DISABLED 0 108 109// Throttler Status Bits. 110// These are aligned with the out of band monitor alarm bits for common throttlers 111#define THROTTLER_PPT0_BIT 0 112#define THROTTLER_PPT1_BIT 1 113#define THROTTLER_TDC_GFX_BIT 2 114#define THROTTLER_TDC_SOC_BIT 3 115#define THROTTLER_TDC_HBM_BIT 4 116#define THROTTLER_SPARE_5 5 117#define THROTTLER_TEMP_GPU_BIT 6 118#define THROTTLER_TEMP_MEM_BIT 7 119#define THORTTLER_SPARE_8 8 120#define THORTTLER_SPARE_9 9 121#define THORTTLER_SPARE_10 10 122#define THROTTLER_TEMP_VR_GFX_BIT 11 123#define THROTTLER_TEMP_VR_SOC_BIT 12 124#define THROTTLER_TEMP_VR_MEM_BIT 13 125#define THORTTLER_SPARE_14 14 126#define THORTTLER_SPARE_15 15 127#define THORTTLER_SPARE_16 16 128#define THORTTLER_SPARE_17 17 129#define THORTTLER_SPARE_18 18 130#define THROTTLER_APCC_BIT 19 131 132// Table transfer status 133#define TABLE_TRANSFER_OK 0x0 134#define TABLE_TRANSFER_FAILED 0xFF 135#define TABLE_TRANSFER_PENDING 0xAB 136 137//I2C Interface 138#define NUM_I2C_CONTROLLERS 8 139 140#define I2C_CONTROLLER_ENABLED 1 141#define I2C_CONTROLLER_DISABLED 0 142 143#define MAX_SW_I2C_COMMANDS 24 144 145#define ALDEBARAN_UMC_CHANNEL_NUM 32 146 147typedef enum { 148 I2C_CONTROLLER_PORT_0, //CKSVII2C0 149 I2C_CONTROLLER_PORT_1, //CKSVII2C1 150 I2C_CONTROLLER_PORT_COUNT, 151} I2cControllerPort_e; 152 153typedef enum { 154 I2C_CONTROLLER_THROTTLER_TYPE_NONE, 155 I2C_CONTROLLER_THROTTLER_VR_GFX0, 156 I2C_CONTROLLER_THROTTLER_VR_GFX1, 157 I2C_CONTROLLER_THROTTLER_VR_SOC, 158 I2C_CONTROLLER_THROTTLER_VR_MEM, 159 I2C_CONTROLLER_THROTTLER_COUNT, 160} I2cControllerThrottler_e; 161 162typedef enum { 163 I2C_CONTROLLER_PROTOCOL_VR_MP2855, 164 I2C_CONTROLLER_PROTOCOL_COUNT, 165} I2cControllerProtocol_e; 166 167typedef struct { 168 uint8_t Enabled; 169 uint8_t Speed; 170 uint8_t SlaveAddress; 171 uint8_t ControllerPort; 172 uint8_t ThermalThrotter; 173 uint8_t I2cProtocol; 174 uint8_t PaddingConfig[2]; 175} I2cControllerConfig_t; 176 177typedef enum { 178 I2C_PORT_SVD_SCL, 179 I2C_PORT_GPIO, 180} I2cPort_e; 181 182typedef enum { 183 I2C_SPEED_FAST_50K, //50 Kbits/s 184 I2C_SPEED_FAST_100K, //100 Kbits/s 185 I2C_SPEED_FAST_400K, //400 Kbits/s 186 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 187 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 188 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 189 I2C_SPEED_COUNT, 190} I2cSpeed_e; 191 192typedef enum { 193 I2C_CMD_READ, 194 I2C_CMD_WRITE, 195 I2C_CMD_COUNT, 196} I2cCmdType_e; 197 198#define CMDCONFIG_STOP_BIT 0 199#define CMDCONFIG_RESTART_BIT 1 200#define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 201 202#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 203#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 204#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 205 206typedef struct { 207 uint8_t ReadWriteData; //Return data for read. Data to send for write 208 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 209} SwI2cCmd_t; //SW I2C Command Table 210 211typedef struct { 212 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 213 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 214 uint8_t SlaveAddress; //Slave address of device 215 uint8_t NumCmds; //Number of commands 216 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 217} SwI2cRequest_t; // SW I2C Request Table 218 219typedef struct { 220 SwI2cRequest_t SwI2cRequest; 221 uint32_t Spare[8]; 222 uint32_t MmHubPadding[8]; // SMU internal use 223} SwI2cRequestExternal_t; 224 225typedef struct { 226 uint32_t a; // store in IEEE float format in this variable 227 uint32_t b; // store in IEEE float format in this variable 228 uint32_t c; // store in IEEE float format in this variable 229} QuadraticInt_t; 230 231typedef struct { 232 uint32_t m; // store in IEEE float format in this variable 233 uint32_t b; // store in IEEE float format in this variable 234} LinearInt_t; 235 236typedef enum { 237 GFXCLK_SOURCE_PLL, 238 GFXCLK_SOURCE_DFLL, 239 GFXCLK_SOURCE_COUNT, 240} GfxclkSrc_e; 241 242typedef enum { 243 PPCLK_GFXCLK, 244 PPCLK_VCLK, 245 PPCLK_DCLK, 246 PPCLK_SOCCLK, 247 PPCLK_UCLK, 248 PPCLK_FCLK, 249 PPCLK_LCLK, 250 PPCLK_COUNT, 251} PPCLK_e; 252 253typedef enum { 254 GPIO_INT_POLARITY_ACTIVE_LOW, 255 GPIO_INT_POLARITY_ACTIVE_HIGH, 256} GpioIntPolarity_e; 257 258//PPSMC_MSG_SetUclkDpmMode 259typedef enum { 260 UCLK_DPM_MODE_BANDWIDTH, 261 UCLK_DPM_MODE_LATENCY, 262} UCLK_DPM_MODE_e; 263 264typedef struct { 265 uint8_t StartupLevel; 266 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 267 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 268 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 269 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 270} DpmDescriptor_t; 271 272#pragma pack(push, 1) 273typedef struct { 274 uint32_t Version; 275 276 // SECTION: Feature Enablement 277 uint32_t FeaturesToRun[2]; 278 279 // SECTION: Infrastructure Limits 280 uint16_t PptLimit; // Watts 281 uint16_t TdcLimitGfx; // Amps 282 uint16_t TdcLimitSoc; // Amps 283 uint16_t TdcLimitHbm; // Amps 284 uint16_t ThotspotLimit; // Celcius 285 uint16_t TmemLimit; // Celcius 286 uint16_t Tvr_gfxLimit; // Celcius 287 uint16_t Tvr_memLimit; // Celcius 288 uint16_t Tvr_socLimit; // Celcius 289 uint16_t PaddingLimit; 290 291 // SECTION: Voltage Control Parameters 292 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 293 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 294 295 //SECTION: DPM Config 1 296 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 297 298 uint8_t DidTableVclk[NUM_VCLK_DPM_LEVELS]; //PPCLK_VCLK 299 uint8_t DidTableDclk[NUM_DCLK_DPM_LEVELS]; //PPCLK_DCLK 300 uint8_t DidTableSocclk[NUM_SOCCLK_DPM_LEVELS]; //PPCLK_SOCCLK 301 uint8_t DidTableLclk[NUM_LCLK_DPM_LEVELS]; //PPCLK_LCLK 302 uint32_t FidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK 303 uint8_t DidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK 304 uint32_t FidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK 305 uint8_t DidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK 306 307 uint32_t StartupFidPll0; //GFXAVFSCLK, SOCCLK, MP0CLK, MPIOCLK, DXIOCLK 308 uint32_t StartupFidPll4; //VCLK, DCLK, WAFLCLK 309 uint32_t StartupFidPll5; //SMNCLK, MP1CLK, LCLK 310 311 uint8_t StartupSmnclkDid; 312 uint8_t StartupMp0clkDid; 313 uint8_t StartupMp1clkDid; 314 uint8_t StartupWaflclkDid; 315 uint8_t StartupGfxavfsclkDid; 316 uint8_t StartupMpioclkDid; 317 uint8_t StartupDxioclkDid; 318 uint8_t spare123; 319 320 uint8_t StartupVidGpu0Svi0Plane0; //VDDCR_GFX0 321 uint8_t StartupVidGpu0Svi0Plane1; //VDDCR_SOC 322 uint8_t StartupVidGpu0Svi1Plane0; //VDDCR_HBM 323 uint8_t StartupVidGpu0Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed] 324 325 uint8_t StartupVidGpu1Svi0Plane0; //VDDCR_GFX1 326 uint8_t StartupVidGpu1Svi0Plane1; //UNUSED [0 = plane is not used and should not be programmed] 327 uint8_t StartupVidGpu1Svi1Plane0; //UNUSED [0 = plane is not used and should not be programmed] 328 uint8_t StartupVidGpu1Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed] 329 330 // GFXCLK DPM 331 uint16_t GfxclkFmax; // In MHz 332 uint16_t GfxclkFmin; // In MHz 333 uint16_t GfxclkFidle; // In MHz 334 uint16_t GfxclkFinit; // In MHz 335 uint8_t GfxclkSource; // GfxclkSrc_e [0 = PLL, 1 = DFLL] 336 uint8_t spare1[2]; 337 uint8_t StartupGfxclkDid; 338 uint32_t StartupGfxclkFid; 339 340 // SECTION: AVFS 341 uint16_t GFX_Guardband_Freq[8]; // MHz [unsigned] 342 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed] 343 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed] 344 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed] 345 346 uint16_t SOC_Guardband_Freq[8]; // MHz [unsigned] 347 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed] 348 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed] 349 int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed] 350 351 // VDDCR_GFX BTC 352 uint16_t DcBtcEnabled; 353 int16_t DcBtcMin; // mV [signed] 354 int16_t DcBtcMax; // mV [signed] 355 int16_t DcBtcGb; // mV [signed] 356 357 // SECTION: XGMI 358 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps] 359 uint8_t XgmiLinkWidth[NUM_XGMI_DPM_LEVELS]; //Width [EX: 16 = x16] 360 uint8_t XgmiStartupLevel; 361 uint8_t spare12[3]; 362 363 // GFX Vmin 364 uint16_t GFX_PPVmin_Enabled; 365 uint16_t GFX_Vmin_Plat_Offset_Hot; // mV 366 uint16_t GFX_Vmin_Plat_Offset_Cold; // mV 367 uint16_t GFX_Vmin_Hot_T0; // mV 368 uint16_t GFX_Vmin_Cold_T0; // mV 369 uint16_t GFX_Vmin_Hot_Eol; // mV 370 uint16_t GFX_Vmin_Cold_Eol; // mV 371 uint16_t GFX_Vmin_Aging_Offset; // mV 372 uint16_t GFX_Vmin_Temperature_Hot; // 'C 373 uint16_t GFX_Vmin_Temperature_Cold; // 'C 374 375 // SOC Vmin 376 uint16_t SOC_PPVmin_Enabled; 377 uint16_t SOC_Vmin_Plat_Offset_Hot; // mV 378 uint16_t SOC_Vmin_Plat_Offset_Cold; // mV 379 uint16_t SOC_Vmin_Hot_T0; // mV 380 uint16_t SOC_Vmin_Cold_T0; // mV 381 uint16_t SOC_Vmin_Hot_Eol; // mV 382 uint16_t SOC_Vmin_Cold_Eol; // mV 383 uint16_t SOC_Vmin_Aging_Offset; // mV 384 uint16_t SOC_Vmin_Temperature_Hot; // 'C 385 uint16_t SOC_Vmin_Temperature_Cold; // 'C 386 387 // APCC Settings 388 uint32_t ApccPlusResidencyLimit; //PCC residency % (0-100) 389 390 // Determinism 391 uint16_t DeterminismVoltageOffset; //mV 392 uint16_t spare22; 393 394 // reserved 395 uint32_t spare3[14]; 396 397 // SECTION: BOARD PARAMETERS 398 // Telemetry Settings 399 uint16_t GfxMaxCurrent; // in Amps 400 int8_t GfxOffset; // in Amps 401 uint8_t Padding_TelemetryGfx; 402 403 uint16_t SocMaxCurrent; // in Amps 404 int8_t SocOffset; // in Amps 405 uint8_t Padding_TelemetrySoc; 406 407 uint16_t MemMaxCurrent; // in Amps 408 int8_t MemOffset; // in Amps 409 uint8_t Padding_TelemetryMem; 410 411 uint16_t BoardMaxCurrent; // in Amps 412 int8_t BoardOffset; // in Amps 413 uint8_t Padding_TelemetryBoardInput; 414 415 // Platform input telemetry voltage coefficient 416 uint32_t BoardVoltageCoeffA; // decode by /1000 417 uint32_t BoardVoltageCoeffB; // decode by /1000 418 419 // GPIO Settings 420 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 421 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 422 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 423 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 424 425 // UCLK Spread Spectrum 426 uint8_t UclkSpreadEnabled; // on or off 427 uint8_t UclkSpreadPercent; // Q4.4 428 uint16_t UclkSpreadFreq; // kHz 429 430 // FCLK Spread Spectrum 431 uint8_t FclkSpreadEnabled; // on or off 432 uint8_t FclkSpreadPercent; // Q4.4 433 uint16_t FclkSpreadFreq; // kHz 434 435 // I2C Controller Structure 436 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 437 438 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 439 uint8_t GpioI2cScl; // Serial Clock 440 uint8_t GpioI2cSda; // Serial Data 441 uint16_t spare5; 442 443 uint16_t XgmiMaxCurrent; // in Amps 444 int8_t XgmiOffset; // in Amps 445 uint8_t Padding_TelemetryXgmi; 446 447 uint16_t EdcPowerLimit; 448 uint16_t spare6; 449 450 //reserved 451 uint32_t reserved[14]; 452 453} PPTable_t; 454#pragma pack(pop) 455 456typedef struct { 457 // Time constant parameters for clock averages in ms 458 uint16_t GfxclkAverageLpfTau; 459 uint16_t SocclkAverageLpfTau; 460 uint16_t UclkAverageLpfTau; 461 uint16_t GfxActivityLpfTau; 462 uint16_t UclkActivityLpfTau; 463 464 uint16_t SocketPowerLpfTau; 465 466 uint32_t Spare[8]; 467 // Padding - ignore 468 uint32_t MmHubPadding[8]; // SMU internal use 469} DriverSmuConfig_t; 470 471typedef struct { 472 uint16_t CurrClock[PPCLK_COUNT]; 473 uint16_t Padding1 ; 474 uint16_t AverageGfxclkFrequency; 475 uint16_t AverageSocclkFrequency; 476 uint16_t AverageUclkFrequency ; 477 uint16_t AverageGfxActivity ; 478 uint16_t AverageUclkActivity ; 479 uint8_t CurrSocVoltageOffset ; 480 uint8_t CurrGfxVoltageOffset ; 481 uint8_t CurrMemVidOffset ; 482 uint8_t Padding8 ; 483 uint16_t AverageSocketPower ; 484 uint16_t TemperatureEdge ; 485 uint16_t TemperatureHotspot ; 486 uint16_t TemperatureHBM ; // Max 487 uint16_t TemperatureVrGfx ; 488 uint16_t TemperatureVrSoc ; 489 uint16_t TemperatureVrMem ; 490 uint32_t ThrottlerStatus ; 491 492 uint32_t PublicSerialNumLower32; 493 uint32_t PublicSerialNumUpper32; 494 uint16_t TemperatureAllHBM[4] ; 495 uint32_t GfxBusyAcc ; 496 uint32_t DramBusyAcc ; 497 uint32_t EnergyAcc64bitLow ; //15.259uJ resolution 498 uint32_t EnergyAcc64bitHigh ; 499 uint32_t TimeStampLow ; //10ns resolution 500 uint32_t TimeStampHigh ; 501 502 // Padding - ignore 503 uint32_t MmHubPadding[8]; // SMU internal use 504} SmuMetrics_t; 505 506 507typedef struct { 508 uint16_t avgPsmCount[76]; 509 uint16_t minPsmCount[76]; 510 float avgPsmVoltage[76]; 511 float minPsmVoltage[76]; 512 513 uint32_t MmHubPadding[8]; // SMU internal use 514} AvfsDebugTable_t; 515 516typedef struct { 517 uint64_t mca_umc_status; 518 uint64_t mca_umc_addr; 519 uint16_t ce_count_lo_chip; 520 uint16_t ce_count_hi_chip; 521 522 uint32_t eccPadding; 523} EccInfo_t; 524 525typedef struct { 526 uint64_t mca_umc_status; 527 uint64_t mca_umc_addr; 528 529 uint16_t ce_count_lo_chip; 530 uint16_t ce_count_hi_chip; 531 532 uint32_t eccPadding; 533 534 uint64_t mca_ceumc_addr; 535} EccInfo_V2_t; 536 537typedef struct { 538 union { 539 EccInfo_t EccInfo[ALDEBARAN_UMC_CHANNEL_NUM]; 540 EccInfo_V2_t EccInfo_V2[ALDEBARAN_UMC_CHANNEL_NUM]; 541 }; 542} EccInfoTable_t; 543 544// These defines are used with the following messages: 545// SMC_MSG_TransferTableDram2Smu 546// SMC_MSG_TransferTableSmu2Dram 547#define TABLE_PPTABLE 0 548#define TABLE_AVFS_PSM_DEBUG 1 549#define TABLE_AVFS_FUSE_OVERRIDE 2 550#define TABLE_PMSTATUSLOG 3 551#define TABLE_SMU_METRICS 4 552#define TABLE_DRIVER_SMU_CONFIG 5 553#define TABLE_I2C_COMMANDS 6 554#define TABLE_ECCINFO 7 555#define TABLE_COUNT 8 556 557#endif 558