1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef SMU13_DRIVER_IF_SMU_13_0_7_H 24#define SMU13_DRIVER_IF_SMU_13_0_7_H 25 26// *** IMPORTANT *** 27// PMFW TEAM: Always increment the interface version on any change to this file 28#define SMU13_0_7_DRIVER_IF_VERSION 0x35 29 30//Increment this version if SkuTable_t or BoardTable_t change 31#define PPTABLE_VERSION 0x27 32 33#define NUM_GFXCLK_DPM_LEVELS 16 34#define NUM_SOCCLK_DPM_LEVELS 8 35#define NUM_MP0CLK_DPM_LEVELS 2 36#define NUM_DCLK_DPM_LEVELS 8 37#define NUM_VCLK_DPM_LEVELS 8 38#define NUM_DISPCLK_DPM_LEVELS 8 39#define NUM_DPPCLK_DPM_LEVELS 8 40#define NUM_DPREFCLK_DPM_LEVELS 8 41#define NUM_DCFCLK_DPM_LEVELS 8 42#define NUM_DTBCLK_DPM_LEVELS 8 43#define NUM_UCLK_DPM_LEVELS 4 44#define NUM_LINK_LEVELS 3 45#define NUM_FCLK_DPM_LEVELS 8 46#define NUM_OD_FAN_MAX_POINTS 6 47 48// Feature Control Defines 49#define FEATURE_FW_DATA_READ_BIT 0 50#define FEATURE_DPM_GFXCLK_BIT 1 51#define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 52#define FEATURE_DPM_UCLK_BIT 3 53#define FEATURE_DPM_FCLK_BIT 4 54#define FEATURE_DPM_SOCCLK_BIT 5 55#define FEATURE_DPM_MP0CLK_BIT 6 56#define FEATURE_DPM_LINK_BIT 7 57#define FEATURE_DPM_DCN_BIT 8 58#define FEATURE_VMEMP_SCALING_BIT 9 59#define FEATURE_VDDIO_MEM_SCALING_BIT 10 60#define FEATURE_DS_GFXCLK_BIT 11 61#define FEATURE_DS_SOCCLK_BIT 12 62#define FEATURE_DS_FCLK_BIT 13 63#define FEATURE_DS_LCLK_BIT 14 64#define FEATURE_DS_DCFCLK_BIT 15 65#define FEATURE_DS_UCLK_BIT 16 66#define FEATURE_GFX_ULV_BIT 17 67#define FEATURE_FW_DSTATE_BIT 18 68#define FEATURE_GFXOFF_BIT 19 69#define FEATURE_BACO_BIT 20 70#define FEATURE_MM_DPM_BIT 21 71#define FEATURE_SOC_MPCLK_DS_BIT 22 72#define FEATURE_BACO_MPCLK_DS_BIT 23 73#define FEATURE_THROTTLERS_BIT 24 74#define FEATURE_SMARTSHIFT_BIT 25 75#define FEATURE_GTHR_BIT 26 76#define FEATURE_ACDC_BIT 27 77#define FEATURE_VR0HOT_BIT 28 78#define FEATURE_FW_CTF_BIT 29 79#define FEATURE_FAN_CONTROL_BIT 30 80#define FEATURE_GFX_DCS_BIT 31 81#define FEATURE_GFX_READ_MARGIN_BIT 32 82#define FEATURE_LED_DISPLAY_BIT 33 83#define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 84#define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 85#define FEATURE_OPTIMIZED_VMIN_BIT 36 86#define FEATURE_GFX_IMU_BIT 37 87#define FEATURE_BOOT_TIME_CAL_BIT 38 88#define FEATURE_GFX_PCC_DFLL_BIT 39 89#define FEATURE_SOC_CG_BIT 40 90#define FEATURE_DF_CSTATE_BIT 41 91#define FEATURE_GFX_EDC_BIT 42 92#define FEATURE_BOOT_POWER_OPT_BIT 43 93#define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 94#define FEATURE_DS_VCN_BIT 45 95#define FEATURE_BACO_CG_BIT 46 96#define FEATURE_MEM_TEMP_READ_BIT 47 97#define FEATURE_ATHUB_MMHUB_PG_BIT 48 98#define FEATURE_SOC_PCC_BIT 49 99#define FEATURE_EDC_PWRBRK_BIT 50 100#define FEATURE_SPARE_51_BIT 51 101#define FEATURE_SPARE_52_BIT 52 102#define FEATURE_SPARE_53_BIT 53 103#define FEATURE_SPARE_54_BIT 54 104#define FEATURE_SPARE_55_BIT 55 105#define FEATURE_SPARE_56_BIT 56 106#define FEATURE_SPARE_57_BIT 57 107#define FEATURE_SPARE_58_BIT 58 108#define FEATURE_SPARE_59_BIT 59 109#define FEATURE_SPARE_60_BIT 60 110#define FEATURE_SPARE_61_BIT 61 111#define FEATURE_SPARE_62_BIT 62 112#define FEATURE_SPARE_63_BIT 63 113#define NUM_FEATURES 64 114 115#define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 116#define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \ 117 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 118 (1 << FEATURE_DPM_UCLK_BIT) | \ 119 (1 << FEATURE_DPM_FCLK_BIT) | \ 120 (1 << FEATURE_DPM_SOCCLK_BIT) | \ 121 (1 << FEATURE_DPM_MP0CLK_BIT) | \ 122 (1 << FEATURE_DPM_LINK_BIT) | \ 123 (1 << FEATURE_DPM_DCN_BIT) | \ 124 (1 << FEATURE_DS_GFXCLK_BIT) | \ 125 (1 << FEATURE_DS_SOCCLK_BIT) | \ 126 (1 << FEATURE_DS_FCLK_BIT) | \ 127 (1 << FEATURE_DS_LCLK_BIT) | \ 128 (1 << FEATURE_DS_DCFCLK_BIT) | \ 129 (1 << FEATURE_DS_UCLK_BIT) | \ 130 (1ULL << FEATURE_DS_VCN_BIT)) 131 132//For use with feature control messages 133typedef enum { 134 FEATURE_PWR_ALL, 135 FEATURE_PWR_S5, 136 FEATURE_PWR_BACO, 137 FEATURE_PWR_SOC, 138 FEATURE_PWR_GFX, 139 FEATURE_PWR_DOMAIN_COUNT, 140} FEATURE_PWR_DOMAIN_e; 141 142 143// Debug Overrides Bitmask 144#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 145#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 146#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 147#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 148#define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 149#define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 150#define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 151#define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 152#define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 153#define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 154#define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 155#define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 156#define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 157 158// VR Mapping Bit Defines 159#define VR_MAPPING_VR_SELECT_MASK 0x01 160#define VR_MAPPING_VR_SELECT_SHIFT 0x00 161 162#define VR_MAPPING_PLANE_SELECT_MASK 0x02 163#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 164 165// PSI Bit Defines 166#define PSI_SEL_VR0_PLANE0_PSI0 0x01 167#define PSI_SEL_VR0_PLANE0_PSI1 0x02 168#define PSI_SEL_VR0_PLANE1_PSI0 0x04 169#define PSI_SEL_VR0_PLANE1_PSI1 0x08 170#define PSI_SEL_VR1_PLANE0_PSI0 0x10 171#define PSI_SEL_VR1_PLANE0_PSI1 0x20 172#define PSI_SEL_VR1_PLANE1_PSI0 0x40 173#define PSI_SEL_VR1_PLANE1_PSI1 0x80 174 175typedef enum { 176 SVI_PSI_0, // Full phase count (default) 177 SVI_PSI_1, // Phase count 1st level 178 SVI_PSI_2, // Phase count 2nd level 179 SVI_PSI_3, // Single phase operation + active diode emulation 180 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 181 SVI_PSI_5, // Reserved 182 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 183 SVI_PSI_7, // Automated phase shedding and diode emulation 184} SVI_PSI_e; 185 186// Throttler Control/Status Bits 187#define THROTTLER_TEMP_EDGE_BIT 0 188#define THROTTLER_TEMP_HOTSPOT_BIT 1 189#define THROTTLER_TEMP_HOTSPOT_G_BIT 2 190#define THROTTLER_TEMP_HOTSPOT_M_BIT 3 191#define THROTTLER_TEMP_MEM_BIT 4 192#define THROTTLER_TEMP_VR_GFX_BIT 5 193#define THROTTLER_TEMP_VR_MEM0_BIT 6 194#define THROTTLER_TEMP_VR_MEM1_BIT 7 195#define THROTTLER_TEMP_VR_SOC_BIT 8 196#define THROTTLER_TEMP_VR_U_BIT 9 197#define THROTTLER_TEMP_LIQUID0_BIT 10 198#define THROTTLER_TEMP_LIQUID1_BIT 11 199#define THROTTLER_TEMP_PLX_BIT 12 200#define THROTTLER_TDC_GFX_BIT 13 201#define THROTTLER_TDC_SOC_BIT 14 202#define THROTTLER_TDC_U_BIT 15 203#define THROTTLER_PPT0_BIT 16 204#define THROTTLER_PPT1_BIT 17 205#define THROTTLER_PPT2_BIT 18 206#define THROTTLER_PPT3_BIT 19 207#define THROTTLER_FIT_BIT 20 208#define THROTTLER_GFX_APCC_PLUS_BIT 21 209#define THROTTLER_COUNT 22 210 211// FW DState Features Control Bits 212#define FW_DSTATE_SOC_ULV_BIT 0 213#define FW_DSTATE_G6_HSR_BIT 1 214#define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 215#define FW_DSTATE_SMN_DS_BIT 3 216#define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 217#define FW_DSTATE_SOC_LIV_MIN_BIT 5 218#define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 219#define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 220#define FW_DSTATE_MALL_ALLOC_BIT 8 221#define FW_DSTATE_MEM_PSI_BIT 9 222#define FW_DSTATE_HSR_NON_STROBE_BIT 10 223#define FW_DSTATE_MP0_ENTER_WFI_BIT 11 224#define FW_DSTATE_U_ULV_BIT 12 225#define FW_DSTATE_MALL_FLUSH_BIT 13 226#define FW_DSTATE_SOC_PSI_BIT 14 227#define FW_DSTATE_U_PSI_BIT 15 228#define FW_DSTATE_UCP_DS_BIT 16 229#define FW_DSTATE_CSRCLK_DS_BIT 17 230#define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 231#define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 232#define FW_DSTATE_CLDO_PRG_BIT 20 233#define FW_DSTATE_DF_PLL_PWRDN_BIT 21 234#define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 235#define FW_DSTATE_GFX_PSI6_BIT 23 236#define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 237 238//LED Display Mask & Control Bits 239#define LED_DISPLAY_GFX_DPM_BIT 0 240#define LED_DISPLAY_PCIE_BIT 1 241#define LED_DISPLAY_ERROR_BIT 2 242 243 244#define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 245#define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 246#define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 247 248typedef enum { 249 SMARTSHIFT_VERSION_1, 250 SMARTSHIFT_VERSION_2, 251 SMARTSHIFT_VERSION_3, 252} SMARTSHIFT_VERSION_e; 253 254typedef enum { 255 FOPT_CALC_AC_CALC_DC, 256 FOPT_PPTABLE_AC_CALC_DC, 257 FOPT_CALC_AC_PPTABLE_DC, 258 FOPT_PPTABLE_AC_PPTABLE_DC, 259} FOPT_CALC_e; 260 261typedef enum { 262 DRAM_BIT_WIDTH_DISABLED = 0, 263 DRAM_BIT_WIDTH_X_8 = 8, 264 DRAM_BIT_WIDTH_X_16 = 16, 265 DRAM_BIT_WIDTH_X_32 = 32, 266 DRAM_BIT_WIDTH_X_64 = 64, 267 DRAM_BIT_WIDTH_X_128 = 128, 268 DRAM_BIT_WIDTH_COUNT, 269} DRAM_BIT_WIDTH_TYPE_e; 270 271//I2C Interface 272#define NUM_I2C_CONTROLLERS 8 273 274#define I2C_CONTROLLER_ENABLED 1 275#define I2C_CONTROLLER_DISABLED 0 276 277#define MAX_SW_I2C_COMMANDS 24 278 279typedef enum { 280 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 281 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 282 I2C_CONTROLLER_PORT_COUNT, 283} I2cControllerPort_e; 284 285typedef enum { 286 I2C_CONTROLLER_NAME_VR_GFX = 0, 287 I2C_CONTROLLER_NAME_VR_SOC, 288 I2C_CONTROLLER_NAME_VR_VMEMP, 289 I2C_CONTROLLER_NAME_VR_VDDIO, 290 I2C_CONTROLLER_NAME_LIQUID0, 291 I2C_CONTROLLER_NAME_LIQUID1, 292 I2C_CONTROLLER_NAME_PLX, 293 I2C_CONTROLLER_NAME_FAN_INTAKE, 294 I2C_CONTROLLER_NAME_COUNT, 295} I2cControllerName_e; 296 297typedef enum { 298 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 299 I2C_CONTROLLER_THROTTLER_VR_GFX, 300 I2C_CONTROLLER_THROTTLER_VR_SOC, 301 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 302 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 303 I2C_CONTROLLER_THROTTLER_LIQUID0, 304 I2C_CONTROLLER_THROTTLER_LIQUID1, 305 I2C_CONTROLLER_THROTTLER_PLX, 306 I2C_CONTROLLER_THROTTLER_FAN_INTAKE, 307 I2C_CONTROLLER_THROTTLER_INA3221, 308 I2C_CONTROLLER_THROTTLER_COUNT, 309} I2cControllerThrottler_e; 310 311typedef enum { 312 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 313 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 314 I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, 315 I2C_CONTROLLER_PROTOCOL_INA3221, 316 I2C_CONTROLLER_PROTOCOL_TMP_MAX6604, 317 I2C_CONTROLLER_PROTOCOL_COUNT, 318} I2cControllerProtocol_e; 319 320typedef struct { 321 uint8_t Enabled; 322 uint8_t Speed; 323 uint8_t SlaveAddress; 324 uint8_t ControllerPort; 325 uint8_t ControllerName; 326 uint8_t ThermalThrotter; 327 uint8_t I2cProtocol; 328 uint8_t PaddingConfig; 329} I2cControllerConfig_t; 330 331typedef enum { 332 I2C_PORT_SVD_SCL = 0, 333 I2C_PORT_GPIO, 334} I2cPort_e; 335 336typedef enum { 337 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 338 I2C_SPEED_FAST_100K, //100 Kbits/s 339 I2C_SPEED_FAST_400K, //400 Kbits/s 340 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 341 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 342 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 343 I2C_SPEED_COUNT, 344} I2cSpeed_e; 345 346typedef enum { 347 I2C_CMD_READ = 0, 348 I2C_CMD_WRITE, 349 I2C_CMD_COUNT, 350} I2cCmdType_e; 351 352#define CMDCONFIG_STOP_BIT 0 353#define CMDCONFIG_RESTART_BIT 1 354#define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 355 356#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 357#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 358#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 359 360typedef struct { 361 uint8_t ReadWriteData; //Return data for read. Data to send for write 362 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 363} SwI2cCmd_t; //SW I2C Command Table 364 365typedef struct { 366 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 367 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 368 uint8_t SlaveAddress; //Slave address of device 369 uint8_t NumCmds; //Number of commands 370 371 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 372} SwI2cRequest_t; // SW I2C Request Table 373 374typedef struct { 375 SwI2cRequest_t SwI2cRequest; 376 377 uint32_t Spare[8]; 378 uint32_t MmHubPadding[8]; // SMU internal use 379} SwI2cRequestExternal_t; 380 381typedef struct { 382 uint64_t mca_umc_status; 383 uint64_t mca_umc_addr; 384 385 uint16_t ce_count_lo_chip; 386 uint16_t ce_count_hi_chip; 387 388 uint32_t eccPadding; 389} EccInfo_t; 390 391typedef struct { 392 EccInfo_t EccInfo[24]; 393} EccInfoTable_t; 394 395//D3HOT sequences 396typedef enum { 397 BACO_SEQUENCE, 398 MSR_SEQUENCE, 399 BAMACO_SEQUENCE, 400 ULPS_SEQUENCE, 401 D3HOT_SEQUENCE_COUNT, 402} D3HOTSequence_e; 403 404//This is aligned with RSMU PGFSM Register Mapping 405typedef enum { 406 PG_DYNAMIC_MODE = 0, 407 PG_STATIC_MODE, 408} PowerGatingMode_e; 409 410//This is aligned with RSMU PGFSM Register Mapping 411typedef enum { 412 PG_POWER_DOWN = 0, 413 PG_POWER_UP, 414} PowerGatingSettings_e; 415 416typedef struct { 417 uint32_t a; // store in IEEE float format in this variable 418 uint32_t b; // store in IEEE float format in this variable 419 uint32_t c; // store in IEEE float format in this variable 420} QuadraticInt_t; 421 422typedef struct { 423 uint32_t m; // store in IEEE float format in this variable 424 uint32_t b; // store in IEEE float format in this variable 425} LinearInt_t; 426 427typedef struct { 428 uint32_t a; // store in IEEE float format in this variable 429 uint32_t b; // store in IEEE float format in this variable 430 uint32_t c; // store in IEEE float format in this variable 431} DroopInt_t; 432 433typedef enum { 434 DCS_ARCH_DISABLED, 435 DCS_ARCH_FADCS, 436 DCS_ARCH_ASYNC, 437} DCS_ARCH_e; 438 439//Only Clks that have DPM descriptors are listed here 440typedef enum { 441 PPCLK_GFXCLK = 0, 442 PPCLK_SOCCLK, 443 PPCLK_UCLK, 444 PPCLK_FCLK, 445 PPCLK_DCLK_0, 446 PPCLK_VCLK_0, 447 PPCLK_DCLK_1, 448 PPCLK_VCLK_1, 449 PPCLK_DISPCLK, 450 PPCLK_DPPCLK, 451 PPCLK_DPREFCLK, 452 PPCLK_DCFCLK, 453 PPCLK_DTBCLK, 454 PPCLK_COUNT, 455} PPCLK_e; 456 457typedef enum { 458 VOLTAGE_MODE_PPTABLE = 0, 459 VOLTAGE_MODE_FUSES, 460 VOLTAGE_MODE_COUNT, 461} VOLTAGE_MODE_e; 462 463 464typedef enum { 465 AVFS_VOLTAGE_GFX = 0, 466 AVFS_VOLTAGE_SOC, 467 AVFS_VOLTAGE_COUNT, 468} AVFS_VOLTAGE_TYPE_e; 469 470typedef enum { 471 AVFS_TEMP_COLD = 0, 472 AVFS_TEMP_HOT, 473 AVFS_TEMP_COUNT, 474} AVFS_TEMP_e; 475 476typedef enum { 477 AVFS_D_G, 478 AVFS_D_M_B, 479 AVFS_D_M_S, 480 AVFS_D_COUNT, 481} AVFS_D_e; 482 483typedef enum { 484 UCLK_DIV_BY_1 = 0, 485 UCLK_DIV_BY_2, 486 UCLK_DIV_BY_4, 487 UCLK_DIV_BY_8, 488} UCLK_DIV_e; 489 490typedef enum { 491 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 492 GPIO_INT_POLARITY_ACTIVE_HIGH, 493} GpioIntPolarity_e; 494 495typedef enum { 496 PWR_CONFIG_TDP = 0, 497 PWR_CONFIG_TGP, 498 PWR_CONFIG_TCP_ESTIMATED, 499 PWR_CONFIG_TCP_MEASURED, 500} PwrConfig_e; 501 502typedef struct { 503 uint8_t Padding; 504 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 505 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 506 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 507 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 508 uint32_t Padding3[3]; 509 uint16_t Padding4; 510 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 511 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 512 uint16_t Padding2; 513} DpmDescriptor_t; 514 515typedef enum { 516 PPT_THROTTLER_PPT0, 517 PPT_THROTTLER_PPT1, 518 PPT_THROTTLER_PPT2, 519 PPT_THROTTLER_PPT3, 520 PPT_THROTTLER_COUNT 521} PPT_THROTTLER_e; 522 523typedef enum { 524 TEMP_EDGE, 525 TEMP_HOTSPOT, 526 TEMP_HOTSPOT_G, 527 TEMP_HOTSPOT_M, 528 TEMP_MEM, 529 TEMP_VR_GFX, 530 TEMP_VR_MEM0, 531 TEMP_VR_MEM1, 532 TEMP_VR_SOC, 533 TEMP_VR_U, 534 TEMP_LIQUID0, 535 TEMP_LIQUID1, 536 TEMP_PLX, 537 TEMP_COUNT, 538} TEMP_e; 539 540typedef enum { 541 TDC_THROTTLER_GFX, 542 TDC_THROTTLER_SOC, 543 TDC_THROTTLER_U, 544 TDC_THROTTLER_COUNT 545} TDC_THROTTLER_e; 546 547typedef enum { 548 SVI_PLANE_GFX, 549 SVI_PLANE_SOC, 550 SVI_PLANE_VMEMP, 551 SVI_PLANE_VDDIO_MEM, 552 SVI_PLANE_U, 553 SVI_PLANE_COUNT, 554} SVI_PLANE_e; 555 556typedef enum { 557 PMFW_VOLT_PLANE_GFX, 558 PMFW_VOLT_PLANE_SOC, 559 PMFW_VOLT_PLANE_COUNT 560} PMFW_VOLT_PLANE_e; 561 562typedef enum { 563 CUSTOMER_VARIANT_ROW, 564 CUSTOMER_VARIANT_FALCON, 565 CUSTOMER_VARIANT_COUNT, 566} CUSTOMER_VARIANT_e; 567 568typedef enum { 569 POWER_SOURCE_AC, 570 POWER_SOURCE_DC, 571 POWER_SOURCE_COUNT, 572} POWER_SOURCE_e; 573 574typedef enum { 575 MEM_VENDOR_SAMSUNG, 576 MEM_VENDOR_INFINEON, 577 MEM_VENDOR_ELPIDA, 578 MEM_VENDOR_ETRON, 579 MEM_VENDOR_NANYA, 580 MEM_VENDOR_HYNIX, 581 MEM_VENDOR_MOSEL, 582 MEM_VENDOR_WINBOND, 583 MEM_VENDOR_ESMT, 584 MEM_VENDOR_PLACEHOLDER0, 585 MEM_VENDOR_PLACEHOLDER1, 586 MEM_VENDOR_PLACEHOLDER2, 587 MEM_VENDOR_PLACEHOLDER3, 588 MEM_VENDOR_PLACEHOLDER4, 589 MEM_VENDOR_PLACEHOLDER5, 590 MEM_VENDOR_MICRON, 591 MEM_VENDOR_COUNT, 592} MEM_VENDOR_e; 593 594typedef enum { 595 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 596 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 597 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 598 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 599 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 600 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 601 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 602 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 603 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 604 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 605 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 606 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 607 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 608 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 609 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 610 PP_GRTAVFS_HW_ZONE0_VF, 611 PP_GRTAVFS_HW_ZONE1_VF1, 612 PP_GRTAVFS_HW_ZONE2_VF2, 613 PP_GRTAVFS_HW_ZONE3_VF3, 614 PP_GRTAVFS_HW_VOLTAGE_GB, 615 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 616 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 617 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 618 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 619 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 620 PP_GRTAVFS_HW_RESERVED_0, 621 PP_GRTAVFS_HW_RESERVED_1, 622 PP_GRTAVFS_HW_RESERVED_2, 623 PP_GRTAVFS_HW_RESERVED_3, 624 PP_GRTAVFS_HW_RESERVED_4, 625 PP_GRTAVFS_HW_RESERVED_5, 626 PP_GRTAVFS_HW_RESERVED_6, 627 PP_GRTAVFS_HW_FUSE_COUNT, 628} PP_GRTAVFS_HW_FUSE_e; 629 630typedef enum { 631 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 632 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 633 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 634 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 635 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 636 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 637 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 638 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 639 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 640 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 641 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 642 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 643 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 644 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 645} PP_GRTAVFS_FW_COMMON_FUSE_e; 646 647typedef enum { 648 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 649 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 650 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 651 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 652 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 653 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 654 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 655 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 656 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 657 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 658 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 659 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 660 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 661 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 662 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 663 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 664 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 665 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 666 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 667 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 668} PP_GRTAVFS_FW_SEP_FUSE_e; 669 670#define PP_NUM_RTAVFS_PWL_ZONES 5 671 672 673 674// VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 675// Slope Q1.7, Offset Q1.2 676typedef struct { 677 int8_t Offset; // in Amps 678 uint8_t Padding; 679 uint16_t MaxCurrent; // in Amps 680} SviTelemetryScale_t; 681 682#define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 683 684 685#define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 686#define PP_OD_FEATURE_PPT_BIT 2 687#define PP_OD_FEATURE_FAN_CURVE_BIT 3 688#define PP_OD_FEATURE_GFXCLK_BIT 7 689#define PP_OD_FEATURE_UCLK_BIT 8 690#define PP_OD_FEATURE_ZERO_FAN_BIT 9 691#define PP_OD_FEATURE_TEMPERATURE_BIT 10 692#define PP_OD_FEATURE_COUNT 13 693 694typedef enum { 695 PP_OD_POWER_FEATURE_ALWAYS_ENABLED, 696 PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING, 697 PP_OD_POWER_FEATURE_ALWAYS_DISABLED, 698} PP_OD_POWER_FEATURE_e; 699 700typedef enum { 701 FAN_MODE_AUTO = 0, 702 FAN_MODE_MANUAL_LINEAR, 703} FanMode_e; 704 705typedef struct { 706 uint32_t FeatureCtrlMask; 707 708 //Voltage control 709 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 710 711 uint32_t Reserved; 712 713 //Frequency changes 714 int16_t GfxclkFmin; // MHz 715 int16_t GfxclkFmax; // MHz 716 uint16_t UclkFmin; // MHz 717 uint16_t UclkFmax; // MHz 718 719 //PPT 720 int16_t Ppt; // % 721 int16_t Tdc; 722 723 //Fan control 724 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 725 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 726 uint16_t FanMinimumPwm; 727 uint16_t AcousticTargetRpmThreshold; 728 uint16_t AcousticLimitRpmThreshold; 729 uint16_t FanTargetTemperature; // Degree Celcius 730 uint8_t FanZeroRpmEnable; 731 uint8_t FanZeroRpmStopTemp; 732 uint8_t FanMode; 733 uint8_t MaxOpTemp; 734 uint8_t Padding[4]; 735 736 uint32_t Spare[12]; 737 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 738} OverDriveTable_t; 739 740typedef struct { 741 OverDriveTable_t OverDriveTable; 742 743} OverDriveTableExternal_t; 744 745typedef struct { 746 uint32_t FeatureCtrlMask; 747 748 int16_t VoltageOffsetPerZoneBoundary; 749 uint16_t Reserved1; 750 751 uint16_t Reserved2; 752 753 int16_t GfxclkFmin; // MHz 754 int16_t GfxclkFmax; // MHz 755 uint16_t UclkFmin; // MHz 756 uint16_t UclkFmax; // MHz 757 758 //PPT 759 int16_t Ppt; // % 760 int16_t Tdc; 761 762 uint8_t FanLinearPwmPoints; 763 uint8_t FanLinearTempPoints; 764 uint16_t FanMinimumPwm; 765 uint16_t AcousticTargetRpmThreshold; 766 uint16_t AcousticLimitRpmThreshold; 767 uint16_t FanTargetTemperature; // Degree Celcius 768 uint8_t FanZeroRpmEnable; 769 uint8_t FanZeroRpmStopTemp; 770 uint8_t FanMode; 771 uint8_t MaxOpTemp; 772 uint8_t Padding[4]; 773 774 uint32_t Spare[12]; 775 776} OverDriveLimits_t; 777 778 779typedef enum { 780 BOARD_GPIO_SMUIO_0, 781 BOARD_GPIO_SMUIO_1, 782 BOARD_GPIO_SMUIO_2, 783 BOARD_GPIO_SMUIO_3, 784 BOARD_GPIO_SMUIO_4, 785 BOARD_GPIO_SMUIO_5, 786 BOARD_GPIO_SMUIO_6, 787 BOARD_GPIO_SMUIO_7, 788 BOARD_GPIO_SMUIO_8, 789 BOARD_GPIO_SMUIO_9, 790 BOARD_GPIO_SMUIO_10, 791 BOARD_GPIO_SMUIO_11, 792 BOARD_GPIO_SMUIO_12, 793 BOARD_GPIO_SMUIO_13, 794 BOARD_GPIO_SMUIO_14, 795 BOARD_GPIO_SMUIO_15, 796 BOARD_GPIO_SMUIO_16, 797 BOARD_GPIO_SMUIO_17, 798 BOARD_GPIO_SMUIO_18, 799 BOARD_GPIO_SMUIO_19, 800 BOARD_GPIO_SMUIO_20, 801 BOARD_GPIO_SMUIO_21, 802 BOARD_GPIO_SMUIO_22, 803 BOARD_GPIO_SMUIO_23, 804 BOARD_GPIO_SMUIO_24, 805 BOARD_GPIO_SMUIO_25, 806 BOARD_GPIO_SMUIO_26, 807 BOARD_GPIO_SMUIO_27, 808 BOARD_GPIO_SMUIO_28, 809 BOARD_GPIO_SMUIO_29, 810 BOARD_GPIO_SMUIO_30, 811 BOARD_GPIO_SMUIO_31, 812 MAX_BOARD_GPIO_SMUIO_NUM, 813 BOARD_GPIO_DC_GEN_A, 814 BOARD_GPIO_DC_GEN_B, 815 BOARD_GPIO_DC_GEN_C, 816 BOARD_GPIO_DC_GEN_D, 817 BOARD_GPIO_DC_GEN_E, 818 BOARD_GPIO_DC_GEN_F, 819 BOARD_GPIO_DC_GEN_G, 820 BOARD_GPIO_DC_GENLK_CLK, 821 BOARD_GPIO_DC_GENLK_VSYNC, 822 BOARD_GPIO_DC_SWAPLOCK_A, 823 BOARD_GPIO_DC_SWAPLOCK_B, 824} BOARD_GPIO_TYPE_e; 825 826#define INVALID_BOARD_GPIO 0xFF 827 828 829typedef struct { 830 //PLL 0 831 uint16_t InitGfxclk_bypass; 832 uint16_t InitSocclk; 833 uint16_t InitMp0clk; 834 uint16_t InitMpioclk; 835 uint16_t InitSmnclk; 836 uint16_t InitUcpclk; 837 uint16_t InitCsrclk; 838 //PLL 1 839 840 uint16_t InitDprefclk; 841 uint16_t InitDcfclk; 842 uint16_t InitDtbclk; 843 //PLL 2 844 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 845 uint16_t InitVclk; 846 // PLL 3 847 uint16_t InitUsbdfsclk; 848 uint16_t InitMp1clk; 849 uint16_t InitLclk; 850 uint16_t InitBaco400clk_bypass; 851 uint16_t InitBaco1200clk_bypass; 852 uint16_t InitBaco700clk_bypass; 853 // PLL 4 854 uint16_t InitFclk; 855 // PLL 5 856 uint16_t InitGfxclk_clkb; 857 858 //PLL 6 859 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 860 861 uint8_t Padding[3]; 862 863 uint32_t InitVcoFreqPll0; 864 uint32_t InitVcoFreqPll1; 865 uint32_t InitVcoFreqPll2; 866 uint32_t InitVcoFreqPll3; 867 uint32_t InitVcoFreqPll4; 868 uint32_t InitVcoFreqPll5; 869 uint32_t InitVcoFreqPll6; 870 871 //encoding will change depending on SVI2/SVI3 872 uint16_t InitGfx; // In mV(Q2) , should be 0? 873 uint16_t InitSoc; // In mV(Q2) 874 uint16_t InitU; // In Mv(Q2) not applicable 875 876 uint16_t Padding2; 877 878 uint32_t Spare[8]; 879 880} BootValues_t; 881 882 883typedef struct { 884 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 885 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 886 887 uint16_t Temperature[TEMP_COUNT]; // Celsius 888 889 uint8_t PwmLimitMin; 890 uint8_t PwmLimitMax; 891 uint8_t FanTargetTemperature; 892 uint8_t Spare1[1]; 893 894 uint16_t AcousticTargetRpmThresholdMin; 895 uint16_t AcousticTargetRpmThresholdMax; 896 897 uint16_t AcousticLimitRpmThresholdMin; 898 uint16_t AcousticLimitRpmThresholdMax; 899 900 uint16_t PccLimitMin; 901 uint16_t PccLimitMax; 902 903 uint16_t FanStopTempMin; 904 uint16_t FanStopTempMax; 905 uint16_t FanStartTempMin; 906 uint16_t FanStartTempMax; 907 908 uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; 909 uint32_t Spare[11]; 910 911} MsgLimits_t; 912 913typedef struct { 914 uint16_t BaseClockAc; 915 uint16_t GameClockAc; 916 uint16_t BoostClockAc; 917 uint16_t BaseClockDc; 918 uint16_t GameClockDc; 919 uint16_t BoostClockDc; 920 921 uint32_t Reserved[4]; 922} DriverReportedClocks_t; 923 924typedef struct { 925 uint8_t DcBtcEnabled; 926 uint8_t Padding[3]; 927 928 uint16_t DcTol; // mV Q2 929 uint16_t DcBtcGb; // mV Q2 930 931 uint16_t DcBtcMin; // mV Q2 932 uint16_t DcBtcMax; // mV Q2 933 934 LinearInt_t DcBtcGbScalar; 935 936} AvfsDcBtcParams_t; 937 938typedef struct { 939 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 940 uint16_t VftFMin; // in MHz 941 uint16_t VInversion; // in mV Q2 942 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 943 QuadraticInt_t qAvfsGb; 944 QuadraticInt_t qAvfsGb2; 945} AvfsFuseOverride_t; 946 947typedef struct { 948 // SECTION: Version 949 950 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 951 952 // SECTION: Feature Control 953 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 954 955 // SECTION: Miscellaneous Configuration 956 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 957 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 958 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 959 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 960 961 // SECTION: Infrastructure Limits 962 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 963 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 964 965 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 966 967 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 968 //relative index 0 969 uint8_t EnableLegacyPptLimit; 970 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 971 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 972 973 uint8_t PaddingPpt[1]; 974 975 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 976 977 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 978 979 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 980 981 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 982 983 uint16_t PaddingInfra; 984 985 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 986 uint32_t FitControllerFailureRateLimit; //in IEEE float 987 //Expected GFX Duty Cycle at Vmax. 988 uint32_t FitControllerGfxDutyCycle; // in IEEE float 989 //Expected SOC Duty Cycle at Vmax. 990 uint32_t FitControllerSocDutyCycle; // in IEEE float 991 992 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 993 uint32_t FitControllerSocOffset; //in IEEE float 994 995 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 996 997 // SECTION: Throttler settings 998 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 999 1000 // SECTION: FW DSTATE Settings 1001 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 1002 1003 // SECTION: Voltage Control Parameters 1004 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 1005 1006 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 1007 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 1008 1009 // Voltage Limits 1010 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 1011 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 1012 1013 //Vmin Optimizations 1014 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 1015 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 1016 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 1017 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 1018 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1019 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1020 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1021 uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 1022 uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1023 1024 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1025 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1026 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1027 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1028 //Scalar coefficient of the PSM aging degradation function 1029 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1030 //Exponential coefficient of the PSM aging degradation function 1031 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1032 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1033 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1034 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1035 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1036 1037 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1038 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1039 1040 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1041 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1042 1043 QuadraticInt_t Vmin_droop; 1044 uint32_t SpareVmin[9]; 1045 1046 1047 //SECTION: DPM Configuration 1 1048 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1049 1050 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1051 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1052 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1053 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1054 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1055 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1056 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1057 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1058 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1059 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1060 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1061 1062 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1063 1064 // SECTION: DPM Configuration 2 1065 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1066 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1067 1068 uint8_t GfxclkSpare[2]; 1069 uint16_t GfxclkFreqCap; 1070 1071 //GFX Idle Power Settings 1072 uint16_t GfxclkFgfxoffEntry; // in Mhz 1073 uint16_t GfxclkFgfxoffExitImu; // in Mhz 1074 uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1075 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1076 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1077 uint8_t GfxIdlePadding; 1078 1079 uint8_t SmsRepairWRCKClkDivEn; 1080 uint8_t SmsRepairWRCKClkDivVal; 1081 uint8_t GfxOffEntryEarlyMGCGEn; 1082 uint8_t GfxOffEntryForceCGCGEn; 1083 uint8_t GfxOffEntryForceCGCGDelayEn; 1084 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1085 1086 uint16_t GfxclkFreqGfxUlv; // in MHz 1087 uint8_t GfxIdlePadding2[2]; 1088 uint32_t GfxOffEntryHysteresis; //For RLC to count after it enters CGCG, and before triggers GFXOFF entry 1089 uint32_t GfxoffSpare[15]; 1090 1091 // GFX GPO 1092 uint32_t DfllBtcMasterScalerM; 1093 int32_t DfllBtcMasterScalerB; 1094 uint32_t DfllBtcSlaveScalerM; 1095 int32_t DfllBtcSlaveScalerB; 1096 uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg 1097 uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg 1098 uint32_t GfxGpoSpare[10]; 1099 1100 // GFX DCS 1101 1102 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1103 uint16_t PaddingDcs; 1104 1105 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1106 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1107 1108 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1109 1110 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1111 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1112 1113 1114 uint32_t DcsSpare[14]; 1115 1116 // UCLK section 1117 uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz 1118 1119 // UCLK section 1120 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1121 uint8_t PaddingMem[3]; 1122 1123 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1124 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1125 1126 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1127 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1128 1129 //FCLK Section 1130 1131 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1132 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1133 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1134 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1135 uint16_t PaddingFclk; 1136 1137 // Link DPM Settings 1138 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1139 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1140 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1141 1142 // SECTION: Fan Control 1143 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1144 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1145 1146 uint16_t FanGain[TEMP_COUNT]; 1147 uint16_t FanGainPadding; 1148 1149 uint16_t FanPwmMin; 1150 uint16_t AcousticTargetRpmThreshold; 1151 uint16_t AcousticLimitRpmThreshold; 1152 uint16_t FanMaximumRpm; 1153 uint16_t MGpuAcousticLimitRpmThreshold; 1154 uint16_t FanTargetGfxclk; 1155 uint32_t TempInputSelectMask; 1156 uint8_t FanZeroRpmEnable; 1157 uint8_t FanTachEdgePerRev; 1158 uint16_t FanTargetTemperature[TEMP_COUNT]; 1159 1160 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1161 int16_t FuzzyFan_ErrorSetDelta; 1162 int16_t FuzzyFan_ErrorRateSetDelta; 1163 int16_t FuzzyFan_PwmSetDelta; 1164 uint16_t FuzzyFan_Reserved; 1165 1166 uint16_t FwCtfLimit[TEMP_COUNT]; 1167 1168 uint16_t IntakeTempEnableRPM; 1169 int16_t IntakeTempOffsetTemp; 1170 uint16_t IntakeTempReleaseTemp; 1171 uint16_t IntakeTempHighIntakeAcousticLimit; 1172 uint16_t IntakeTempAcouticLimitReleaseRate; 1173 1174 int16_t FanAbnormalTempLimitOffset; 1175 uint16_t FanStalledTriggerRpm; 1176 uint16_t FanAbnormalTriggerRpmCoeff; 1177 uint16_t FanAbnormalDetectionEnable; 1178 1179 uint8_t FanIntakeSensorSupport; 1180 uint8_t FanIntakePadding[3]; 1181 uint32_t FanSpare[13]; 1182 // SECTION: VDD_GFX AVFS 1183 1184 uint8_t OverrideGfxAvfsFuses; 1185 uint8_t GfxAvfsPadding[3]; 1186 1187 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1188 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1189 1190 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1191 1192 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1193 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1194 1195 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1196 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1197 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1198 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1199 1200 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1201 1202 uint32_t dGbV_dT_vmin; 1203 uint32_t dGbV_dT_vmax; 1204 1205 uint32_t V2F_vmin_range_low; 1206 uint32_t V2F_vmin_range_high; 1207 uint32_t V2F_vmax_range_low; 1208 uint32_t V2F_vmax_range_high; 1209 1210 AvfsDcBtcParams_t DcBtcGfxParams; 1211 1212 uint32_t GfxAvfsSpare[32]; 1213 1214 //SECTION: VDD_SOC AVFS 1215 1216 uint8_t OverrideSocAvfsFuses; 1217 uint8_t MinSocAvfsRevision; 1218 uint8_t SocAvfsPadding[2]; 1219 1220 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1221 1222 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1223 1224 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1225 1226 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1227 1228 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1229 1230 uint32_t SocAvfsSpare[32]; 1231 1232 //SECTION: Boot clock and voltage values 1233 BootValues_t BootValues; 1234 1235 //SECTION: Driver Reported Clocks 1236 DriverReportedClocks_t DriverReportedClocks; 1237 1238 //SECTION: Message Limits 1239 MsgLimits_t MsgLimits; 1240 1241 //SECTION: OverDrive Limits 1242 OverDriveLimits_t OverDriveLimitsMin; 1243 OverDriveLimits_t OverDriveLimitsBasicMax; 1244 OverDriveLimits_t OverDriveLimitsAdvancedMax; 1245 1246 // SECTION: Advanced Options 1247 uint32_t DebugOverrides; 1248 1249 // Section: Total Board Power idle vs active coefficients 1250 uint8_t TotalBoardPowerSupport; 1251 uint8_t TotalBoardPowerPadding[3]; 1252 1253 int16_t TotalIdleBoardPowerM; 1254 int16_t TotalIdleBoardPowerB; 1255 int16_t TotalBoardPowerM; 1256 int16_t TotalBoardPowerB; 1257 1258 QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; 1259 QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; 1260 QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; 1261 1262 // SECTION: Sku Reserved 1263 uint32_t Spare[43]; 1264 1265 // Padding for MMHUB - do not modify this 1266 uint32_t MmHubPadding[8]; 1267 1268} SkuTable_t; 1269 1270typedef struct { 1271 // SECTION: Version 1272 uint32_t Version; //should be unique to each board type 1273 1274 1275 // SECTION: I2C Control 1276 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1277 1278 // SECTION: SVI2 Board Parameters 1279 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1280 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1281 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1282 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1283 1284 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1285 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1286 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1287 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1288 1289 //SECTION SVI3 Board Parameters 1290 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1291 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1292 1293 uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1294 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1295 1296 // SECTION: Voltage Regulator Settings 1297 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1298 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1299 1300 uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1301 1302 // SECTION: GPIO Settings 1303 1304 uint8_t LedOffGpio; 1305 uint8_t FanOffGpio; 1306 uint8_t GfxVrPowerStageOffGpio; 1307 1308 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1309 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1310 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1311 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1312 1313 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1314 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1315 1316 // LED Display Settings 1317 uint8_t LedPin0; // GPIO number for LedPin[0] 1318 uint8_t LedPin1; // GPIO number for LedPin[1] 1319 uint8_t LedPin2; // GPIO number for LedPin[2] 1320 uint8_t LedEnableMask; 1321 1322 uint8_t LedPcie; // GPIO number for PCIE results 1323 uint8_t LedError; // GPIO number for Error Cases 1324 1325 // SECTION: Clock Spread Spectrum 1326 1327 // UCLK Spread Spectrum 1328 uint8_t UclkTrainingModeSpreadPercent; // Q4.4 1329 uint8_t UclkSpreadPadding; 1330 uint16_t UclkSpreadFreq; // kHz 1331 1332 // UCLK Spread Spectrum 1333 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1334 1335 // FCLK Spread Spectrum 1336 uint8_t FclkSpreadPadding; 1337 uint8_t FclkSpreadPercent; // Q4.4 1338 uint16_t FclkSpreadFreq; // kHz 1339 1340 // Section: Memory Config 1341 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1342 uint8_t PaddingMem1[7]; 1343 1344 // SECTION: UMC feature flags 1345 uint8_t HsrEnabled; 1346 uint8_t VddqOffEnabled; 1347 uint8_t PaddingUmcFlags[2]; 1348 1349 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1350 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1351 1352 uint8_t FuseWritePowerMuxPresent; 1353 uint8_t FuseWritePadding[3]; 1354 1355 // SECTION: Board Reserved 1356 uint32_t BoardSpare[63]; 1357 1358 // SECTION: Structure Padding 1359 1360 // Padding for MMHUB - do not modify this 1361 uint32_t MmHubPadding[8]; 1362} BoardTable_t; 1363 1364#pragma pack(push, 1) 1365typedef struct { 1366 SkuTable_t SkuTable; 1367 BoardTable_t BoardTable; 1368} PPTable_t; 1369#pragma pack(pop) 1370 1371typedef struct { 1372 // Time constant parameters for clock averages in ms 1373 uint16_t GfxclkAverageLpfTau; 1374 uint16_t FclkAverageLpfTau; 1375 uint16_t UclkAverageLpfTau; 1376 uint16_t GfxActivityLpfTau; 1377 uint16_t UclkActivityLpfTau; 1378 uint16_t SocketPowerLpfTau; 1379 uint16_t VcnClkAverageLpfTau; 1380 uint16_t VcnUsageAverageLpfTau; 1381} DriverSmuConfig_t; 1382 1383typedef struct { 1384 DriverSmuConfig_t DriverSmuConfig; 1385 1386 uint32_t Spare[8]; 1387 // Padding - ignore 1388 uint32_t MmHubPadding[8]; // SMU internal use 1389} DriverSmuConfigExternal_t; 1390 1391 1392typedef struct { 1393 1394 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1395 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1396 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1397 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1398 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1399 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1400 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1401 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1402 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1403 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1404 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1405 1406 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1407 1408 uint16_t Padding; 1409 1410 uint32_t Spare[32]; 1411 1412 // Padding - ignore 1413 uint32_t MmHubPadding[8]; // SMU internal use 1414 1415} DriverInfoTable_t; 1416 1417typedef struct { 1418 uint32_t CurrClock[PPCLK_COUNT]; 1419 1420 uint16_t AverageGfxclkFrequencyTarget; 1421 uint16_t AverageGfxclkFrequencyPreDs; 1422 uint16_t AverageGfxclkFrequencyPostDs; 1423 uint16_t AverageFclkFrequencyPreDs; 1424 uint16_t AverageFclkFrequencyPostDs; 1425 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1426 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1427 uint16_t AverageVclk0Frequency ; 1428 uint16_t AverageDclk0Frequency ; 1429 uint16_t AverageVclk1Frequency ; 1430 uint16_t AverageDclk1Frequency ; 1431 uint16_t PCIeBusy ; 1432 uint16_t dGPU_W_MAX ; 1433 uint16_t padding ; 1434 1435 uint32_t MetricsCounter ; 1436 1437 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1438 uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1439 1440 uint16_t AverageGfxActivity ; 1441 uint16_t AverageUclkActivity ; 1442 uint16_t Vcn0ActivityPercentage ; 1443 uint16_t Vcn1ActivityPercentage ; 1444 1445 uint32_t EnergyAccumulator; 1446 uint16_t AverageSocketPower; 1447 uint16_t AverageTotalBoardPower; 1448 1449 uint16_t AvgTemperature[TEMP_COUNT]; 1450 uint16_t AvgTemperatureFanIntake; 1451 1452 uint8_t PcieRate ; 1453 uint8_t PcieWidth ; 1454 1455 uint8_t AvgFanPwm; 1456 uint8_t Padding[1]; 1457 uint16_t AvgFanRpm; 1458 1459 1460 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1461 1462 //metrics for D3hot entry/exit and driver ARM msgs 1463 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1464 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1465 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1466 1467 uint16_t ApuSTAPMSmartShiftLimit; 1468 uint16_t ApuSTAPMLimit; 1469 uint16_t AvgApuSocketPower; 1470 1471 uint16_t AverageUclkActivity_MAX; 1472 1473 uint32_t PublicSerialNumberLower; 1474 uint32_t PublicSerialNumberUpper; 1475} SmuMetrics_t; 1476 1477typedef struct { 1478 SmuMetrics_t SmuMetrics; 1479 uint32_t Spare[30]; 1480 1481 // Padding - ignore 1482 uint32_t MmHubPadding[8]; // SMU internal use 1483} SmuMetricsExternal_t; 1484 1485typedef struct { 1486 uint8_t WmSetting; 1487 uint8_t Flags; 1488 uint8_t Padding[2]; 1489 1490} WatermarkRowGeneric_t; 1491 1492#define NUM_WM_RANGES 4 1493 1494typedef enum { 1495 WATERMARKS_CLOCK_RANGE = 0, 1496 WATERMARKS_DUMMY_PSTATE, 1497 WATERMARKS_MALL, 1498 WATERMARKS_COUNT, 1499} WATERMARKS_FLAGS_e; 1500 1501typedef struct { 1502 // Watermarks 1503 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1504} Watermarks_t; 1505 1506typedef struct { 1507 Watermarks_t Watermarks; 1508 uint32_t Spare[16]; 1509 1510 uint32_t MmHubPadding[8]; // SMU internal use 1511} WatermarksExternal_t; 1512 1513typedef struct { 1514 uint16_t avgPsmCount[36]; 1515 uint16_t minPsmCount[36]; 1516 float avgPsmVoltage[36]; 1517 float minPsmVoltage[36]; 1518} AvfsDebugTable_t; 1519 1520typedef struct { 1521 AvfsDebugTable_t AvfsDebugTable; 1522 1523 uint32_t MmHubPadding[8]; // SMU internal use 1524} AvfsDebugTableExternal_t; 1525 1526 1527typedef struct { 1528 uint8_t Gfx_ActiveHystLimit; 1529 uint8_t Gfx_IdleHystLimit; 1530 uint8_t Gfx_FPS; 1531 uint8_t Gfx_MinActiveFreqType; 1532 uint8_t Gfx_BoosterFreqType; 1533 uint8_t PaddingGfx; 1534 uint16_t Gfx_MinActiveFreq; // MHz 1535 uint16_t Gfx_BoosterFreq; // MHz 1536 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1537 uint32_t Gfx_PD_Data_limit_a; // Q16 1538 uint32_t Gfx_PD_Data_limit_b; // Q16 1539 uint32_t Gfx_PD_Data_limit_c; // Q16 1540 uint32_t Gfx_PD_Data_error_coeff; // Q16 1541 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1542 1543 uint8_t Fclk_ActiveHystLimit; 1544 uint8_t Fclk_IdleHystLimit; 1545 uint8_t Fclk_FPS; 1546 uint8_t Fclk_MinActiveFreqType; 1547 uint8_t Fclk_BoosterFreqType; 1548 uint8_t PaddingFclk; 1549 uint16_t Fclk_MinActiveFreq; // MHz 1550 uint16_t Fclk_BoosterFreq; // MHz 1551 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1552 uint32_t Fclk_PD_Data_limit_a; // Q16 1553 uint32_t Fclk_PD_Data_limit_b; // Q16 1554 uint32_t Fclk_PD_Data_limit_c; // Q16 1555 uint32_t Fclk_PD_Data_error_coeff; // Q16 1556 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1557 1558 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1559 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1560 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1561 uint16_t Mem_Fps; 1562 uint8_t padding[2]; 1563 1564} DpmActivityMonitorCoeffInt_t; 1565 1566 1567typedef struct { 1568 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1569 uint32_t MmHubPadding[8]; // SMU internal use 1570} DpmActivityMonitorCoeffIntExternal_t; 1571 1572 1573 1574// Workload bits 1575#define WORKLOAD_PPLIB_DEFAULT_BIT 0 1576#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1577#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1578#define WORKLOAD_PPLIB_VIDEO_BIT 3 1579#define WORKLOAD_PPLIB_VR_BIT 4 1580#define WORKLOAD_PPLIB_COMPUTE_BIT 5 1581#define WORKLOAD_PPLIB_CUSTOM_BIT 6 1582#define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1583#define WORKLOAD_PPLIB_COUNT 8 1584 1585 1586// These defines are used with the following messages: 1587// SMC_MSG_TransferTableDram2Smu 1588// SMC_MSG_TransferTableSmu2Dram 1589 1590// Table transfer status 1591#define TABLE_TRANSFER_OK 0x0 1592#define TABLE_TRANSFER_FAILED 0xFF 1593#define TABLE_TRANSFER_PENDING 0xAB 1594 1595// Table types 1596#define TABLE_PPTABLE 0 1597#define TABLE_COMBO_PPTABLE 1 1598#define TABLE_WATERMARKS 2 1599#define TABLE_AVFS_PSM_DEBUG 3 1600#define TABLE_PMSTATUSLOG 4 1601#define TABLE_SMU_METRICS 5 1602#define TABLE_DRIVER_SMU_CONFIG 6 1603#define TABLE_ACTIVITY_MONITOR_COEFF 7 1604#define TABLE_OVERDRIVE 8 1605#define TABLE_I2C_COMMANDS 9 1606#define TABLE_DRIVER_INFO 10 1607#define TABLE_ECCINFO 11 1608#define TABLE_WIFIBAND 12 1609#define TABLE_COUNT 13 1610 1611//IH Interupt ID 1612#define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1613#define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1614#define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1615#define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1616#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1617#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1618#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1619#define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 1620#define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 1621 1622#endif 1623