Searched refs:MII_BMCR (Results 1 - 25 of 109) sorted by relevance

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/linux-master/drivers/net/ethernet/ibm/emac/
H A Dphy.c60 val = phy_read(phy, MII_BMCR);
63 phy_write(phy, MII_BMCR, val);
68 val = phy_read(phy, MII_BMCR);
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
84 val = gpcs_phy_read(phy, MII_BMCR);
87 gpcs_phy_write(phy, MII_BMCR, val);
92 val = gpcs_phy_read(phy, MII_BMCR);
98 gpcs_phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
120 ctl = phy_read(phy, MII_BMCR);
126 phy_write(phy, MII_BMCR, ct
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/linux-master/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.c53 mdio_set_bit(cphy, MII_BMCR, BMCR_RESET);
56 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
129 (void) simple_mdio_read(phy, MII_BMCR, &ctl);
144 (void) simple_mdio_write(phy, MII_BMCR, ctl);
167 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
170 (void) simple_mdio_write(cphy, MII_BMCR, ctl);
188 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
190 (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART);
196 mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART);
235 mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBAC
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/linux-master/drivers/net/phy/
H A Dste10Xp.c35 value = phy_read(phydev, MII_BMCR);
40 err = phy_write(phydev, MII_BMCR, value);
45 value = phy_read(phydev, MII_BMCR);
H A Det1011c.c49 int ctl = phy_read(phydev, MII_BMCR);
56 phy_write(phydev, MII_BMCR, ctl | BMCR_RESET);
H A Dax88796b.c37 ret = phy_write(phydev, MII_BMCR, 0);
60 * linkmode so use MII_BMCR as default values.
62 val = phy_read(phydev, MII_BMCR);
H A Ddavicom.c123 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
142 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
170 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
H A Dnational.c123 int bmcr = phy_read(phydev, MII_BMCR);
125 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
131 phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
H A Dlxt.c199 control = phy_read(phydev, MII_BMCR);
289 val = phy_read(phydev, MII_BMCR);
292 phy_write(phydev, MII_BMCR, val);
H A Dmicrochip.c360 temp = phy_read(phydev, MII_BMCR);
362 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
364 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
H A Dswphy.c149 case MII_BMCR:
H A Ddp83848.c119 val = phy_read(phydev, MII_BMCR);
H A Dncn26000.c59 return phy_write(phydev, MII_BMCR, NCN26000_BCMR_LINK_CTRL_BIT);
H A Dbroadcom.c155 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
169 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
180 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
500 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
684 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
704 err = phy_read(phydev, MII_BMCR);
845 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
H A Dmotorcomm.c1429 * has MII_BMCR. poll mode combines utp and faber,so need do both.
1445 ret = __phy_modify(phydev, MII_BMCR, mask, set);
1453 ret = __phy_read(phydev, MII_BMCR);
1475 * has MII_BMCR. poll mode combines utp and faber,so need do both.
1735 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
1771 ret = __phy_read(phydev, MII_BMCR);
1782 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
1817 bmcr = __phy_read(phydev, MII_BMCR);
1825 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
1827 __phy_modify(phydev, MII_BMCR, BMCR_PDOW
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/linux-master/drivers/net/
H A Dsungem_phy.c72 val = __sungem_phy_read(phy, phy_id, MII_BMCR);
75 __sungem_phy_write(phy, phy_id, MII_BMCR, val);
80 val = __sungem_phy_read(phy, phy_id, MII_BMCR);
86 __sungem_phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
220 sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
276 sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
295 sungem_phy_write(phy, MII_BMCR, BMCR_RESET);
296 sungem_phy_write(phy, MII_BMCR, 0x1340);
334 ctl = sungem_phy_read(phy, MII_BMCR);
336 sungem_phy_write(phy, MII_BMCR, ct
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H A Dmii.c79 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
165 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
291 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
293 mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr);
300 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
313 mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp);
388 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
390 mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr);
397 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
411 mii->mdio_write(dev, mii->phy_id, MII_BMCR, tm
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/linux-master/drivers/net/dsa/b53/
H A Db53_serdes.c95 reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
98 b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
148 reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
154 b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
/linux-master/drivers/net/ethernet/chelsio/cxgb3/
H A Dvsc8211.c118 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR,
125 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR,
136 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr);
212 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr);
318 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN,
/linux-master/drivers/net/mdio/
H A Dmdio-moxart.c98 data = moxart_mdio_read(bus, i, MII_BMCR);
103 if (moxart_mdio_write(bus, i, MII_BMCR, data) < 0)
/linux-master/drivers/net/dsa/mv88e6xxx/
H A Dpcs-6352.c128 return marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_PDOWN, val);
209 err = __mdiodev_modify_changed(&mpcs->mdio, MII_BMCR, BMCR_ANENABLE,
230 marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_ANRESTART, BMCR_ANRESTART);
246 err = marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_SPEED100 |
/linux-master/drivers/net/phy/qcom/
H A Dqca83xx.c168 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
173 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
211 phy_modify(phydev, MII_BMCR, mask, 0);
/linux-master/drivers/net/ethernet/intel/e1000e/
H A Dphy.c1145 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1150 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1237 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1243 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1315 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1321 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1408 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1414 ret_val = e1e_wphy(hw, MII_BMCR, data);
1458 * @phy_ctrl: pointer to current value of MII_BMCR
1464 * caller must write to the MII_BMCR registe
[all...]
/linux-master/drivers/net/ethernet/sun/
H A Dsunbmac.c501 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
503 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
507 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
515 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
519 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
536 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
590 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
594 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
596 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
600 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
[all...]
H A Dsunhme.c485 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
492 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
499 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
520 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
550 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
614 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
656 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
660 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
666 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
701 happy_meal_tcvr_write(hp, tregs, MII_BMCR, h
[all...]
/linux-master/drivers/net/ethernet/dec/tulip/
H A Dmedia.c271 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
298 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
466 mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
535 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
538 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);

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