1// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
2/*
3 * Northstar Plus switch SerDes/SGMII PHY main logic
4 *
5 * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/delay.h>
11#include <linux/kernel.h>
12#include <linux/phy.h>
13#include <linux/phylink.h>
14#include <net/dsa.h>
15
16#include "b53_priv.h"
17#include "b53_serdes.h"
18#include "b53_regs.h"
19
20static void b53_serdes_write_blk(struct b53_device *dev, u8 offset, u16 block,
21				 u16 value)
22{
23	b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block);
24	b53_write16(dev, B53_SERDES_PAGE, offset, value);
25}
26
27static u16 b53_serdes_read_blk(struct b53_device *dev, u8 offset, u16 block)
28{
29	u16 value;
30
31	b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block);
32	b53_read16(dev, B53_SERDES_PAGE, offset, &value);
33
34	return value;
35}
36
37static void b53_serdes_set_lane(struct b53_device *dev, u8 lane)
38{
39	if (dev->serdes_lane == lane)
40		return;
41
42	WARN_ON(lane > 1);
43
44	b53_serdes_write_blk(dev, B53_SERDES_LANE,
45			     SERDES_XGXSBLK0_BLOCKADDRESS, lane);
46	dev->serdes_lane = lane;
47}
48
49static void b53_serdes_write(struct b53_device *dev, u8 lane,
50			     u8 offset, u16 block, u16 value)
51{
52	b53_serdes_set_lane(dev, lane);
53	b53_serdes_write_blk(dev, offset, block, value);
54}
55
56static u16 b53_serdes_read(struct b53_device *dev, u8 lane,
57			   u8 offset, u16 block)
58{
59	b53_serdes_set_lane(dev, lane);
60	return b53_serdes_read_blk(dev, offset, block);
61}
62
63void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,
64		       const struct phylink_link_state *state)
65{
66	u8 lane = b53_serdes_map_lane(dev, port);
67	u16 reg;
68
69	if (lane == B53_INVALID_LANE)
70		return;
71
72	reg = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),
73			      SERDES_DIGITAL_BLK);
74	if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
75		reg |= FIBER_MODE_1000X;
76	else
77		reg &= ~FIBER_MODE_1000X;
78	b53_serdes_write(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),
79			 SERDES_DIGITAL_BLK, reg);
80}
81EXPORT_SYMBOL(b53_serdes_config);
82
83void b53_serdes_an_restart(struct b53_device *dev, int port)
84{
85	u8 lane = b53_serdes_map_lane(dev, port);
86	u16 reg;
87
88	if (lane == B53_INVALID_LANE)
89		return;
90
91	reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
92			      SERDES_MII_BLK);
93	reg |= BMCR_ANRESTART;
94	b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
95			 SERDES_MII_BLK, reg);
96}
97EXPORT_SYMBOL(b53_serdes_an_restart);
98
99int b53_serdes_link_state(struct b53_device *dev, int port,
100			  struct phylink_link_state *state)
101{
102	u8 lane = b53_serdes_map_lane(dev, port);
103	u16 dig, bmsr;
104
105	if (lane == B53_INVALID_LANE)
106		return 1;
107
108	dig = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_STATUS,
109			      SERDES_DIGITAL_BLK);
110	bmsr = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMSR),
111			       SERDES_MII_BLK);
112
113	switch ((dig >> SPEED_STATUS_SHIFT) & SPEED_STATUS_MASK) {
114	case SPEED_STATUS_10:
115		state->speed = SPEED_10;
116		break;
117	case SPEED_STATUS_100:
118		state->speed = SPEED_100;
119		break;
120	case SPEED_STATUS_1000:
121		state->speed = SPEED_1000;
122		break;
123	default:
124	case SPEED_STATUS_2500:
125		state->speed = SPEED_2500;
126		break;
127	}
128
129	state->duplex = dig & DUPLEX_STATUS ? DUPLEX_FULL : DUPLEX_HALF;
130	state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
131	state->link = !!(dig & LINK_STATUS);
132	if (dig & PAUSE_RESOLUTION_RX_SIDE)
133		state->pause |= MLO_PAUSE_RX;
134	if (dig & PAUSE_RESOLUTION_TX_SIDE)
135		state->pause |= MLO_PAUSE_TX;
136
137	return 0;
138}
139EXPORT_SYMBOL(b53_serdes_link_state);
140
141void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
142			 phy_interface_t interface, bool link_up)
143{
144	u8 lane = b53_serdes_map_lane(dev, port);
145	u16 reg;
146
147	if (lane == B53_INVALID_LANE)
148		return;
149
150	reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
151			      SERDES_MII_BLK);
152	if (link_up)
153		reg &= ~BMCR_PDOWN;
154	else
155		reg |= BMCR_PDOWN;
156	b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
157			 SERDES_MII_BLK, reg);
158}
159EXPORT_SYMBOL(b53_serdes_link_set);
160
161void b53_serdes_phylink_validate(struct b53_device *dev, int port,
162				 unsigned long *supported,
163				 struct phylink_link_state *state)
164{
165	u8 lane = b53_serdes_map_lane(dev, port);
166
167	if (lane == B53_INVALID_LANE)
168		return;
169
170	switch (lane) {
171	case 0:
172		phylink_set(supported, 2500baseX_Full);
173		fallthrough;
174	case 1:
175		phylink_set(supported, 1000baseX_Full);
176		break;
177	default:
178		break;
179	}
180}
181EXPORT_SYMBOL(b53_serdes_phylink_validate);
182
183int b53_serdes_init(struct b53_device *dev, int port)
184{
185	u8 lane = b53_serdes_map_lane(dev, port);
186	u16 id0, msb, lsb;
187
188	if (lane == B53_INVALID_LANE)
189		return -EINVAL;
190
191	id0 = b53_serdes_read(dev, lane, B53_SERDES_ID0, SERDES_ID0);
192	msb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID1),
193			      SERDES_MII_BLK);
194	lsb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID2),
195			      SERDES_MII_BLK);
196	if (id0 == 0 || id0 == 0xffff) {
197		dev_err(dev->dev, "SerDes not initialized, check settings\n");
198		return -ENODEV;
199	}
200
201	dev_info(dev->dev,
202		 "SerDes lane %d, model: %d, rev %c%d (OUI: 0x%08x)\n",
203		 lane, id0 & SERDES_ID0_MODEL_MASK,
204		 (id0 >> SERDES_ID0_REV_LETTER_SHIFT) + 0x41,
205		 (id0 >> SERDES_ID0_REV_NUM_SHIFT) & SERDES_ID0_REV_NUM_MASK,
206		 (u32)msb << 16 | lsb);
207
208	return 0;
209}
210EXPORT_SYMBOL(b53_serdes_init);
211
212MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
213MODULE_DESCRIPTION("B53 Switch SerDes driver");
214MODULE_LICENSE("Dual BSD/GPL");
215