1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Motorcomm 8511/8521/8531/8531S PHY driver. 4 * 5 * Author: Peter Geis <pgwipeout@gmail.com> 6 * Author: Frank <Frank.Sae@motor-comm.com> 7 */ 8 9#include <linux/etherdevice.h> 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/phy.h> 13#include <linux/of.h> 14 15#define PHY_ID_YT8511 0x0000010a 16#define PHY_ID_YT8521 0x0000011a 17#define PHY_ID_YT8531 0x4f51e91b 18#define PHY_ID_YT8531S 0x4f51e91a 19 20/* YT8521/YT8531S Register Overview 21 * UTP Register space | FIBER Register space 22 * ------------------------------------------------------------ 23 * | UTP MII | FIBER MII | 24 * | UTP MMD | | 25 * | UTP Extended | FIBER Extended | 26 * ------------------------------------------------------------ 27 * | Common Extended | 28 * ------------------------------------------------------------ 29 */ 30 31/* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */ 32 33/* Specific Function Control Register */ 34#define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10 35 36/* 2b00 Manual MDI configuration 37 * 2b01 Manual MDIX configuration 38 * 2b10 Reserved 39 * 2b11 Enable automatic crossover for all modes *default* 40 */ 41#define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5)) 42#define YTPHY_SFCR_CROSSOVER_EN BIT(3) 43#define YTPHY_SFCR_SQE_TEST_EN BIT(2) 44#define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1) 45#define YTPHY_SFCR_JABBER_DIS BIT(0) 46 47/* Specific Status Register */ 48#define YTPHY_SPECIFIC_STATUS_REG 0x11 49#define YTPHY_SSR_SPEED_MODE_OFFSET 14 50 51#define YTPHY_SSR_SPEED_MODE_MASK (BIT(15) | BIT(14)) 52#define YTPHY_SSR_SPEED_10M 0x0 53#define YTPHY_SSR_SPEED_100M 0x1 54#define YTPHY_SSR_SPEED_1000M 0x2 55#define YTPHY_SSR_DUPLEX_OFFSET 13 56#define YTPHY_SSR_DUPLEX BIT(13) 57#define YTPHY_SSR_PAGE_RECEIVED BIT(12) 58#define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11) 59#define YTPHY_SSR_LINK BIT(10) 60#define YTPHY_SSR_MDIX_CROSSOVER BIT(6) 61#define YTPHY_SSR_DOWNGRADE BIT(5) 62#define YTPHY_SSR_TRANSMIT_PAUSE BIT(3) 63#define YTPHY_SSR_RECEIVE_PAUSE BIT(2) 64#define YTPHY_SSR_POLARITY BIT(1) 65#define YTPHY_SSR_JABBER BIT(0) 66 67/* Interrupt enable Register */ 68#define YTPHY_INTERRUPT_ENABLE_REG 0x12 69#define YTPHY_IER_WOL BIT(6) 70 71/* Interrupt Status Register */ 72#define YTPHY_INTERRUPT_STATUS_REG 0x13 73#define YTPHY_ISR_AUTONEG_ERR BIT(15) 74#define YTPHY_ISR_SPEED_CHANGED BIT(14) 75#define YTPHY_ISR_DUPLEX_CHANGED BIT(13) 76#define YTPHY_ISR_PAGE_RECEIVED BIT(12) 77#define YTPHY_ISR_LINK_FAILED BIT(11) 78#define YTPHY_ISR_LINK_SUCCESSED BIT(10) 79#define YTPHY_ISR_WOL BIT(6) 80#define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5) 81#define YTPHY_ISR_SERDES_LINK_FAILED BIT(3) 82#define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2) 83#define YTPHY_ISR_POLARITY_CHANGED BIT(1) 84#define YTPHY_ISR_JABBER_HAPPENED BIT(0) 85 86/* Speed Auto Downgrade Control Register */ 87#define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14 88#define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5) 89 90/* If these bits are set to 3, the PHY attempts five times ( 3(set value) + 91 * additional 2) before downgrading, default 0x3 92 */ 93#define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2) 94 95/* Rx Error Counter Register */ 96#define YTPHY_RX_ERROR_COUNTER_REG 0x15 97 98/* Extended Register's Address Offset Register */ 99#define YTPHY_PAGE_SELECT 0x1E 100 101/* Extended Register's Data Register */ 102#define YTPHY_PAGE_DATA 0x1F 103 104/* FIBER Auto-Negotiation link partner ability */ 105#define YTPHY_FLPA_PAUSE (0x3 << 7) 106#define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7) 107 108#define YT8511_PAGE_SELECT 0x1e 109#define YT8511_PAGE 0x1f 110#define YT8511_EXT_CLK_GATE 0x0c 111#define YT8511_EXT_DELAY_DRIVE 0x0d 112#define YT8511_EXT_SLEEP_CTRL 0x27 113 114/* 2b00 25m from pll 115 * 2b01 25m from xtl *default* 116 * 2b10 62.m from pll 117 * 2b11 125m from pll 118 */ 119#define YT8511_CLK_125M (BIT(2) | BIT(1)) 120#define YT8511_PLLON_SLP BIT(14) 121 122/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */ 123#define YT8511_DELAY_RX BIT(0) 124 125/* TX Gig-E Delay is bits 7:4, default 0x5 126 * TX Fast-E Delay is bits 15:12, default 0xf 127 * Delay = 150ps * N - 250ps 128 * On = 2000ps, off = 50ps 129 */ 130#define YT8511_DELAY_GE_TX_EN (0xf << 4) 131#define YT8511_DELAY_GE_TX_DIS (0x2 << 4) 132#define YT8511_DELAY_FE_TX_EN (0xf << 12) 133#define YT8511_DELAY_FE_TX_DIS (0x2 << 12) 134 135/* Extended register is different from MMD Register and MII Register. 136 * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to 137 * operate extended register. 138 * Extended Register start 139 */ 140 141/* Phy gmii clock gating Register */ 142#define YT8521_CLOCK_GATING_REG 0xC 143#define YT8521_CGR_RX_CLK_EN BIT(12) 144 145#define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27 146#define YT8521_ESC1R_SLEEP_SW BIT(15) 147#define YT8521_ESC1R_PLLON_SLP BIT(14) 148 149/* Phy fiber Link timer cfg2 Register */ 150#define YT8521_LINK_TIMER_CFG2_REG 0xA5 151#define YT8521_LTCR_EN_AUTOSEN BIT(15) 152 153/* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers 154 * of yt8521 phy. There is no need to switch reg space when operating these 155 * registers. 156 */ 157 158#define YT8521_REG_SPACE_SELECT_REG 0xA000 159#define YT8521_RSSR_SPACE_MASK BIT(1) 160#define YT8521_RSSR_FIBER_SPACE (0x1 << 1) 161#define YT8521_RSSR_UTP_SPACE (0x0 << 1) 162#define YT8521_RSSR_TO_BE_ARBITRATED (0xFF) 163 164#define YT8521_CHIP_CONFIG_REG 0xA001 165#define YT8521_CCR_SW_RST BIT(15) 166#define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4) 167#define YT8531_LDO_VOL_3V3 0x0 168#define YT8531_LDO_VOL_1V8 0x2 169 170/* 1b0 disable 1.9ns rxc clock delay *default* 171 * 1b1 enable 1.9ns rxc clock delay 172 */ 173#define YT8521_CCR_RXC_DLY_EN BIT(8) 174#define YT8521_CCR_RXC_DLY_1_900_NS 1900 175 176#define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0)) 177#define YT8521_CCR_MODE_UTP_TO_RGMII 0 178#define YT8521_CCR_MODE_FIBER_TO_RGMII 1 179#define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2 180#define YT8521_CCR_MODE_UTP_TO_SGMII 3 181#define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4 182#define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5 183#define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6 184#define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7 185 186/* 3 phy polling modes,poll mode combines utp and fiber mode*/ 187#define YT8521_MODE_FIBER 0x1 188#define YT8521_MODE_UTP 0x2 189#define YT8521_MODE_POLL 0x3 190 191#define YT8521_RGMII_CONFIG1_REG 0xA003 192/* 1b0 use original tx_clk_rgmii *default* 193 * 1b1 use inverted tx_clk_rgmii. 194 */ 195#define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14) 196#define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10) 197#define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) 198#define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) 199#define YT8521_RC1R_RGMII_0_000_NS 0 200#define YT8521_RC1R_RGMII_0_150_NS 1 201#define YT8521_RC1R_RGMII_0_300_NS 2 202#define YT8521_RC1R_RGMII_0_450_NS 3 203#define YT8521_RC1R_RGMII_0_600_NS 4 204#define YT8521_RC1R_RGMII_0_750_NS 5 205#define YT8521_RC1R_RGMII_0_900_NS 6 206#define YT8521_RC1R_RGMII_1_050_NS 7 207#define YT8521_RC1R_RGMII_1_200_NS 8 208#define YT8521_RC1R_RGMII_1_350_NS 9 209#define YT8521_RC1R_RGMII_1_500_NS 10 210#define YT8521_RC1R_RGMII_1_650_NS 11 211#define YT8521_RC1R_RGMII_1_800_NS 12 212#define YT8521_RC1R_RGMII_1_950_NS 13 213#define YT8521_RC1R_RGMII_2_100_NS 14 214#define YT8521_RC1R_RGMII_2_250_NS 15 215 216#define YTPHY_MISC_CONFIG_REG 0xA006 217#define YTPHY_MCR_FIBER_SPEED_MASK BIT(0) 218#define YTPHY_MCR_FIBER_1000BX (0x1 << 0) 219#define YTPHY_MCR_FIBER_100FX (0x0 << 0) 220 221/* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */ 222#define YTPHY_WOL_MACADDR2_REG 0xA007 223#define YTPHY_WOL_MACADDR1_REG 0xA008 224#define YTPHY_WOL_MACADDR0_REG 0xA009 225 226#define YTPHY_WOL_CONFIG_REG 0xA00A 227#define YTPHY_WCR_INTR_SEL BIT(6) 228#define YTPHY_WCR_ENABLE BIT(3) 229 230/* 2b00 84ms 231 * 2b01 168ms *default* 232 * 2b10 336ms 233 * 2b11 672ms 234 */ 235#define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1)) 236#define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1)) 237 238/* 1b0 Interrupt and WOL events is level triggered and active LOW *default* 239 * 1b1 Interrupt and WOL events is pulse triggered and active LOW 240 */ 241#define YTPHY_WCR_TYPE_PULSE BIT(0) 242 243#define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010 244#define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13) 245#define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */ 246#define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */ 247#define YT8531_RGMII_RX_DS_DEFAULT 0x3 248 249#define YTPHY_SYNCE_CFG_REG 0xA012 250#define YT8521_SCR_SYNCE_ENABLE BIT(5) 251/* 1b0 output 25m clock 252 * 1b1 output 125m clock *default* 253 */ 254#define YT8521_SCR_CLK_FRE_SEL_125M BIT(3) 255#define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1) 256#define YT8521_SCR_CLK_SRC_PLL_125M 0 257#define YT8521_SCR_CLK_SRC_UTP_RX 1 258#define YT8521_SCR_CLK_SRC_SDS_RX 2 259#define YT8521_SCR_CLK_SRC_REF_25M 3 260#define YT8531_SCR_SYNCE_ENABLE BIT(6) 261/* 1b0 output 25m clock *default* 262 * 1b1 output 125m clock 263 */ 264#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4) 265#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1) 266#define YT8531_SCR_CLK_SRC_PLL_125M 0 267#define YT8531_SCR_CLK_SRC_UTP_RX 1 268#define YT8531_SCR_CLK_SRC_SDS_RX 2 269#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 270#define YT8531_SCR_CLK_SRC_REF_25M 4 271#define YT8531_SCR_CLK_SRC_SSC_25M 5 272 273/* Extended Register end */ 274 275#define YTPHY_DTS_OUTPUT_CLK_DIS 0 276#define YTPHY_DTS_OUTPUT_CLK_25M 25000000 277#define YTPHY_DTS_OUTPUT_CLK_125M 125000000 278 279struct yt8521_priv { 280 /* combo_advertising is used for case of YT8521 in combo mode, 281 * this means that yt8521 may work in utp or fiber mode which depends 282 * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED). 283 */ 284 __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising); 285 286 /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/ 287 u8 polling_mode; 288 u8 strap_mode; /* 8 working modes */ 289 /* current reg page of yt8521 phy: 290 * YT8521_RSSR_UTP_SPACE 291 * YT8521_RSSR_FIBER_SPACE 292 * YT8521_RSSR_TO_BE_ARBITRATED 293 */ 294 u8 reg_page; 295}; 296 297/** 298 * ytphy_read_ext() - read a PHY's extended register 299 * @phydev: a pointer to a &struct phy_device 300 * @regnum: register number to read 301 * 302 * NOTE:The caller must have taken the MDIO bus lock. 303 * 304 * returns the value of regnum reg or negative error code 305 */ 306static int ytphy_read_ext(struct phy_device *phydev, u16 regnum) 307{ 308 int ret; 309 310 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 311 if (ret < 0) 312 return ret; 313 314 return __phy_read(phydev, YTPHY_PAGE_DATA); 315} 316 317/** 318 * ytphy_read_ext_with_lock() - read a PHY's extended register 319 * @phydev: a pointer to a &struct phy_device 320 * @regnum: register number to read 321 * 322 * returns the value of regnum reg or negative error code 323 */ 324static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum) 325{ 326 int ret; 327 328 phy_lock_mdio_bus(phydev); 329 ret = ytphy_read_ext(phydev, regnum); 330 phy_unlock_mdio_bus(phydev); 331 332 return ret; 333} 334 335/** 336 * ytphy_write_ext() - write a PHY's extended register 337 * @phydev: a pointer to a &struct phy_device 338 * @regnum: register number to write 339 * @val: value to write to @regnum 340 * 341 * NOTE:The caller must have taken the MDIO bus lock. 342 * 343 * returns 0 or negative error code 344 */ 345static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val) 346{ 347 int ret; 348 349 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 350 if (ret < 0) 351 return ret; 352 353 return __phy_write(phydev, YTPHY_PAGE_DATA, val); 354} 355 356/** 357 * ytphy_write_ext_with_lock() - write a PHY's extended register 358 * @phydev: a pointer to a &struct phy_device 359 * @regnum: register number to write 360 * @val: value to write to @regnum 361 * 362 * returns 0 or negative error code 363 */ 364static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum, 365 u16 val) 366{ 367 int ret; 368 369 phy_lock_mdio_bus(phydev); 370 ret = ytphy_write_ext(phydev, regnum, val); 371 phy_unlock_mdio_bus(phydev); 372 373 return ret; 374} 375 376/** 377 * ytphy_modify_ext() - bits modify a PHY's extended register 378 * @phydev: a pointer to a &struct phy_device 379 * @regnum: register number to write 380 * @mask: bit mask of bits to clear 381 * @set: bit mask of bits to set 382 * 383 * NOTE: Convenience function which allows a PHY's extended register to be 384 * modified as new register value = (old register value & ~mask) | set. 385 * The caller must have taken the MDIO bus lock. 386 * 387 * returns 0 or negative error code 388 */ 389static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask, 390 u16 set) 391{ 392 int ret; 393 394 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 395 if (ret < 0) 396 return ret; 397 398 return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set); 399} 400 401/** 402 * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register 403 * @phydev: a pointer to a &struct phy_device 404 * @regnum: register number to write 405 * @mask: bit mask of bits to clear 406 * @set: bit mask of bits to set 407 * 408 * NOTE: Convenience function which allows a PHY's extended register to be 409 * modified as new register value = (old register value & ~mask) | set. 410 * 411 * returns 0 or negative error code 412 */ 413static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum, 414 u16 mask, u16 set) 415{ 416 int ret; 417 418 phy_lock_mdio_bus(phydev); 419 ret = ytphy_modify_ext(phydev, regnum, mask, set); 420 phy_unlock_mdio_bus(phydev); 421 422 return ret; 423} 424 425/** 426 * ytphy_get_wol() - report whether wake-on-lan is enabled 427 * @phydev: a pointer to a &struct phy_device 428 * @wol: a pointer to a &struct ethtool_wolinfo 429 * 430 * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg. 431 */ 432static void ytphy_get_wol(struct phy_device *phydev, 433 struct ethtool_wolinfo *wol) 434{ 435 int wol_config; 436 437 wol->supported = WAKE_MAGIC; 438 wol->wolopts = 0; 439 440 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 441 if (wol_config < 0) 442 return; 443 444 if (wol_config & YTPHY_WCR_ENABLE) 445 wol->wolopts |= WAKE_MAGIC; 446} 447 448/** 449 * ytphy_set_wol() - turn wake-on-lan on or off 450 * @phydev: a pointer to a &struct phy_device 451 * @wol: a pointer to a &struct ethtool_wolinfo 452 * 453 * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG 454 * and YTPHY_WOL_MACADDR0_REG are common ext reg. The 455 * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register. 456 * 457 * returns 0 or negative errno code 458 */ 459static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 460{ 461 struct net_device *p_attached_dev; 462 const u16 mac_addr_reg[] = { 463 YTPHY_WOL_MACADDR2_REG, 464 YTPHY_WOL_MACADDR1_REG, 465 YTPHY_WOL_MACADDR0_REG, 466 }; 467 const u8 *mac_addr; 468 int old_page; 469 int ret = 0; 470 u16 mask; 471 u16 val; 472 u8 i; 473 474 if (wol->wolopts & WAKE_MAGIC) { 475 p_attached_dev = phydev->attached_dev; 476 if (!p_attached_dev) 477 return -ENODEV; 478 479 mac_addr = (const u8 *)p_attached_dev->dev_addr; 480 if (!is_valid_ether_addr(mac_addr)) 481 return -EINVAL; 482 483 /* lock mdio bus then switch to utp reg space */ 484 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 485 if (old_page < 0) 486 goto err_restore_page; 487 488 /* Store the device address for the magic packet */ 489 for (i = 0; i < 3; i++) { 490 ret = ytphy_write_ext(phydev, mac_addr_reg[i], 491 ((mac_addr[i * 2] << 8)) | 492 (mac_addr[i * 2 + 1])); 493 if (ret < 0) 494 goto err_restore_page; 495 } 496 497 /* Enable WOL feature */ 498 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; 499 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 500 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; 501 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val); 502 if (ret < 0) 503 goto err_restore_page; 504 505 /* Enable WOL interrupt */ 506 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, 507 YTPHY_IER_WOL); 508 if (ret < 0) 509 goto err_restore_page; 510 511 } else { 512 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 513 if (old_page < 0) 514 goto err_restore_page; 515 516 /* Disable WOL feature */ 517 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 518 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0); 519 520 /* Disable WOL interrupt */ 521 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 522 YTPHY_IER_WOL, 0); 523 if (ret < 0) 524 goto err_restore_page; 525 } 526 527err_restore_page: 528 return phy_restore_page(phydev, old_page, ret); 529} 530 531static int yt8531_set_wol(struct phy_device *phydev, 532 struct ethtool_wolinfo *wol) 533{ 534 const u16 mac_addr_reg[] = { 535 YTPHY_WOL_MACADDR2_REG, 536 YTPHY_WOL_MACADDR1_REG, 537 YTPHY_WOL_MACADDR0_REG, 538 }; 539 const u8 *mac_addr; 540 u16 mask, val; 541 int ret; 542 u8 i; 543 544 if (wol->wolopts & WAKE_MAGIC) { 545 mac_addr = phydev->attached_dev->dev_addr; 546 547 /* Store the device address for the magic packet */ 548 for (i = 0; i < 3; i++) { 549 ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i], 550 ((mac_addr[i * 2] << 8)) | 551 (mac_addr[i * 2 + 1])); 552 if (ret < 0) 553 return ret; 554 } 555 556 /* Enable WOL feature */ 557 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; 558 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 559 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; 560 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, 561 mask, val); 562 if (ret < 0) 563 return ret; 564 565 /* Enable WOL interrupt */ 566 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, 567 YTPHY_IER_WOL); 568 if (ret < 0) 569 return ret; 570 } else { 571 /* Disable WOL feature */ 572 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 573 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, 574 mask, 0); 575 576 /* Disable WOL interrupt */ 577 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 578 YTPHY_IER_WOL, 0); 579 if (ret < 0) 580 return ret; 581 } 582 583 return 0; 584} 585 586static int yt8511_read_page(struct phy_device *phydev) 587{ 588 return __phy_read(phydev, YT8511_PAGE_SELECT); 589}; 590 591static int yt8511_write_page(struct phy_device *phydev, int page) 592{ 593 return __phy_write(phydev, YT8511_PAGE_SELECT, page); 594}; 595 596static int yt8511_config_init(struct phy_device *phydev) 597{ 598 int oldpage, ret = 0; 599 unsigned int ge, fe; 600 601 oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE); 602 if (oldpage < 0) 603 goto err_restore_page; 604 605 /* set rgmii delay mode */ 606 switch (phydev->interface) { 607 case PHY_INTERFACE_MODE_RGMII: 608 ge = YT8511_DELAY_GE_TX_DIS; 609 fe = YT8511_DELAY_FE_TX_DIS; 610 break; 611 case PHY_INTERFACE_MODE_RGMII_RXID: 612 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS; 613 fe = YT8511_DELAY_FE_TX_DIS; 614 break; 615 case PHY_INTERFACE_MODE_RGMII_TXID: 616 ge = YT8511_DELAY_GE_TX_EN; 617 fe = YT8511_DELAY_FE_TX_EN; 618 break; 619 case PHY_INTERFACE_MODE_RGMII_ID: 620 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN; 621 fe = YT8511_DELAY_FE_TX_EN; 622 break; 623 default: /* do not support other modes */ 624 ret = -EOPNOTSUPP; 625 goto err_restore_page; 626 } 627 628 ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge); 629 if (ret < 0) 630 goto err_restore_page; 631 632 /* set clock mode to 125mhz */ 633 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M); 634 if (ret < 0) 635 goto err_restore_page; 636 637 /* fast ethernet delay is in a separate page */ 638 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE); 639 if (ret < 0) 640 goto err_restore_page; 641 642 ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe); 643 if (ret < 0) 644 goto err_restore_page; 645 646 /* leave pll enabled in sleep */ 647 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL); 648 if (ret < 0) 649 goto err_restore_page; 650 651 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP); 652 if (ret < 0) 653 goto err_restore_page; 654 655err_restore_page: 656 return phy_restore_page(phydev, oldpage, ret); 657} 658 659/** 660 * yt8521_read_page() - read reg page 661 * @phydev: a pointer to a &struct phy_device 662 * 663 * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/ 664 * YT8521_RSSR_UTP_SPACE) or negative errno code 665 */ 666static int yt8521_read_page(struct phy_device *phydev) 667{ 668 int old_page; 669 670 old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG); 671 if (old_page < 0) 672 return old_page; 673 674 if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 675 return YT8521_RSSR_FIBER_SPACE; 676 677 return YT8521_RSSR_UTP_SPACE; 678}; 679 680/** 681 * yt8521_write_page() - write reg page 682 * @phydev: a pointer to a &struct phy_device 683 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write. 684 * 685 * returns 0 or negative errno code 686 */ 687static int yt8521_write_page(struct phy_device *phydev, int page) 688{ 689 int mask = YT8521_RSSR_SPACE_MASK; 690 int set; 691 692 if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 693 set = YT8521_RSSR_FIBER_SPACE; 694 else 695 set = YT8521_RSSR_UTP_SPACE; 696 697 return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set); 698}; 699 700/** 701 * struct ytphy_cfg_reg_map - map a config value to a register value 702 * @cfg: value in device configuration 703 * @reg: value in the register 704 */ 705struct ytphy_cfg_reg_map { 706 u32 cfg; 707 u32 reg; 708}; 709 710static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = { 711 /* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */ 712 { 0, YT8521_RC1R_RGMII_0_000_NS }, 713 { 150, YT8521_RC1R_RGMII_0_150_NS }, 714 { 300, YT8521_RC1R_RGMII_0_300_NS }, 715 { 450, YT8521_RC1R_RGMII_0_450_NS }, 716 { 600, YT8521_RC1R_RGMII_0_600_NS }, 717 { 750, YT8521_RC1R_RGMII_0_750_NS }, 718 { 900, YT8521_RC1R_RGMII_0_900_NS }, 719 { 1050, YT8521_RC1R_RGMII_1_050_NS }, 720 { 1200, YT8521_RC1R_RGMII_1_200_NS }, 721 { 1350, YT8521_RC1R_RGMII_1_350_NS }, 722 { 1500, YT8521_RC1R_RGMII_1_500_NS }, 723 { 1650, YT8521_RC1R_RGMII_1_650_NS }, 724 { 1800, YT8521_RC1R_RGMII_1_800_NS }, 725 { 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */ 726 { 2100, YT8521_RC1R_RGMII_2_100_NS }, 727 { 2250, YT8521_RC1R_RGMII_2_250_NS }, 728 729 /* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */ 730 { 0 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_000_NS }, 731 { 150 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_150_NS }, 732 { 300 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_300_NS }, 733 { 450 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_450_NS }, 734 { 600 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_600_NS }, 735 { 750 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_750_NS }, 736 { 900 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_900_NS }, 737 { 1050 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_050_NS }, 738 { 1200 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_200_NS }, 739 { 1350 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_350_NS }, 740 { 1500 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_500_NS }, 741 { 1650 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_650_NS }, 742 { 1800 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_800_NS }, 743 { 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS }, 744 { 2100 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_100_NS }, 745 { 2250 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_250_NS } 746}; 747 748static u32 ytphy_get_delay_reg_value(struct phy_device *phydev, 749 const char *prop_name, 750 const struct ytphy_cfg_reg_map *tbl, 751 int tb_size, 752 u16 *rxc_dly_en, 753 u32 dflt) 754{ 755 struct device_node *node = phydev->mdio.dev.of_node; 756 int tb_size_half = tb_size / 2; 757 u32 val; 758 int i; 759 760 if (of_property_read_u32(node, prop_name, &val)) 761 goto err_dts_val; 762 763 /* when rxc_dly_en is NULL, it is get the delay for tx, only half of 764 * tb_size is valid. 765 */ 766 if (!rxc_dly_en) 767 tb_size = tb_size_half; 768 769 for (i = 0; i < tb_size; i++) { 770 if (tbl[i].cfg == val) { 771 if (rxc_dly_en && i < tb_size_half) 772 *rxc_dly_en = 0; 773 return tbl[i].reg; 774 } 775 } 776 777 phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n", 778 val, prop_name, dflt); 779 780err_dts_val: 781 /* when rxc_dly_en is not NULL, it is get the delay for rx. 782 * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps, 783 * so YT8521_CCR_RXC_DLY_EN should not be set. 784 */ 785 if (rxc_dly_en) 786 *rxc_dly_en = 0; 787 788 return dflt; 789} 790 791static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) 792{ 793 int tb_size = ARRAY_SIZE(ytphy_rgmii_delays); 794 u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN; 795 u32 rx_reg, tx_reg; 796 u16 mask, val = 0; 797 int ret; 798 799 rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps", 800 ytphy_rgmii_delays, tb_size, 801 &rxc_dly_en, 802 YT8521_RC1R_RGMII_1_950_NS); 803 tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps", 804 ytphy_rgmii_delays, tb_size, NULL, 805 YT8521_RC1R_RGMII_1_950_NS); 806 807 switch (phydev->interface) { 808 case PHY_INTERFACE_MODE_RGMII: 809 rxc_dly_en = 0; 810 break; 811 case PHY_INTERFACE_MODE_RGMII_RXID: 812 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg); 813 break; 814 case PHY_INTERFACE_MODE_RGMII_TXID: 815 rxc_dly_en = 0; 816 val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); 817 break; 818 case PHY_INTERFACE_MODE_RGMII_ID: 819 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | 820 FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); 821 break; 822 default: /* do not support other modes */ 823 return -EOPNOTSUPP; 824 } 825 826 ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 827 YT8521_CCR_RXC_DLY_EN, rxc_dly_en); 828 if (ret < 0) 829 return ret; 830 831 /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */ 832 mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK; 833 return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); 834} 835 836static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev) 837{ 838 int ret; 839 840 phy_lock_mdio_bus(phydev); 841 ret = ytphy_rgmii_clk_delay_config(phydev); 842 phy_unlock_mdio_bus(phydev); 843 844 return ret; 845} 846 847/** 848 * struct ytphy_ldo_vol_map - map a current value to a register value 849 * @vol: ldo voltage 850 * @ds: value in the register 851 * @cur: value in device configuration 852 */ 853struct ytphy_ldo_vol_map { 854 u32 vol; 855 u32 ds; 856 u32 cur; 857}; 858 859static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = { 860 {.vol = YT8531_LDO_VOL_1V8, .ds = 0, .cur = 1200}, 861 {.vol = YT8531_LDO_VOL_1V8, .ds = 1, .cur = 2100}, 862 {.vol = YT8531_LDO_VOL_1V8, .ds = 2, .cur = 2700}, 863 {.vol = YT8531_LDO_VOL_1V8, .ds = 3, .cur = 2910}, 864 {.vol = YT8531_LDO_VOL_1V8, .ds = 4, .cur = 3110}, 865 {.vol = YT8531_LDO_VOL_1V8, .ds = 5, .cur = 3600}, 866 {.vol = YT8531_LDO_VOL_1V8, .ds = 6, .cur = 3970}, 867 {.vol = YT8531_LDO_VOL_1V8, .ds = 7, .cur = 4350}, 868 {.vol = YT8531_LDO_VOL_3V3, .ds = 0, .cur = 3070}, 869 {.vol = YT8531_LDO_VOL_3V3, .ds = 1, .cur = 4080}, 870 {.vol = YT8531_LDO_VOL_3V3, .ds = 2, .cur = 4370}, 871 {.vol = YT8531_LDO_VOL_3V3, .ds = 3, .cur = 4680}, 872 {.vol = YT8531_LDO_VOL_3V3, .ds = 4, .cur = 5020}, 873 {.vol = YT8531_LDO_VOL_3V3, .ds = 5, .cur = 5450}, 874 {.vol = YT8531_LDO_VOL_3V3, .ds = 6, .cur = 5740}, 875 {.vol = YT8531_LDO_VOL_3V3, .ds = 7, .cur = 6140}, 876}; 877 878static u32 yt8531_get_ldo_vol(struct phy_device *phydev) 879{ 880 u32 val; 881 882 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 883 val = FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val); 884 885 return val <= YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8; 886} 887 888static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur) 889{ 890 u32 vol; 891 int i; 892 893 vol = yt8531_get_ldo_vol(phydev); 894 for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) { 895 if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur) 896 return yt8531_ldo_vol[i].ds; 897 } 898 899 return -EINVAL; 900} 901 902static int yt8531_set_ds(struct phy_device *phydev) 903{ 904 struct device_node *node = phydev->mdio.dev.of_node; 905 u32 ds_field_low, ds_field_hi, val; 906 int ret, ds; 907 908 /* set rgmii rx clk driver strength */ 909 if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) { 910 ds = yt8531_get_ds_map(phydev, val); 911 if (ds < 0) 912 return dev_err_probe(&phydev->mdio.dev, ds, 913 "No matching current value was found.\n"); 914 } else { 915 ds = YT8531_RGMII_RX_DS_DEFAULT; 916 } 917 918 ret = ytphy_modify_ext_with_lock(phydev, 919 YTPHY_PAD_DRIVE_STRENGTH_REG, 920 YT8531_RGMII_RXC_DS_MASK, 921 FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds)); 922 if (ret < 0) 923 return ret; 924 925 /* set rgmii rx data driver strength */ 926 if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) { 927 ds = yt8531_get_ds_map(phydev, val); 928 if (ds < 0) 929 return dev_err_probe(&phydev->mdio.dev, ds, 930 "No matching current value was found.\n"); 931 } else { 932 ds = YT8531_RGMII_RX_DS_DEFAULT; 933 } 934 935 ds_field_hi = FIELD_GET(BIT(2), ds); 936 ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi); 937 938 ds_field_low = FIELD_GET(GENMASK(1, 0), ds); 939 ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low); 940 941 ret = ytphy_modify_ext_with_lock(phydev, 942 YTPHY_PAD_DRIVE_STRENGTH_REG, 943 YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK, 944 ds_field_low | ds_field_hi); 945 if (ret < 0) 946 return ret; 947 948 return 0; 949} 950 951/** 952 * yt8521_probe() - read chip config then set suitable polling_mode 953 * @phydev: a pointer to a &struct phy_device 954 * 955 * returns 0 or negative errno code 956 */ 957static int yt8521_probe(struct phy_device *phydev) 958{ 959 struct device_node *node = phydev->mdio.dev.of_node; 960 struct device *dev = &phydev->mdio.dev; 961 struct yt8521_priv *priv; 962 int chip_config; 963 u16 mask, val; 964 u32 freq; 965 int ret; 966 967 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 968 if (!priv) 969 return -ENOMEM; 970 971 phydev->priv = priv; 972 973 chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 974 if (chip_config < 0) 975 return chip_config; 976 977 priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK; 978 switch (priv->strap_mode) { 979 case YT8521_CCR_MODE_FIBER_TO_RGMII: 980 case YT8521_CCR_MODE_SGPHY_TO_RGMAC: 981 case YT8521_CCR_MODE_SGMAC_TO_RGPHY: 982 priv->polling_mode = YT8521_MODE_FIBER; 983 priv->reg_page = YT8521_RSSR_FIBER_SPACE; 984 phydev->port = PORT_FIBRE; 985 break; 986 case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII: 987 case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO: 988 case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE: 989 priv->polling_mode = YT8521_MODE_POLL; 990 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 991 phydev->port = PORT_NONE; 992 break; 993 case YT8521_CCR_MODE_UTP_TO_SGMII: 994 case YT8521_CCR_MODE_UTP_TO_RGMII: 995 priv->polling_mode = YT8521_MODE_UTP; 996 priv->reg_page = YT8521_RSSR_UTP_SPACE; 997 phydev->port = PORT_TP; 998 break; 999 } 1000 /* set default reg space */ 1001 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1002 ret = ytphy_write_ext_with_lock(phydev, 1003 YT8521_REG_SPACE_SELECT_REG, 1004 priv->reg_page); 1005 if (ret < 0) 1006 return ret; 1007 } 1008 1009 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) 1010 freq = YTPHY_DTS_OUTPUT_CLK_DIS; 1011 1012 if (phydev->drv->phy_id == PHY_ID_YT8521) { 1013 switch (freq) { 1014 case YTPHY_DTS_OUTPUT_CLK_DIS: 1015 mask = YT8521_SCR_SYNCE_ENABLE; 1016 val = 0; 1017 break; 1018 case YTPHY_DTS_OUTPUT_CLK_25M: 1019 mask = YT8521_SCR_SYNCE_ENABLE | 1020 YT8521_SCR_CLK_SRC_MASK | 1021 YT8521_SCR_CLK_FRE_SEL_125M; 1022 val = YT8521_SCR_SYNCE_ENABLE | 1023 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, 1024 YT8521_SCR_CLK_SRC_REF_25M); 1025 break; 1026 case YTPHY_DTS_OUTPUT_CLK_125M: 1027 mask = YT8521_SCR_SYNCE_ENABLE | 1028 YT8521_SCR_CLK_SRC_MASK | 1029 YT8521_SCR_CLK_FRE_SEL_125M; 1030 val = YT8521_SCR_SYNCE_ENABLE | 1031 YT8521_SCR_CLK_FRE_SEL_125M | 1032 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, 1033 YT8521_SCR_CLK_SRC_PLL_125M); 1034 break; 1035 default: 1036 phydev_warn(phydev, "Freq err:%u\n", freq); 1037 return -EINVAL; 1038 } 1039 } else if (phydev->drv->phy_id == PHY_ID_YT8531S) { 1040 switch (freq) { 1041 case YTPHY_DTS_OUTPUT_CLK_DIS: 1042 mask = YT8531_SCR_SYNCE_ENABLE; 1043 val = 0; 1044 break; 1045 case YTPHY_DTS_OUTPUT_CLK_25M: 1046 mask = YT8531_SCR_SYNCE_ENABLE | 1047 YT8531_SCR_CLK_SRC_MASK | 1048 YT8531_SCR_CLK_FRE_SEL_125M; 1049 val = YT8531_SCR_SYNCE_ENABLE | 1050 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1051 YT8531_SCR_CLK_SRC_REF_25M); 1052 break; 1053 case YTPHY_DTS_OUTPUT_CLK_125M: 1054 mask = YT8531_SCR_SYNCE_ENABLE | 1055 YT8531_SCR_CLK_SRC_MASK | 1056 YT8531_SCR_CLK_FRE_SEL_125M; 1057 val = YT8531_SCR_SYNCE_ENABLE | 1058 YT8531_SCR_CLK_FRE_SEL_125M | 1059 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1060 YT8531_SCR_CLK_SRC_PLL_125M); 1061 break; 1062 default: 1063 phydev_warn(phydev, "Freq err:%u\n", freq); 1064 return -EINVAL; 1065 } 1066 } else { 1067 phydev_warn(phydev, "PHY id err\n"); 1068 return -EINVAL; 1069 } 1070 1071 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, 1072 val); 1073} 1074 1075static int yt8531_probe(struct phy_device *phydev) 1076{ 1077 struct device_node *node = phydev->mdio.dev.of_node; 1078 u16 mask, val; 1079 u32 freq; 1080 1081 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) 1082 freq = YTPHY_DTS_OUTPUT_CLK_DIS; 1083 1084 switch (freq) { 1085 case YTPHY_DTS_OUTPUT_CLK_DIS: 1086 mask = YT8531_SCR_SYNCE_ENABLE; 1087 val = 0; 1088 break; 1089 case YTPHY_DTS_OUTPUT_CLK_25M: 1090 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | 1091 YT8531_SCR_CLK_FRE_SEL_125M; 1092 val = YT8531_SCR_SYNCE_ENABLE | 1093 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1094 YT8531_SCR_CLK_SRC_REF_25M); 1095 break; 1096 case YTPHY_DTS_OUTPUT_CLK_125M: 1097 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | 1098 YT8531_SCR_CLK_FRE_SEL_125M; 1099 val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | 1100 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1101 YT8531_SCR_CLK_SRC_PLL_125M); 1102 break; 1103 default: 1104 phydev_warn(phydev, "Freq err:%u\n", freq); 1105 return -EINVAL; 1106 } 1107 1108 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, 1109 val); 1110} 1111 1112/** 1113 * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp 1114 * @phydev: a pointer to a &struct phy_device 1115 * 1116 * NOTE:The caller must have taken the MDIO bus lock. 1117 * 1118 * returns 0 or negative errno code 1119 */ 1120static int ytphy_utp_read_lpa(struct phy_device *phydev) 1121{ 1122 int lpa, lpagb; 1123 1124 if (phydev->autoneg == AUTONEG_ENABLE) { 1125 if (!phydev->autoneg_complete) { 1126 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 1127 0); 1128 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1129 return 0; 1130 } 1131 1132 if (phydev->is_gigabit_capable) { 1133 lpagb = __phy_read(phydev, MII_STAT1000); 1134 if (lpagb < 0) 1135 return lpagb; 1136 1137 if (lpagb & LPA_1000MSFAIL) { 1138 int adv = __phy_read(phydev, MII_CTRL1000); 1139 1140 if (adv < 0) 1141 return adv; 1142 1143 if (adv & CTL1000_ENABLE_MASTER) 1144 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); 1145 else 1146 phydev_err(phydev, "Master/Slave resolution failed\n"); 1147 return -ENOLINK; 1148 } 1149 1150 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 1151 lpagb); 1152 } 1153 1154 lpa = __phy_read(phydev, MII_LPA); 1155 if (lpa < 0) 1156 return lpa; 1157 1158 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa); 1159 } else { 1160 linkmode_zero(phydev->lp_advertising); 1161 } 1162 1163 return 0; 1164} 1165 1166/** 1167 * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber 1168 * mode, adjust speed and duplex. 1169 * @phydev: a pointer to a &struct phy_device 1170 * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG 1171 * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode) 1172 * 1173 * NOTE:The caller must have taken the MDIO bus lock. 1174 * 1175 * returns 0 1176 */ 1177static int yt8521_adjust_status(struct phy_device *phydev, int status, 1178 bool is_utp) 1179{ 1180 int speed_mode, duplex; 1181 int speed; 1182 int err; 1183 int lpa; 1184 1185 if (is_utp) 1186 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET; 1187 else 1188 duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */ 1189 1190 speed_mode = (status & YTPHY_SSR_SPEED_MODE_MASK) >> 1191 YTPHY_SSR_SPEED_MODE_OFFSET; 1192 1193 switch (speed_mode) { 1194 case YTPHY_SSR_SPEED_10M: 1195 if (is_utp) 1196 speed = SPEED_10; 1197 else 1198 /* for fiber, it will never run here, default to 1199 * SPEED_UNKNOWN 1200 */ 1201 speed = SPEED_UNKNOWN; 1202 break; 1203 case YTPHY_SSR_SPEED_100M: 1204 speed = SPEED_100; 1205 break; 1206 case YTPHY_SSR_SPEED_1000M: 1207 speed = SPEED_1000; 1208 break; 1209 default: 1210 speed = SPEED_UNKNOWN; 1211 break; 1212 } 1213 1214 phydev->speed = speed; 1215 phydev->duplex = duplex; 1216 1217 if (is_utp) { 1218 err = ytphy_utp_read_lpa(phydev); 1219 if (err < 0) 1220 return err; 1221 1222 phy_resolve_aneg_pause(phydev); 1223 } else { 1224 lpa = __phy_read(phydev, MII_LPA); 1225 if (lpa < 0) 1226 return lpa; 1227 1228 /* only support 1000baseX Full */ 1229 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1230 phydev->lp_advertising, lpa & LPA_1000XFULL); 1231 1232 if (!(lpa & YTPHY_FLPA_PAUSE)) { 1233 phydev->pause = 0; 1234 phydev->asym_pause = 0; 1235 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) { 1236 phydev->pause = 1; 1237 phydev->asym_pause = 1; 1238 } else { 1239 phydev->pause = 1; 1240 phydev->asym_pause = 0; 1241 } 1242 } 1243 1244 return 0; 1245} 1246 1247/** 1248 * yt8521_read_status_paged() - determines the speed and duplex of one page 1249 * @phydev: a pointer to a &struct phy_device 1250 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 1251 * operate. 1252 * 1253 * returns 1 (utp or fiber link),0 (no link) or negative errno code 1254 */ 1255static int yt8521_read_status_paged(struct phy_device *phydev, int page) 1256{ 1257 int fiber_latch_val; 1258 int fiber_curr_val; 1259 int old_page; 1260 int ret = 0; 1261 int status; 1262 int link; 1263 1264 linkmode_zero(phydev->lp_advertising); 1265 phydev->duplex = DUPLEX_UNKNOWN; 1266 phydev->speed = SPEED_UNKNOWN; 1267 phydev->asym_pause = 0; 1268 phydev->pause = 0; 1269 1270 /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber 1271 * respectively. but for utp/fiber combo mode, reg space should be 1272 * arbitrated based on media priority. by default, utp takes 1273 * priority. reg space should be properly set before read 1274 * YTPHY_SPECIFIC_STATUS_REG. 1275 */ 1276 1277 page &= YT8521_RSSR_SPACE_MASK; 1278 old_page = phy_select_page(phydev, page); 1279 if (old_page < 0) 1280 goto err_restore_page; 1281 1282 /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex 1283 * of the PHY is actually using. 1284 */ 1285 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 1286 if (ret < 0) 1287 goto err_restore_page; 1288 1289 status = ret; 1290 link = !!(status & YTPHY_SSR_LINK); 1291 1292 /* When PHY is in fiber mode, speed transferred from 1000Mbps to 1293 * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so 1294 * we need check MII_BMSR to identify such case. 1295 */ 1296 if (page == YT8521_RSSR_FIBER_SPACE) { 1297 ret = __phy_read(phydev, MII_BMSR); 1298 if (ret < 0) 1299 goto err_restore_page; 1300 1301 fiber_latch_val = ret; 1302 ret = __phy_read(phydev, MII_BMSR); 1303 if (ret < 0) 1304 goto err_restore_page; 1305 1306 fiber_curr_val = ret; 1307 if (link && fiber_latch_val != fiber_curr_val) { 1308 link = 0; 1309 phydev_info(phydev, 1310 "%s, fiber link down detect, latch = %04x, curr = %04x\n", 1311 __func__, fiber_latch_val, fiber_curr_val); 1312 } 1313 } else { 1314 /* Read autonegotiation status */ 1315 ret = __phy_read(phydev, MII_BMSR); 1316 if (ret < 0) 1317 goto err_restore_page; 1318 1319 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0; 1320 } 1321 1322 if (link) { 1323 if (page == YT8521_RSSR_UTP_SPACE) 1324 yt8521_adjust_status(phydev, status, true); 1325 else 1326 yt8521_adjust_status(phydev, status, false); 1327 } 1328 return phy_restore_page(phydev, old_page, link); 1329 1330err_restore_page: 1331 return phy_restore_page(phydev, old_page, ret); 1332} 1333 1334/** 1335 * yt8521_read_status() - determines the negotiated speed and duplex 1336 * @phydev: a pointer to a &struct phy_device 1337 * 1338 * returns 0 or negative errno code 1339 */ 1340static int yt8521_read_status(struct phy_device *phydev) 1341{ 1342 struct yt8521_priv *priv = phydev->priv; 1343 int link_fiber = 0; 1344 int link_utp; 1345 int link; 1346 int ret; 1347 1348 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1349 link = yt8521_read_status_paged(phydev, priv->reg_page); 1350 if (link < 0) 1351 return link; 1352 } else { 1353 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is 1354 * needed. by default, utp is higher priority. 1355 */ 1356 1357 link_utp = yt8521_read_status_paged(phydev, 1358 YT8521_RSSR_UTP_SPACE); 1359 if (link_utp < 0) 1360 return link_utp; 1361 1362 if (!link_utp) { 1363 link_fiber = yt8521_read_status_paged(phydev, 1364 YT8521_RSSR_FIBER_SPACE); 1365 if (link_fiber < 0) 1366 return link_fiber; 1367 } 1368 1369 link = link_utp || link_fiber; 1370 } 1371 1372 if (link) { 1373 if (phydev->link == 0) { 1374 /* arbitrate reg space based on linkup media type. */ 1375 if (priv->polling_mode == YT8521_MODE_POLL && 1376 priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 1377 if (link_fiber) 1378 priv->reg_page = 1379 YT8521_RSSR_FIBER_SPACE; 1380 else 1381 priv->reg_page = YT8521_RSSR_UTP_SPACE; 1382 1383 ret = ytphy_write_ext_with_lock(phydev, 1384 YT8521_REG_SPACE_SELECT_REG, 1385 priv->reg_page); 1386 if (ret < 0) 1387 return ret; 1388 1389 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP; 1390 1391 phydev_info(phydev, "%s, link up, media: %s\n", 1392 __func__, 1393 (phydev->port == PORT_TP) ? 1394 "UTP" : "Fiber"); 1395 } 1396 } 1397 phydev->link = 1; 1398 } else { 1399 if (phydev->link == 1) { 1400 phydev_info(phydev, "%s, link down, media: %s\n", 1401 __func__, (phydev->port == PORT_TP) ? 1402 "UTP" : "Fiber"); 1403 1404 /* When in YT8521_MODE_POLL mode, need prepare for next 1405 * arbitration. 1406 */ 1407 if (priv->polling_mode == YT8521_MODE_POLL) { 1408 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 1409 phydev->port = PORT_NONE; 1410 } 1411 } 1412 1413 phydev->link = 0; 1414 } 1415 1416 return 0; 1417} 1418 1419/** 1420 * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page 1421 * @phydev: the phy_device struct 1422 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate 1423 * @mask: bit mask of bits to clear 1424 * @set: bit mask of bits to set 1425 * 1426 * NOTE: Convenience function which allows a PHY's BMCR register to be 1427 * modified as new register value = (old register value & ~mask) | set. 1428 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 1429 * has MII_BMCR. poll mode combines utp and faber,so need do both. 1430 * If it is reset, it will wait for completion. 1431 * 1432 * returns 0 or negative errno code 1433 */ 1434static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page, 1435 u16 mask, u16 set) 1436{ 1437 int max_cnt = 500; /* the max wait time of reset ~ 500 ms */ 1438 int old_page; 1439 int ret = 0; 1440 1441 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 1442 if (old_page < 0) 1443 goto err_restore_page; 1444 1445 ret = __phy_modify(phydev, MII_BMCR, mask, set); 1446 if (ret < 0) 1447 goto err_restore_page; 1448 1449 /* If it is reset, need to wait for the reset to complete */ 1450 if (set == BMCR_RESET) { 1451 while (max_cnt--) { 1452 usleep_range(1000, 1100); 1453 ret = __phy_read(phydev, MII_BMCR); 1454 if (ret < 0) 1455 goto err_restore_page; 1456 1457 if (!(ret & BMCR_RESET)) 1458 return phy_restore_page(phydev, old_page, 0); 1459 } 1460 } 1461 1462err_restore_page: 1463 return phy_restore_page(phydev, old_page, ret); 1464} 1465 1466/** 1467 * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register 1468 * @phydev: the phy_device struct 1469 * @mask: bit mask of bits to clear 1470 * @set: bit mask of bits to set 1471 * 1472 * NOTE: Convenience function which allows a PHY's BMCR register to be 1473 * modified as new register value = (old register value & ~mask) | set. 1474 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 1475 * has MII_BMCR. poll mode combines utp and faber,so need do both. 1476 * 1477 * returns 0 or negative errno code 1478 */ 1479static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask, 1480 u16 set) 1481{ 1482 struct yt8521_priv *priv = phydev->priv; 1483 int ret; 1484 1485 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1486 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask, 1487 set); 1488 if (ret < 0) 1489 return ret; 1490 } else { 1491 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE, 1492 mask, set); 1493 if (ret < 0) 1494 return ret; 1495 1496 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE, 1497 mask, set); 1498 if (ret < 0) 1499 return ret; 1500 } 1501 return 0; 1502} 1503 1504/** 1505 * yt8521_soft_reset() - called to issue a PHY software reset 1506 * @phydev: a pointer to a &struct phy_device 1507 * 1508 * returns 0 or negative errno code 1509 */ 1510static int yt8521_soft_reset(struct phy_device *phydev) 1511{ 1512 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET); 1513} 1514 1515/** 1516 * yt8521_suspend() - suspend the hardware 1517 * @phydev: a pointer to a &struct phy_device 1518 * 1519 * returns 0 or negative errno code 1520 */ 1521static int yt8521_suspend(struct phy_device *phydev) 1522{ 1523 int wol_config; 1524 1525 /* YTPHY_WOL_CONFIG_REG is common ext reg */ 1526 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1527 if (wol_config < 0) 1528 return wol_config; 1529 1530 /* if wol enable, do nothing */ 1531 if (wol_config & YTPHY_WCR_ENABLE) 1532 return 0; 1533 1534 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN); 1535} 1536 1537/** 1538 * yt8521_resume() - resume the hardware 1539 * @phydev: a pointer to a &struct phy_device 1540 * 1541 * returns 0 or negative errno code 1542 */ 1543static int yt8521_resume(struct phy_device *phydev) 1544{ 1545 int ret; 1546 int wol_config; 1547 1548 /* disable auto sleep */ 1549 ret = ytphy_modify_ext_with_lock(phydev, 1550 YT8521_EXTREG_SLEEP_CONTROL1_REG, 1551 YT8521_ESC1R_SLEEP_SW, 0); 1552 if (ret < 0) 1553 return ret; 1554 1555 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1556 if (wol_config < 0) 1557 return wol_config; 1558 1559 /* if wol enable, do nothing */ 1560 if (wol_config & YTPHY_WCR_ENABLE) 1561 return 0; 1562 1563 return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); 1564} 1565 1566/** 1567 * yt8521_config_init() - called to initialize the PHY 1568 * @phydev: a pointer to a &struct phy_device 1569 * 1570 * returns 0 or negative errno code 1571 */ 1572static int yt8521_config_init(struct phy_device *phydev) 1573{ 1574 struct device_node *node = phydev->mdio.dev.of_node; 1575 int old_page; 1576 int ret = 0; 1577 1578 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 1579 if (old_page < 0) 1580 goto err_restore_page; 1581 1582 /* set rgmii delay mode */ 1583 if (phydev->interface != PHY_INTERFACE_MODE_SGMII) { 1584 ret = ytphy_rgmii_clk_delay_config(phydev); 1585 if (ret < 0) 1586 goto err_restore_page; 1587 } 1588 1589 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { 1590 /* disable auto sleep */ 1591 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, 1592 YT8521_ESC1R_SLEEP_SW, 0); 1593 if (ret < 0) 1594 goto err_restore_page; 1595 } 1596 1597 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { 1598 /* enable RXC clock when no wire plug */ 1599 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, 1600 YT8521_CGR_RX_CLK_EN, 0); 1601 if (ret < 0) 1602 goto err_restore_page; 1603 } 1604err_restore_page: 1605 return phy_restore_page(phydev, old_page, ret); 1606} 1607 1608static int yt8531_config_init(struct phy_device *phydev) 1609{ 1610 struct device_node *node = phydev->mdio.dev.of_node; 1611 int ret; 1612 1613 ret = ytphy_rgmii_clk_delay_config_with_lock(phydev); 1614 if (ret < 0) 1615 return ret; 1616 1617 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { 1618 /* disable auto sleep */ 1619 ret = ytphy_modify_ext_with_lock(phydev, 1620 YT8521_EXTREG_SLEEP_CONTROL1_REG, 1621 YT8521_ESC1R_SLEEP_SW, 0); 1622 if (ret < 0) 1623 return ret; 1624 } 1625 1626 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { 1627 /* enable RXC clock when no wire plug */ 1628 ret = ytphy_modify_ext_with_lock(phydev, 1629 YT8521_CLOCK_GATING_REG, 1630 YT8521_CGR_RX_CLK_EN, 0); 1631 if (ret < 0) 1632 return ret; 1633 } 1634 1635 ret = yt8531_set_ds(phydev); 1636 if (ret < 0) 1637 return ret; 1638 1639 return 0; 1640} 1641 1642/** 1643 * yt8531_link_change_notify() - Adjust the tx clock direction according to 1644 * the current speed and dts config. 1645 * @phydev: a pointer to a &struct phy_device 1646 * 1647 * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please 1648 * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not 1649 * JH7110. 1650 */ 1651static void yt8531_link_change_notify(struct phy_device *phydev) 1652{ 1653 struct device_node *node = phydev->mdio.dev.of_node; 1654 bool tx_clk_1000_inverted = false; 1655 bool tx_clk_100_inverted = false; 1656 bool tx_clk_10_inverted = false; 1657 bool tx_clk_adj_enabled = false; 1658 u16 val = 0; 1659 int ret; 1660 1661 if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled")) 1662 tx_clk_adj_enabled = true; 1663 1664 if (!tx_clk_adj_enabled) 1665 return; 1666 1667 if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted")) 1668 tx_clk_10_inverted = true; 1669 if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted")) 1670 tx_clk_100_inverted = true; 1671 if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted")) 1672 tx_clk_1000_inverted = true; 1673 1674 if (phydev->speed < 0) 1675 return; 1676 1677 switch (phydev->speed) { 1678 case SPEED_1000: 1679 if (tx_clk_1000_inverted) 1680 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1681 break; 1682 case SPEED_100: 1683 if (tx_clk_100_inverted) 1684 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1685 break; 1686 case SPEED_10: 1687 if (tx_clk_10_inverted) 1688 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1689 break; 1690 default: 1691 return; 1692 } 1693 1694 ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG, 1695 YT8521_RC1R_TX_CLK_SEL_INVERTED, val); 1696 if (ret < 0) 1697 phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret); 1698} 1699 1700/** 1701 * yt8521_prepare_fiber_features() - A small helper function that setup 1702 * fiber's features. 1703 * @phydev: a pointer to a &struct phy_device 1704 * @dst: a pointer to store fiber's features 1705 */ 1706static void yt8521_prepare_fiber_features(struct phy_device *phydev, 1707 unsigned long *dst) 1708{ 1709 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst); 1710 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst); 1711 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst); 1712 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst); 1713} 1714 1715/** 1716 * yt8521_fiber_setup_forced - configures/forces speed from @phydev 1717 * @phydev: target phy_device struct 1718 * 1719 * NOTE:The caller must have taken the MDIO bus lock. 1720 * 1721 * returns 0 or negative errno code 1722 */ 1723static int yt8521_fiber_setup_forced(struct phy_device *phydev) 1724{ 1725 u16 val; 1726 int ret; 1727 1728 if (phydev->speed == SPEED_1000) 1729 val = YTPHY_MCR_FIBER_1000BX; 1730 else if (phydev->speed == SPEED_100) 1731 val = YTPHY_MCR_FIBER_100FX; 1732 else 1733 return -EINVAL; 1734 1735 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 1736 if (ret < 0) 1737 return ret; 1738 1739 /* disable Fiber auto sensing */ 1740 ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 1741 YT8521_LTCR_EN_AUTOSEN, 0); 1742 if (ret < 0) 1743 return ret; 1744 1745 ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG, 1746 YTPHY_MCR_FIBER_SPEED_MASK, val); 1747 if (ret < 0) 1748 return ret; 1749 1750 return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 1751 YT8521_CCR_SW_RST, 0); 1752} 1753 1754/** 1755 * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation 1756 * @phydev: target phy_device struct 1757 * @restart: whether aneg restart is requested 1758 * 1759 * NOTE:The caller must have taken the MDIO bus lock. 1760 * 1761 * returns 0 or negative errno code 1762 */ 1763static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart) 1764{ 1765 int ret; 1766 1767 if (!restart) { 1768 /* Advertisement hasn't changed, but maybe aneg was never on to 1769 * begin with? Or maybe phy was isolated? 1770 */ 1771 ret = __phy_read(phydev, MII_BMCR); 1772 if (ret < 0) 1773 return ret; 1774 1775 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE)) 1776 restart = true; 1777 } 1778 /* Enable and Restart Autonegotiation 1779 * Don't isolate the PHY if we're negotiating 1780 */ 1781 if (restart) 1782 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, 1783 BMCR_ANENABLE | BMCR_ANRESTART); 1784 1785 return 0; 1786} 1787 1788/** 1789 * yt8521_fiber_config_aneg - restart auto-negotiation or write 1790 * YTPHY_MISC_CONFIG_REG. 1791 * @phydev: target phy_device struct 1792 * 1793 * NOTE:The caller must have taken the MDIO bus lock. 1794 * 1795 * returns 0 or negative errno code 1796 */ 1797static int yt8521_fiber_config_aneg(struct phy_device *phydev) 1798{ 1799 int err, changed = 0; 1800 int bmcr; 1801 u16 adv; 1802 1803 if (phydev->autoneg != AUTONEG_ENABLE) 1804 return yt8521_fiber_setup_forced(phydev); 1805 1806 /* enable Fiber auto sensing */ 1807 err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 1808 0, YT8521_LTCR_EN_AUTOSEN); 1809 if (err < 0) 1810 return err; 1811 1812 err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 1813 YT8521_CCR_SW_RST, 0); 1814 if (err < 0) 1815 return err; 1816 1817 bmcr = __phy_read(phydev, MII_BMCR); 1818 if (bmcr < 0) 1819 return bmcr; 1820 1821 /* When it is coming from fiber forced mode, add bmcr power down 1822 * and power up to let aneg work fine. 1823 */ 1824 if (!(bmcr & BMCR_ANENABLE)) { 1825 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); 1826 usleep_range(1000, 1100); 1827 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); 1828 } 1829 1830 adv = linkmode_adv_to_mii_adv_x(phydev->advertising, 1831 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 1832 1833 /* Setup fiber advertisement */ 1834 err = __phy_modify_changed(phydev, MII_ADVERTISE, 1835 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL | 1836 ADVERTISE_1000XPAUSE | 1837 ADVERTISE_1000XPSE_ASYM, 1838 adv); 1839 if (err < 0) 1840 return err; 1841 1842 if (err > 0) 1843 changed = 1; 1844 1845 return ytphy_check_and_restart_aneg(phydev, changed); 1846} 1847 1848/** 1849 * ytphy_setup_master_slave 1850 * @phydev: target phy_device struct 1851 * 1852 * NOTE: The caller must have taken the MDIO bus lock. 1853 * 1854 * returns 0 or negative errno code 1855 */ 1856static int ytphy_setup_master_slave(struct phy_device *phydev) 1857{ 1858 u16 ctl = 0; 1859 1860 if (!phydev->is_gigabit_capable) 1861 return 0; 1862 1863 switch (phydev->master_slave_set) { 1864 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 1865 ctl |= CTL1000_PREFER_MASTER; 1866 break; 1867 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 1868 break; 1869 case MASTER_SLAVE_CFG_MASTER_FORCE: 1870 ctl |= CTL1000_AS_MASTER; 1871 fallthrough; 1872 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1873 ctl |= CTL1000_ENABLE_MASTER; 1874 break; 1875 case MASTER_SLAVE_CFG_UNKNOWN: 1876 case MASTER_SLAVE_CFG_UNSUPPORTED: 1877 return 0; 1878 default: 1879 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1880 return -EOPNOTSUPP; 1881 } 1882 1883 return __phy_modify_changed(phydev, MII_CTRL1000, 1884 (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER | 1885 CTL1000_PREFER_MASTER), ctl); 1886} 1887 1888/** 1889 * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters 1890 * @phydev: target phy_device struct 1891 * 1892 * NOTE: Writes MII_ADVERTISE with the appropriate values, 1893 * after sanitizing the values to make sure we only advertise 1894 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement 1895 * hasn't changed, and > 0 if it has changed. 1896 * The caller must have taken the MDIO bus lock. 1897 * 1898 * returns 0 or negative errno code 1899 */ 1900static int ytphy_utp_config_advert(struct phy_device *phydev) 1901{ 1902 int err, bmsr, changed = 0; 1903 u32 adv; 1904 1905 /* Only allow advertising what this PHY supports */ 1906 linkmode_and(phydev->advertising, phydev->advertising, 1907 phydev->supported); 1908 1909 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 1910 1911 /* Setup standard advertisement */ 1912 err = __phy_modify_changed(phydev, MII_ADVERTISE, 1913 ADVERTISE_ALL | ADVERTISE_100BASE4 | 1914 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 1915 adv); 1916 if (err < 0) 1917 return err; 1918 if (err > 0) 1919 changed = 1; 1920 1921 bmsr = __phy_read(phydev, MII_BMSR); 1922 if (bmsr < 0) 1923 return bmsr; 1924 1925 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all 1926 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a 1927 * logical 1. 1928 */ 1929 if (!(bmsr & BMSR_ESTATEN)) 1930 return changed; 1931 1932 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1933 1934 err = __phy_modify_changed(phydev, MII_CTRL1000, 1935 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 1936 adv); 1937 if (err < 0) 1938 return err; 1939 if (err > 0) 1940 changed = 1; 1941 1942 return changed; 1943} 1944 1945/** 1946 * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR 1947 * @phydev: target phy_device struct 1948 * @changed: whether autoneg is requested 1949 * 1950 * NOTE: If auto-negotiation is enabled, we configure the 1951 * advertising, and then restart auto-negotiation. If it is not 1952 * enabled, then we write the BMCR. 1953 * The caller must have taken the MDIO bus lock. 1954 * 1955 * returns 0 or negative errno code 1956 */ 1957static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed) 1958{ 1959 int err; 1960 u16 ctl; 1961 1962 err = ytphy_setup_master_slave(phydev); 1963 if (err < 0) 1964 return err; 1965 else if (err) 1966 changed = true; 1967 1968 if (phydev->autoneg != AUTONEG_ENABLE) { 1969 /* configures/forces speed/duplex from @phydev */ 1970 1971 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex); 1972 1973 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK | 1974 BMCR_ISOLATE | BMCR_PDOWN), ctl); 1975 } 1976 1977 err = ytphy_utp_config_advert(phydev); 1978 if (err < 0) /* error */ 1979 return err; 1980 else if (err) 1981 changed = true; 1982 1983 return ytphy_check_and_restart_aneg(phydev, changed); 1984} 1985 1986/** 1987 * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg 1988 * of one page 1989 * @phydev: a pointer to a &struct phy_device 1990 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 1991 * operate. 1992 * 1993 * returns 0 or negative errno code 1994 */ 1995static int yt8521_config_aneg_paged(struct phy_device *phydev, int page) 1996{ 1997 __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported); 1998 struct yt8521_priv *priv = phydev->priv; 1999 int old_page; 2000 int ret = 0; 2001 2002 page &= YT8521_RSSR_SPACE_MASK; 2003 2004 old_page = phy_select_page(phydev, page); 2005 if (old_page < 0) 2006 goto err_restore_page; 2007 2008 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 2009 * phydev->advertising should be updated. 2010 */ 2011 if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 2012 linkmode_zero(fiber_supported); 2013 yt8521_prepare_fiber_features(phydev, fiber_supported); 2014 2015 /* prepare fiber_supported, then setup advertising. */ 2016 if (page == YT8521_RSSR_FIBER_SPACE) { 2017 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2018 fiber_supported); 2019 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2020 fiber_supported); 2021 linkmode_and(phydev->advertising, 2022 priv->combo_advertising, fiber_supported); 2023 } else { 2024 /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */ 2025 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2026 fiber_supported); 2027 linkmode_andnot(phydev->advertising, 2028 priv->combo_advertising, 2029 fiber_supported); 2030 } 2031 } 2032 2033 if (page == YT8521_RSSR_FIBER_SPACE) 2034 ret = yt8521_fiber_config_aneg(phydev); 2035 else 2036 ret = ytphy_utp_config_aneg(phydev, false); 2037 2038err_restore_page: 2039 return phy_restore_page(phydev, old_page, ret); 2040} 2041 2042/** 2043 * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged 2044 * @phydev: a pointer to a &struct phy_device 2045 * 2046 * returns 0 or negative errno code 2047 */ 2048static int yt8521_config_aneg(struct phy_device *phydev) 2049{ 2050 struct yt8521_priv *priv = phydev->priv; 2051 int ret; 2052 2053 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2054 ret = yt8521_config_aneg_paged(phydev, priv->reg_page); 2055 if (ret < 0) 2056 return ret; 2057 } else { 2058 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 2059 * phydev->advertising need to be saved at first run. 2060 * Because it contains the advertising which supported by both 2061 * mac and yt8521(utp and fiber). 2062 */ 2063 if (linkmode_empty(priv->combo_advertising)) { 2064 linkmode_copy(priv->combo_advertising, 2065 phydev->advertising); 2066 } 2067 2068 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE); 2069 if (ret < 0) 2070 return ret; 2071 2072 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE); 2073 if (ret < 0) 2074 return ret; 2075 2076 /* we don't known which will be link, so restore 2077 * phydev->advertising as default value. 2078 */ 2079 linkmode_copy(phydev->advertising, priv->combo_advertising); 2080 } 2081 return 0; 2082} 2083 2084/** 2085 * yt8521_aneg_done_paged() - determines the auto negotiation result of one 2086 * page. 2087 * @phydev: a pointer to a &struct phy_device 2088 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2089 * operate. 2090 * 2091 * returns 0(no link)or 1(fiber or utp link) or negative errno code 2092 */ 2093static int yt8521_aneg_done_paged(struct phy_device *phydev, int page) 2094{ 2095 int old_page; 2096 int ret = 0; 2097 int link; 2098 2099 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 2100 if (old_page < 0) 2101 goto err_restore_page; 2102 2103 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 2104 if (ret < 0) 2105 goto err_restore_page; 2106 2107 link = !!(ret & YTPHY_SSR_LINK); 2108 ret = link; 2109 2110err_restore_page: 2111 return phy_restore_page(phydev, old_page, ret); 2112} 2113 2114/** 2115 * yt8521_aneg_done() - determines the auto negotiation result 2116 * @phydev: a pointer to a &struct phy_device 2117 * 2118 * returns 0(no link)or 1(fiber or utp link) or negative errno code 2119 */ 2120static int yt8521_aneg_done(struct phy_device *phydev) 2121{ 2122 struct yt8521_priv *priv = phydev->priv; 2123 int link_fiber = 0; 2124 int link_utp; 2125 int link; 2126 2127 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2128 link = yt8521_aneg_done_paged(phydev, priv->reg_page); 2129 } else { 2130 link_utp = yt8521_aneg_done_paged(phydev, 2131 YT8521_RSSR_UTP_SPACE); 2132 if (link_utp < 0) 2133 return link_utp; 2134 2135 if (!link_utp) { 2136 link_fiber = yt8521_aneg_done_paged(phydev, 2137 YT8521_RSSR_FIBER_SPACE); 2138 if (link_fiber < 0) 2139 return link_fiber; 2140 } 2141 link = link_fiber || link_utp; 2142 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n", 2143 __func__, link_fiber, link_utp); 2144 } 2145 2146 return link; 2147} 2148 2149/** 2150 * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers 2151 * @phydev: target phy_device struct 2152 * 2153 * NOTE: Reads the PHY's abilities and populates 2154 * phydev->supported accordingly. 2155 * The caller must have taken the MDIO bus lock. 2156 * 2157 * returns 0 or negative errno code 2158 */ 2159static int ytphy_utp_read_abilities(struct phy_device *phydev) 2160{ 2161 int val; 2162 2163 linkmode_set_bit_array(phy_basic_ports_array, 2164 ARRAY_SIZE(phy_basic_ports_array), 2165 phydev->supported); 2166 2167 val = __phy_read(phydev, MII_BMSR); 2168 if (val < 0) 2169 return val; 2170 2171 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported, 2172 val & BMSR_ANEGCAPABLE); 2173 2174 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported, 2175 val & BMSR_100FULL); 2176 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported, 2177 val & BMSR_100HALF); 2178 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported, 2179 val & BMSR_10FULL); 2180 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported, 2181 val & BMSR_10HALF); 2182 2183 if (val & BMSR_ESTATEN) { 2184 val = __phy_read(phydev, MII_ESTATUS); 2185 if (val < 0) 2186 return val; 2187 2188 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2189 phydev->supported, val & ESTATUS_1000_TFULL); 2190 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 2191 phydev->supported, val & ESTATUS_1000_THALF); 2192 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2193 phydev->supported, val & ESTATUS_1000_XFULL); 2194 } 2195 2196 return 0; 2197} 2198 2199/** 2200 * yt8521_get_features_paged() - read supported link modes for one page 2201 * @phydev: a pointer to a &struct phy_device 2202 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2203 * operate. 2204 * 2205 * returns 0 or negative errno code 2206 */ 2207static int yt8521_get_features_paged(struct phy_device *phydev, int page) 2208{ 2209 int old_page; 2210 int ret = 0; 2211 2212 page &= YT8521_RSSR_SPACE_MASK; 2213 old_page = phy_select_page(phydev, page); 2214 if (old_page < 0) 2215 goto err_restore_page; 2216 2217 if (page == YT8521_RSSR_FIBER_SPACE) { 2218 linkmode_zero(phydev->supported); 2219 yt8521_prepare_fiber_features(phydev, phydev->supported); 2220 } else { 2221 ret = ytphy_utp_read_abilities(phydev); 2222 if (ret < 0) 2223 goto err_restore_page; 2224 } 2225 2226err_restore_page: 2227 return phy_restore_page(phydev, old_page, ret); 2228} 2229 2230/** 2231 * yt8521_get_features - switch reg space then call yt8521_get_features_paged 2232 * @phydev: target phy_device struct 2233 * 2234 * returns 0 or negative errno code 2235 */ 2236static int yt8521_get_features(struct phy_device *phydev) 2237{ 2238 struct yt8521_priv *priv = phydev->priv; 2239 int ret; 2240 2241 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2242 ret = yt8521_get_features_paged(phydev, priv->reg_page); 2243 } else { 2244 ret = yt8521_get_features_paged(phydev, 2245 YT8521_RSSR_UTP_SPACE); 2246 if (ret < 0) 2247 return ret; 2248 2249 /* add fiber's features to phydev->supported */ 2250 yt8521_prepare_fiber_features(phydev, phydev->supported); 2251 } 2252 return ret; 2253} 2254 2255static struct phy_driver motorcomm_phy_drvs[] = { 2256 { 2257 PHY_ID_MATCH_EXACT(PHY_ID_YT8511), 2258 .name = "YT8511 Gigabit Ethernet", 2259 .config_init = yt8511_config_init, 2260 .suspend = genphy_suspend, 2261 .resume = genphy_resume, 2262 .read_page = yt8511_read_page, 2263 .write_page = yt8511_write_page, 2264 }, 2265 { 2266 PHY_ID_MATCH_EXACT(PHY_ID_YT8521), 2267 .name = "YT8521 Gigabit Ethernet", 2268 .get_features = yt8521_get_features, 2269 .probe = yt8521_probe, 2270 .read_page = yt8521_read_page, 2271 .write_page = yt8521_write_page, 2272 .get_wol = ytphy_get_wol, 2273 .set_wol = ytphy_set_wol, 2274 .config_aneg = yt8521_config_aneg, 2275 .aneg_done = yt8521_aneg_done, 2276 .config_init = yt8521_config_init, 2277 .read_status = yt8521_read_status, 2278 .soft_reset = yt8521_soft_reset, 2279 .suspend = yt8521_suspend, 2280 .resume = yt8521_resume, 2281 }, 2282 { 2283 PHY_ID_MATCH_EXACT(PHY_ID_YT8531), 2284 .name = "YT8531 Gigabit Ethernet", 2285 .probe = yt8531_probe, 2286 .config_init = yt8531_config_init, 2287 .suspend = genphy_suspend, 2288 .resume = genphy_resume, 2289 .get_wol = ytphy_get_wol, 2290 .set_wol = yt8531_set_wol, 2291 .link_change_notify = yt8531_link_change_notify, 2292 }, 2293 { 2294 PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), 2295 .name = "YT8531S Gigabit Ethernet", 2296 .get_features = yt8521_get_features, 2297 .probe = yt8521_probe, 2298 .read_page = yt8521_read_page, 2299 .write_page = yt8521_write_page, 2300 .get_wol = ytphy_get_wol, 2301 .set_wol = ytphy_set_wol, 2302 .config_aneg = yt8521_config_aneg, 2303 .aneg_done = yt8521_aneg_done, 2304 .config_init = yt8521_config_init, 2305 .read_status = yt8521_read_status, 2306 .soft_reset = yt8521_soft_reset, 2307 .suspend = yt8521_suspend, 2308 .resume = yt8521_resume, 2309 }, 2310}; 2311 2312module_phy_driver(motorcomm_phy_drvs); 2313 2314MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S PHY driver"); 2315MODULE_AUTHOR("Peter Geis"); 2316MODULE_AUTHOR("Frank"); 2317MODULE_LICENSE("GPL"); 2318 2319static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { 2320 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, 2321 { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) }, 2322 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) }, 2323 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) }, 2324 { /* sentinel */ } 2325}; 2326 2327MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); 2328